X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=cole.mdwn;h=dbc8a7154dd5481205f031e9b32afde2293c4d1f;hb=bd48c5aba9b9806659ad545fd164a7bb28544b45;hp=00a2fcc02bbd978e601d65c76d3b4a61d784ab99;hpb=34cdd0d6e3dd2e756b63186c76f1cefc554e67e1;p=libreriscv.git diff --git a/cole.mdwn b/cole.mdwn index 00a2fcc02..dbc8a7154 100644 --- a/cole.mdwn +++ b/cole.mdwn @@ -10,6 +10,18 @@ move things along from one stage to the next ## Currently working on +- Reach out to lu_zero of Gentoo about SV POWER binutils +- Script and document the setup and installation of microwatt dependency on the wiki-HDL_workflow page +- MUL tests + - shared with lkcl +- Write VHDL to expose CR and XER from Microwatt so single-stepping is possible + - shared with lkcl +- Create I-Cache from microwatt icache.vhdl + - shared with lkcl +- Create D-cache from microwatt dcache.vhdl + - shared with lkcl +- Create MMU from microwatt mmu.vhdl + - shared with lkcl - Recruiting more engineers to the project - First round of recruitment attempts - Create wiki page for recruitment emails to point to @@ -17,7 +29,6 @@ move things along from one stage to the next - Create bug report for each diagram to be converted to SVG - Contact 'BlackParrot' RV64GC Multicore SoC devs - Convert comp_unit_req_rel diagram to SVG -- MUL Pipeline unit tests ## List of things that need more fleshed out bug reports: @@ -31,22 +42,47 @@ move things along from one stage to the next ## Completed but not yet submitted -- Convert 180nm Test ASIC Mem Layout diagram to SVG +## Submitted for NLNet RFP -- Coriolis2 documentation and setup scripts - - - - - - - - - - +submitted but not confirmed paid: -- TRAP pipeline discussion - - +## Paid -## Submitted for NLNet RFP +### MOU coriolis2 2019-10-029, received payment on 2021-MAY-5 -submitted but not confirmed paid: +- determine SRAM block size and implement it + - EUR 50 -### Project 2019-02-012 Date {TEMPLATE INSERT DATE} +### MOU wishbone 2019-10-043, received payment on 2021-MAY-5 -## Paid +- DMI JTAG TAP needed + - EUR 150 + +### MOU coriolis2 2019-10-029, received payment on 2020-DEC-20 + +- Coriolis2 tutorial + - EUR 500 + +### MOU wishbone 2019-10-043, received payment on 2020-OCT-01 + +- Convert 180nm Test ASIC Mem Layout diagram to SVG + - EUR 150 + +- Adding nmigen-soc as a dependency needs documentation updated + - EUR 100 + +- Tutorial and dev page needed for mesa driver + - EUR 100 + +- Trap pipe discussion + - EUR 500. shared. lkcl (60%, EUR 300), cole (20%, EUR 100), samuel (20%, EUR 100) + +- Virtual Regfile port + - EUR 200. shared, lkcl (50%, EUR 100), cole (50%, EUR 100) + +### MOU coriolis2 2019-10-029, received payment on 2020-OCT-01 + +- Coriolis2 documentation and setup scripts, (documentation budget, EUR 200) + - + - + -