X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=cole.mdwn;h=dbc8a7154dd5481205f031e9b32afde2293c4d1f;hb=bd48c5aba9b9806659ad545fd164a7bb28544b45;hp=5026a7371d92ebb95112f248226c35e7b6842c05;hpb=e06312102c74331988210bef4edbfe6f71f7bcef;p=libreriscv.git diff --git a/cole.mdwn b/cole.mdwn index 5026a7371..dbc8a7154 100644 --- a/cole.mdwn +++ b/cole.mdwn @@ -11,7 +11,6 @@ move things along from one stage to the next ## Currently working on - Reach out to lu_zero of Gentoo about SV POWER binutils -- Complete first functional POWER9 Core - Script and document the setup and installation of microwatt dependency on the wiki-HDL_workflow page - MUL tests - shared with lkcl @@ -43,12 +42,31 @@ move things along from one stage to the next ## Completed but not yet submitted -- Convert 180nm Test ASIC Mem Layout diagram to SVG +## Submitted for NLNet RFP -- Coriolis2 documentation and setup scripts, (documentation budget, EUR 200) - - - - - - +submitted but not confirmed paid: + +## Paid + +### MOU coriolis2 2019-10-029, received payment on 2021-MAY-5 + +- determine SRAM block size and implement it + - EUR 50 + +### MOU wishbone 2019-10-043, received payment on 2021-MAY-5 + +- DMI JTAG TAP needed + - EUR 150 + +### MOU coriolis2 2019-10-029, received payment on 2020-DEC-20 + +- Coriolis2 tutorial + - EUR 500 + +### MOU wishbone 2019-10-043, received payment on 2020-OCT-01 + +- Convert 180nm Test ASIC Mem Layout diagram to SVG + - EUR 150 - Adding nmigen-soc as a dependency needs documentation updated - EUR 100 @@ -62,11 +80,9 @@ move things along from one stage to the next - Virtual Regfile port - EUR 200. shared, lkcl (50%, EUR 100), cole (50%, EUR 100) +### MOU coriolis2 2019-10-029, received payment on 2020-OCT-01 -## Submitted for NLNet RFP - -submitted but not confirmed paid: - -### Project 2019-02-012 Date {TEMPLATE INSERT DATE} - -## Paid +- Coriolis2 documentation and setup scripts, (documentation budget, EUR 200) + - + - + -