X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=common.mk;fp=common.mk;h=359e22097fe0584013f04173a732a31a748dd967;hb=62d4e3ee158440a94f9deb9c57562a805acddaf0;hp=e09cc29a1483485a241437d929269f8dfcf2a3f9;hpb=275e2cd69316e81e59ce5270928dadf90328beb8;p=freedom-sifive.git

diff --git a/common.mk b/common.mk
index e09cc29..359e220 100644
--- a/common.mk
+++ b/common.mk
@@ -30,8 +30,7 @@ $(FIRRTL_JAR): $(shell find $(rocketchip_dir)/firrtl/src/main/scala -iname "*.sc
 
 # Build .fir
 firrtl := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).fir
-firrtl_prm := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).prm
-$(firrtl) $(firrtl_prm): $(shell find $(base_dir)/src/main/scala -name '*.scala') $(FIRRTL_JAR)
+$(firrtl): $(shell find $(base_dir)/src/main/scala -name '*.scala') $(FIRRTL_JAR)
 	mkdir -p $(dir $@)
 	$(SBT) "run-main rocketchip.Generator $(BUILD_DIR) $(PROJECT) $(MODEL) $(CONFIG_PROJECT) $(CONFIG)"
 
@@ -47,20 +46,13 @@ ifneq ($(PATCHVERILOG),"")
 endif
 
 
-verilog_consts_vh := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).vh
-$(verilog_consts_vh): $(firrtl_prm)
-	echo "\`ifndef CONST_VH" > $@
-	echo "\`define CONST_VH" >> $@
-	sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/`define \1 \2/' $< >> $@
-	echo "\`endif // CONST_VH" >> $@
-
 .PHONY: verilog
-verilog: $(verilog) $(verilog_consts_vh)
+verilog: $(verilog)
 
 # Build .mcs
 mcs := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).mcs
-$(mcs): $(verilog) $(verilog_consts_vh)
-	VSRC_TOP=$(verilog) VSRC_CONSTS=$(verilog_consts_vh) EXTRA_VSRCS="$(EXTRA_FPGA_VSRCS)" $(MAKE) -C $(FPGA_DIR) mcs
+$(mcs): $(verilog)
+	VSRC_TOP=$(verilog) EXTRA_VSRCS="$(EXTRA_FPGA_VSRCS)" $(MAKE) -C $(FPGA_DIR) mcs
 	cp $(FPGA_DIR)/obj/system.mcs $@
 
 .PHONY: mcs