X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=conferences%2Ffosdem2024%2Ffosdem2024_bigint%2Ffosdem2024_bigint.tex;h=832a8843014b557504a22191e8735c13abab7ae0;hb=759c93b3e344284c2afc873aa4a60a17e86ef184;hp=c6660d599524468df1411a5521547d9f23566d8c;hpb=112d5247fa47aa15e039510263e5a74c9ee856d9;p=libreriscv.git

diff --git a/conferences/fosdem2024/fosdem2024_bigint/fosdem2024_bigint.tex b/conferences/fosdem2024/fosdem2024_bigint/fosdem2024_bigint.tex
index c6660d599..832a88430 100644
--- a/conferences/fosdem2024/fosdem2024_bigint/fosdem2024_bigint.tex
+++ b/conferences/fosdem2024/fosdem2024_bigint/fosdem2024_bigint.tex
@@ -1,12 +1,12 @@
 % Copyright 2024 Jacob Lifshay
 
-\documentclass[slidestop]{beamer}
+\documentclass{beamer}
 \usepackage{beamerthemesplit}
 \usetheme{default}
 \usepackage[english]{babel}
 \usepackage{tikz}
 
-\title[]{
+\title[Fast Big-Integer Arithmetic on SVP64 ...]{
     Fast Big-Integer Arithmetic on SVP64 at up to 256-bits/cycle and beyond
 }
 
@@ -22,6 +22,56 @@
     \titlepage
 \end{frame}
 
+\begin{frame}[fragile]
+    \frametitle{What is SVP64?}
+    \begin{itemize}
+        \item Vectorization Extension for PowerISA developed by \href{https://libre-soc.org}{Libre-SOC}
+        \pause
+        \item Basically, a way to modify nearly any PowerISA instruction to run it in a HW loop.
+        \pause \\
+        \medskip
+        Simple Example:
+        \begin{semiverbatim}
+setvl 0, 0, 3, 0, 1, 1 # makes stuff run 3 times
+sv.add *r3, *r15, r12  # adds 3 times
+\pause
+# expands to:
+add r3, r15, r12  \only<+(1)->{# no * means r12 doesn't increment}
+add r4, r16, r12  \only<+(1)->{# * means r3 and r15 increment}
+add r5, r17, r12
+        \end{semiverbatim}
+    \end{itemize}
+\end{frame}
+
+\begin{frame}[fragile]
+    \frametitle{Big-Integer Addition on SVP64}
+    How can we use SVP64 to add 256-bit integers?
+    \pause
+    \begin{semiverbatim}
+setvl 0, 0, 4, 0, 1, 1 # makes stuff run 4 times
+addic 0, 0, 0  # clear CA (carry flag)
+sv.adde *r4, *r4, *r8  # carry-propagating add
+\pause
+# expands to:
+addic 0, 0, 0  # clear CA (carry flag)
+adde r4, r4, r8
+adde r5, r5, r9
+adde r6, r6, r10
+adde r6, r6, r11
+    \end{semiverbatim}
+\end{frame}
+
+\begin{frame}
+    \frametitle{Big-Integer Addition on an example CPU}
+    Disclaimer:
+    SVP64 is designed for everything from tiny to big and fast CPUs, this example only shows a hypothetical big and fast CPU design
+\end{frame}
+
+\begin{frame}
+    \frametitle{Big-Integer Addition on an example CPU}
+    \input{bigint-add-pipe.dia-tex}
+\end{frame}
+
 \begin{frame}
     \input{test.dia-tex}
 \end{frame}