X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=conferences.mdwn;h=284358e5716af5b202720cd6958768c1d2d78877;hb=22c8f20820294718e9c325009ea318d40748409c;hp=8517c6ad37e34f0c73c2627533b7db995d89c3ed;hpb=6978d02ac81af16aee8af1ad38c090e32f8de93e;p=libreriscv.git

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 * <http://sfscon.it/> - Roberto PPC64 Notebook
 * <https://www.sfscon.it/talks/202x-open-hardware-concrete-approach/>
+* [[conferences/sfscon2020]]
+
+
+# FOSDEM 2021 OpenPOWER
+
+TODO
+
+* <https://penta.fosdem.org/submission/FOSDEM21/events>
+* <https://lists.fosdem.org/pipermail/fosdem/2020q4/003123.html>
+* <https://fosdem.org/2021/schedule/tracks/>
+* Main LibreSOC talk - part done abstract
+* nmigen-related tech - mostly done abstract
+* SimpleV talk - mostly done absteact
+* Vulkan / Kazan - TODO
+* other?
+
+# LinuxConf 2021
+
+* <https://lca2021.linux.org.au/schedule/presentation/78/>
+
+# Europython 2021
+
+march for CfP
+
+* <https://ep2021.europython.eu/faq/#nodes>
 
-## Why a Libre 3D CPU / GPU / VPU?
-
-* Study of SoCs (Allwinner, Rockchip, NXP) shows none are fully Libre
-  - Either GPU driver firmware is proprietary, or VPU firmware, or bootloader
-* This causes customer product development issues
-  - https://tinyurl.com/valve-steam-intel
-* Businesses are waking up to lack of transparency
-  - Intel Management Engine (spying backdoor co-processor)
-  - Spectre, Meltdown, CSME (Chain-of-Trust) issues
-* Solution: full transparency.  All source available for everything.
-
-## How is LibreSOC being developed?
-
-* Using Libre (rather than "open") development practices
-  - no "I'll release it when it's ready": all development is real-time public access
-* No NDAs, no hidden discussions
-  - we can invite anyone (any expert) to help with review
-  - free to ask for help anywhere in the world (comp.arch, stackexchange)
-* Using litex, nmigen, opencores HDL
-  - heavily depending on python OO (not possible with VHDL or Verilog)
-  - leap-frogging ahead by not reinventing the wheel
-  - yosys converts nmigen to verilog for standard tools.
-
-## Why is it different from other SoCs?
-
-* LibreSOC is a hybrid CPU-VPU-GPU architecture.
-  - OpenPOWER ISA *itself* is extended to include 3D and Video instructions
-  - (SIN, ATAN2, YUV2RGB, Texture Interpolation)
-  - Only after approval of OpenPOWER Foundation!
-  - There is no separate GPU or VPU: it really is the same core.
-  - Massively simplifies driver development and application debugging
-* Vectorisation is "Simple-V" (VSX not being implemented)
-  - VSX is SIMD and is considered harmful
-  - https://www.sigarch.org/simd-instructions-considered-harmful/
-
-
-## What is being developed? (Roadmap)
-
-* First simple core achieved in simulation Sep 2020
-  - FPGA (ECP5) target followed shortly
-* First silicon tape-out 180nm deadline 2nd Dec 2020
-  - sponsored by NLnet, with help from Chips4Makers Libre Cell Libraries
-  - layout is entirely libre-licensed tools: coriolis2 from lip6.fr
-* Next chip is "SBC" style quad-core
-  - similar spec to Allwinner A64, Rockchip RK3399
-  - targets "Pi" boards, smartphones, tablets, Industrial IoT
-
-## Contact
-
-* Freenode IRC #libre-soc
-* Website https://libre-soc.org
-  - mailing list, git repos, bugtracker etc.