X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=configs%2Fcommon%2Fcpu2000.py;h=443399234a51d20cc5dde5b5996dad941e0219a7;hb=f85286b3debf4a4a94d3b959e5bb880be81bd692;hp=f6c7a164f7649ab236febeb6b803da798ab7b19b;hpb=9b66e8289781025bbc4d0e152737fa7c5d024ec8;p=gem5.git

diff --git a/configs/common/cpu2000.py b/configs/common/cpu2000.py
index f6c7a164f..443399234 100644
--- a/configs/common/cpu2000.py
+++ b/configs/common/cpu2000.py
@@ -155,7 +155,7 @@ class Benchmark(object):
         cwd = process_args.get('cwd')
 
         if not cwd:
-            from m5.main import options
+            from m5 import options
             cwd = options.outdir
             process_args['cwd'] = cwd
         if not isdir(cwd):
@@ -663,7 +663,7 @@ class vortex(Benchmark):
     stdin = None
 
     def __init__(self, isa, os, input_set):
-        if isa == 'alpha':
+        if (isa == 'alpha' or isa == 'arm'):
             self.endian = 'lendian'
         elif (isa == 'sparc' or isa == 'sparc32'):
             self.endian = 'bendian'
@@ -731,7 +731,7 @@ class vpr_route(vpr):
              '-first_iter_pres_fac', '4', '-initial_pres_fac', '8' ]
     output = 'route_log.out'
 
-all = [ ammp, applu, apsi, art110, art470, equake, facerec, fma3d, galgel,
+all = [ ammp, applu, apsi, art, art110, art470, equake, facerec, fma3d, galgel,
         lucas, mesa, mgrid, sixtrack, swim, wupwise, bzip2_source,
         bzip2_graphic, bzip2_program, crafty, eon_kajiya, eon_cook,
         eon_rushmeier, gap, gcc_166, gcc_200, gcc_expr, gcc_integrate,