X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=configs%2Fdram%2Fsweep.py;h=a340b46a5821ffd85855ded38b4b1d44db927790;hb=e2a510acefac357d83754369e6abd3e79db5d904;hp=385708e602263f677b5bd6e89491e4ec4e692546;hpb=4c4520ca00fd5ca87bba31544442cbb5e2db1df5;p=gem5.git

diff --git a/configs/dram/sweep.py b/configs/dram/sweep.py
index 385708e60..a340b46a5 100644
--- a/configs/dram/sweep.py
+++ b/configs/dram/sweep.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2014-2015, 2018-2019 ARM Limited
+# Copyright (c) 2014-2015, 2018-2020 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -32,8 +32,6 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Andreas Hansson
 
 from __future__ import print_function
 from __future__ import absolute_import
@@ -48,6 +46,7 @@ from m5.stats import periodicStatDump
 
 addToPath('../')
 
+from common import ObjectList
 from common import MemConfig
 
 # this script is helpful to sweep the efficiency of a specific memory
@@ -64,7 +63,7 @@ dram_generators = {
 
 # Use a single-channel DDR3-1600 x64 (8x8 topology) by default
 parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8",
-                  choices=MemConfig.mem_names(),
+                  choices=ObjectList.mem_list.get_names(),
                   help = "type of memory to use")
 
 parser.add_option("--mem-ranks", "-r", type="int", default=1,
@@ -74,13 +73,13 @@ parser.add_option("--rd_perc", type="int", default=100,
                   help = "Percentage of read commands")
 
 parser.add_option("--mode", type="choice", default="DRAM",
-                  choices=dram_generators.keys(),
+                  choices=list(dram_generators.keys()),
                   help = "DRAM: Random traffic; \
                           DRAM_ROTATE: Traffic rotating across banks and ranks")
 
-parser.add_argument("--addr-map",
-                    choices=m5.objects.AddrMap.vals,
-                    default="RoRaBaCoCh", help = "DRAM address map policy")
+parser.add_option("--addr-map", type="choice",
+                  choices=ObjectList.dram_addr_map_list.get_names(),
+                  default="RoRaBaCoCh", help = "DRAM address map policy")
 
 (options, args) = parser.parse_args()
 
@@ -123,7 +122,7 @@ if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl):
 system.mem_ctrls[0].null = True
 
 # Set the address mapping based on input argument
-system.mem_ctrls[0].addr_mapping = args.addr_map
+system.mem_ctrls[0].addr_mapping = options.addr_map
 
 # stay in each state for 0.25 ms, long enough to warm things up, and
 # short enough to avoid hitting a refresh
@@ -147,7 +146,8 @@ page_size = system.mem_ctrls[0].devices_per_rank.value * \
 
 # match the maximum bandwidth of the memory, the parameter is in seconds
 # and we need it in ticks (ps)
-itt = system.mem_ctrls[0].tBURST.value * 1000000000000
+itt =  getattr(system.mem_ctrls[0].tBURST_MIN, 'value',
+               system.mem_ctrls[0].tBURST.value) * 1000000000000
 
 # assume we start at 0
 max_addr = mem_range.end
@@ -178,12 +178,11 @@ root.system.mem_mode = 'timing'
 
 m5.instantiate()
 
-addr_map = m5.objects.AddrMap.map[args.addr_map]
-
 def trace():
+    addr_map = ObjectList.dram_addr_map_list.get(options.addr_map)
     generator = dram_generators[options.mode](system.tgen)
-    for bank in range(1, nbr_banks + 1):
-        for stride_size in range(burst_size, max_stride + 1, burst_size):
+    for stride_size in range(burst_size, max_stride + 1, burst_size):
+        for bank in range(1, nbr_banks + 1):
             num_seq_pkts = int(math.ceil(float(stride_size) / burst_size))
             yield generator(period,
                             0, max_addr, burst_size, int(itt), int(itt),
@@ -196,5 +195,5 @@ system.tgen.start(trace())
 
 m5.simulate()
 
-print("DRAM sweep with burst: %d, banks: %d, max stride: %d" %
-    (burst_size, nbr_banks, max_stride))
+print("DRAM sweep with burst: %d, banks: %d, max stride: %d, request \
+       generation period: %d" % (burst_size, nbr_banks, max_stride, itt))