X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=configs%2Fexample%2Fse.py;h=1edd99e9b6bea6bc0edf9b399116c26f953af1a0;hb=d7f71bf424f2ccb87366b4f464e657a185abe414;hp=b294480f64d4bd9f6e5e697414a82c1b949038b8;hpb=a13d5af274a1847eaad649af226e643e86a3322d;p=gem5.git diff --git a/configs/example/se.py b/configs/example/se.py index b294480f6..1edd99e9b 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -1,4 +1,16 @@ -# Copyright (c) 2006-2007 The Regents of The University of Michigan +# Copyright (c) 2012 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Copyright (c) 2006-2008 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -30,12 +42,25 @@ # # "m5 test.py" +import os +import optparse +import sys +from os.path import join as joinpath + import m5 +from m5.defines import buildEnv from m5.objects import * -import os, optparse, sys -m5.AddToPath('../common') +from m5.util import addToPath, fatal + +addToPath('../common') +addToPath('../ruby') + +import Ruby + import Simulation +import CacheConfig from Caches import * +from cpu2000 import * # Get paths we might need. It's expected this file is in m5/configs/example. config_path = os.path.dirname(os.path.abspath(__file__)) @@ -46,38 +71,82 @@ parser = optparse.OptionParser() # Benchmark options parser.add_option("-c", "--cmd", - default=os.path.join(m5_root, "tests/test-progs/hello/bin/alpha/linux/hello"), - help="The binary to run in syscall emulation mode.") + default=joinpath(m5_root, "tests/test-progs/hello/bin/%s/linux/hello" % \ + buildEnv['TARGET_ISA']), + help="The binary to run in syscall emulation mode.") parser.add_option("-o", "--options", default="", - help="The options to pass to the binary, use \" \" around the entire\ - string.") -parser.add_option("-i", "--input", default="", - help="A file of input to give to the binary.") + help='The options to pass to the binary, use " " around the entire string') +parser.add_option("-i", "--input", default="", help="Read stdin from a file.") +parser.add_option("--output", default="", help="Redirect stdout to a file.") +parser.add_option("--errout", default="", help="Redirect stderr to a file.") execfile(os.path.join(config_root, "common", "Options.py")) +if buildEnv['PROTOCOL'] != 'None': + parser.add_option("--ruby", action="store_true") + if '--ruby' in sys.argv: + Ruby.define_options(parser) + (options, args) = parser.parse_args() if args: print "Error: script doesn't take any positional arguments" sys.exit(1) -process = LiveProcess() -process.executable = options.cmd -process.cmd = options.cmd + " " + options.options +multiprocesses = [] +apps = [] + +if options.bench: + apps = options.bench.split("-") + if len(apps) != options.num_cpus: + print "number of benchmarks not equal to set num_cpus!" + sys.exit(1) + + for app in apps: + try: + if buildEnv['TARGET_ISA'] == 'alpha': + exec("workload = %s('alpha', 'tru64', 'ref')" % app) + else: + exec("workload = %s(buildEnv['TARGET_ISA'], 'linux', 'ref')" % app) + multiprocesses.append(workload.makeLiveProcess()) + except: + print >>sys.stderr, "Unable to find workload for %s: %s" % (buildEnv['TARGET_ISA'], app) + sys.exit(1) +else: + process = LiveProcess() + process.executable = options.cmd + process.cmd = [options.cmd] + options.options.split() + multiprocesses.append(process) + + if options.input != "": process.input = options.input +if options.output != "": + process.output = options.output +if options.errout != "": + process.errout = options.errout + -if options.detailed: +# By default, set workload to path of user-specified binary +workloads = options.cmd +numThreads = 1 + +if options.cpu_type == "detailed" or options.cpu_type == "inorder": #check for SMT workload workloads = options.cmd.split(';') if len(workloads) > 1: process = [] smt_idx = 0 inputs = [] + outputs = [] + errouts = [] if options.input != "": inputs = options.input.split(';') + if options.output != "": + outputs = options.output.split(';') + if options.errout != "": + errouts = options.errout.split(';') for wrkld in workloads: smt_process = LiveProcess() @@ -85,12 +154,22 @@ if options.detailed: smt_process.cmd = wrkld + " " + options.options if inputs and inputs[smt_idx]: smt_process.input = inputs[smt_idx] + if outputs and outputs[smt_idx]: + smt_process.output = outputs[smt_idx] + if errouts and errouts[smt_idx]: + smt_process.errout = errouts[smt_idx] process += [smt_process, ] smt_idx += 1 + numThreads = len(workloads) -(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) +if options.ruby: + if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): + print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" + sys.exit(1) +(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) CPUClass.clock = '2GHz' +CPUClass.numThreads = numThreads; np = options.num_cpus @@ -98,22 +177,26 @@ system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], physmem = PhysicalMemory(range=AddrRange("512MB")), membus = Bus(), mem_mode = test_mem_mode) -system.physmem.port = system.membus.port +if options.ruby: + options.use_map = True + Ruby.create_system(options, system) + assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) + system.system_port = system.ruby._sys_port_proxy.port +else: + system.system_port = system.membus.port + system.physmem.port = system.membus.port + CacheConfig.config_cache(options, system) for i in xrange(np): - if options.caches: - system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), - L1Cache(size = '64kB')) - if options.l2cache: - system.l2 = L2Cache(size='2MB') - system.tol2bus = Bus() - system.l2.cpu_side = system.tol2bus.port - system.l2.mem_side = system.membus.port - system.cpu[i].connectMemPorts(system.tol2bus) - else: - system.cpu[i].connectMemPorts(system.membus) - system.cpu[i].workload = process - -root = Root(system = system) + system.cpu[i].workload = multiprocesses[i] + + if options.ruby: + system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].port + system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].port + + if options.fastmem: + system.cpu[0].physmem_port = system.physmem.port + +root = Root(full_system = False, system = system) Simulation.run(options, root, system, FutureClass)