X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=configs%2Fexample%2Fse.py;h=4adfe7bb8da5955a96613bc13309c7716a950f10;hb=41beacce088e8f682a0e8ac48f22a3fa4805a43b;hp=39572cd862e14c016f58a940522eb237ec67198d;hpb=e7e17f92db8b249aaf99eb93a2447937d78270d5;p=gem5.git diff --git a/configs/example/se.py b/configs/example/se.py index 39572cd86..4adfe7bb8 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -44,22 +44,31 @@ import optparse import sys +import os import m5 from m5.defines import buildEnv from m5.objects import * from m5.util import addToPath, fatal -addToPath('../common') -addToPath('../ruby') -addToPath('../topologies') +addToPath('../') -import Options -import Ruby -import Simulation -import CacheConfig -from Caches import * -from cpu2000 import * +from ruby import Ruby + +from common import Options +from common import Simulation +from common import CacheConfig +from common import CpuConfig +from common import MemConfig +from common.Caches import * +from common.cpu2000 import * + +# Check if KVM support has been enabled, we might need to do VM +# configuration if that's the case. +have_kvm_support = 'BaseKvmCPU' in globals() +def is_kvm_cpu(cpu_class): + return have_kvm_support and cpu_class != None and \ + issubclass(cpu_class, BaseKvmCPU) def get_processes(options): """Interprets provided options and returns a list of processes""" @@ -84,6 +93,11 @@ def get_processes(options): for wrkld in workloads: process = LiveProcess() process.executable = wrkld + process.cwd = os.getcwd() + + if options.env: + with open(options.env, 'r') as f: + process.env = [line.rstrip() for line in f] if len(pargs) > idx: process.cmd = [wrkld] + pargs[idx].split() @@ -101,7 +115,7 @@ def get_processes(options): idx += 1 if options.smt: - assert(options.cpu_type == "detailed" or options.cpu_type == "inorder") + assert(options.cpu_type == "detailed") return multiprocesses, idx else: return multiprocesses, 1 @@ -132,12 +146,18 @@ if options.bench: for app in apps: try: if buildEnv['TARGET_ISA'] == 'alpha': - exec("workload = %s('alpha', 'tru64', 'ref')" % app) + exec("workload = %s('alpha', 'tru64', '%s')" % ( + app, options.spec_input)) + elif buildEnv['TARGET_ISA'] == 'arm': + exec("workload = %s('arm_%s', 'linux', '%s')" % ( + app, options.arm_iset, options.spec_input)) else: - exec("workload = %s(buildEnv['TARGET_ISA'], 'linux', 'ref')" % app) + exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % ( + app, options.spec_input)) multiprocesses.append(workload.makeLiveProcess()) except: - print >>sys.stderr, "Unable to find workload for %s: %s" % (buildEnv['TARGET_ISA'], app) + print >>sys.stderr, "Unable to find workload for %s: %s" % ( + buildEnv['TARGET_ISA'], app) sys.exit(1) elif options.cmd: multiprocesses, numThreads = get_processes(options) @@ -149,18 +169,19 @@ else: (CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) CPUClass.numThreads = numThreads -MemClass = Simulation.setMemClass(options) - # Check -- do not allow SMT with multiple CPUs if options.smt and options.num_cpus > 1: fatal("You cannot use SMT with multiple CPUs!") np = options.num_cpus system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], - physmem = MemClass(range=AddrRange(options.mem_size)), mem_mode = test_mem_mode, + mem_ranges = [AddrRange(options.mem_size)], cache_line_size = options.cacheline_size) +if numThreads > 1: + system.multi_thread = True + # Create a top-level voltage domain system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) @@ -176,11 +197,25 @@ system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, voltage_domain = system.cpu_voltage_domain) +# If elastic tracing is enabled, then configure the cpu and attach the elastic +# trace probe +if options.elastic_trace_en: + CpuConfig.config_etrace(CPUClass, system.cpu, options) + # All cpus belong to a common cpu_clk_domain, therefore running at a common # frequency. for cpu in system.cpu: cpu.clk_domain = system.cpu_clk_domain +if is_kvm_cpu(CPUClass) or is_kvm_cpu(FutureClass): + if buildEnv['TARGET_ISA'] == 'x86': + system.kvm_vm = KvmVM() + for process in multiprocesses: + process.useArchPT = True + process.kvmInSE = True + else: + fatal("KvmCPU can only be used in SE mode with x86") + # Sanity check if options.fastmem: if CPUClass != AtomicSimpleCPU: @@ -207,8 +242,7 @@ for i in xrange(np): system.cpu[i].fastmem = True if options.simpoint_profile: - system.cpu[i].simpoint_profile = True - system.cpu[i].simpoint_interval = options.simpoint_interval + system.cpu[i].addSimPointProbe(options.simpoint_interval) if options.checker: system.cpu[i].addCheckerCpu() @@ -216,19 +250,17 @@ for i in xrange(np): system.cpu[i].createThreads() if options.ruby: - if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): - print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" + if options.cpu_type == "atomic" or options.cpu_type == "AtomicSimpleCPU": + print >> sys.stderr, "Ruby does not work with atomic cpu!!" sys.exit(1) - # Set the option for physmem so that it is not allocated any space - system.physmem.null = True - - options.use_map = True - Ruby.create_system(options, system) - assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) + Ruby.create_system(options, False, system) + assert(options.num_cpus == len(system.ruby._cpu_ports)) + system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, + voltage_domain = system.voltage_domain) for i in xrange(np): - ruby_port = system.ruby._cpu_ruby_ports[i] + ruby_port = system.ruby._cpu_ports[i] # Create the interrupt controller and connect its ports to Ruby # Note that the interrupt controller is always present but only @@ -239,16 +271,17 @@ if options.ruby: system.cpu[i].icache_port = ruby_port.slave system.cpu[i].dcache_port = ruby_port.slave if buildEnv['TARGET_ISA'] == 'x86': - system.cpu[i].interrupts.pio = ruby_port.master - system.cpu[i].interrupts.int_master = ruby_port.slave - system.cpu[i].interrupts.int_slave = ruby_port.master + system.cpu[i].interrupts[0].pio = ruby_port.master + system.cpu[i].interrupts[0].int_master = ruby_port.slave + system.cpu[i].interrupts[0].int_slave = ruby_port.master system.cpu[i].itb.walker.port = ruby_port.slave system.cpu[i].dtb.walker.port = ruby_port.slave else: - system.membus = CoherentBus() + MemClass = Simulation.setMemClass(options) + system.membus = SystemXBar() system.system_port = system.membus.slave - system.physmem.port = system.membus.master CacheConfig.config_cache(options, system) + MemConfig.config_mem(options, system) root = Root(full_system = False, system = system) Simulation.run(options, root, system, FutureClass)