X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=configs%2Fexample%2Fse.py;h=4adfe7bb8da5955a96613bc13309c7716a950f10;hb=41beacce088e8f682a0e8ac48f22a3fa4805a43b;hp=67a2340cee2a2cded50ea667c5d74f8dffc6e83e;hpb=6c463135561796a3d26709d0498f300717ceba83;p=gem5.git diff --git a/configs/example/se.py b/configs/example/se.py index 67a2340ce..4adfe7bb8 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -1,3 +1,15 @@ +# Copyright (c) 2012-2013 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Copyright (c) 2006-2008 The Regents of The University of Michigan # All rights reserved. # @@ -30,37 +42,91 @@ # # "m5 test.py" +import optparse +import sys +import os + import m5 +from m5.defines import buildEnv +from m5.objects import * +from m5.util import addToPath, fatal -if m5.build_env['FULL_SYSTEM']: - m5.fatal("This script requires syscall emulation mode (*_SE).") +addToPath('../') -from m5.objects import * -import os, optparse, sys -from os.path import join as joinpath -m5.AddToPath('../common') -import Simulation -from Caches import * -from cpu2000 import * - -# Get paths we might need. It's expected this file is in m5/configs/example. -config_path = os.path.dirname(os.path.abspath(__file__)) -config_root = os.path.dirname(config_path) -m5_root = os.path.dirname(config_root) +from ruby import Ruby -parser = optparse.OptionParser() +from common import Options +from common import Simulation +from common import CacheConfig +from common import CpuConfig +from common import MemConfig +from common.Caches import * +from common.cpu2000 import * + +# Check if KVM support has been enabled, we might need to do VM +# configuration if that's the case. +have_kvm_support = 'BaseKvmCPU' in globals() +def is_kvm_cpu(cpu_class): + return have_kvm_support and cpu_class != None and \ + issubclass(cpu_class, BaseKvmCPU) + +def get_processes(options): + """Interprets provided options and returns a list of processes""" + + multiprocesses = [] + inputs = [] + outputs = [] + errouts = [] + pargs = [] + + workloads = options.cmd.split(';') + if options.input != "": + inputs = options.input.split(';') + if options.output != "": + outputs = options.output.split(';') + if options.errout != "": + errouts = options.errout.split(';') + if options.options != "": + pargs = options.options.split(';') -# Benchmark options -parser.add_option("-c", "--cmd", - default=joinpath(m5_root, "tests/test-progs/hello/bin/alpha/linux/hello"), - help="The binary to run in syscall emulation mode.") -parser.add_option("-o", "--options", default="", - help='The options to pass to the binary, use " " around the entire string') -parser.add_option("-i", "--input", default="", help="Read stdin from a file.") -parser.add_option("--output", default="", help="Redirect stdout to a file.") -parser.add_option("--errout", default="", help="Redirect stderr to a file.") + idx = 0 + for wrkld in workloads: + process = LiveProcess() + process.executable = wrkld + process.cwd = os.getcwd() -execfile(os.path.join(config_root, "common", "Options.py")) + if options.env: + with open(options.env, 'r') as f: + process.env = [line.rstrip() for line in f] + + if len(pargs) > idx: + process.cmd = [wrkld] + pargs[idx].split() + else: + process.cmd = [wrkld] + + if len(inputs) > idx: + process.input = inputs[idx] + if len(outputs) > idx: + process.output = outputs[idx] + if len(errouts) > idx: + process.errout = errouts[idx] + + multiprocesses.append(process) + idx += 1 + + if options.smt: + assert(options.cpu_type == "detailed") + return multiprocesses, idx + else: + return multiprocesses, 1 + + +parser = optparse.OptionParser() +Options.addCommonOptions(parser) +Options.addSEOptions(parser) + +if '--ruby' in sys.argv: + Ruby.define_options(parser) (options, args) = parser.parse_args() @@ -68,95 +134,154 @@ if args: print "Error: script doesn't take any positional arguments" sys.exit(1) +multiprocesses = [] +numThreads = 1 + if options.bench: - try: - if m5.build_env['TARGET_ISA'] != 'alpha': - print >>sys.stderr, "Simpoints code only works for Alpha ISA at this time" - sys.exit(1) - exec("workload = %s('alpha', 'tru64', 'ref')" % options.bench) - process = workload.makeLiveProcess() - except: - print >>sys.stderr, "Unable to find workload for %s" % options.bench + apps = options.bench.split("-") + if len(apps) != options.num_cpus: + print "number of benchmarks not equal to set num_cpus!" sys.exit(1) + + for app in apps: + try: + if buildEnv['TARGET_ISA'] == 'alpha': + exec("workload = %s('alpha', 'tru64', '%s')" % ( + app, options.spec_input)) + elif buildEnv['TARGET_ISA'] == 'arm': + exec("workload = %s('arm_%s', 'linux', '%s')" % ( + app, options.arm_iset, options.spec_input)) + else: + exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % ( + app, options.spec_input)) + multiprocesses.append(workload.makeLiveProcess()) + except: + print >>sys.stderr, "Unable to find workload for %s: %s" % ( + buildEnv['TARGET_ISA'], app) + sys.exit(1) +elif options.cmd: + multiprocesses, numThreads = get_processes(options) else: - process = LiveProcess() - process.executable = options.cmd - process.cmd = [options.cmd] + options.options.split() + print >> sys.stderr, "No workload specified. Exiting!\n" + sys.exit(1) -if options.input != "": - process.input = options.input -if options.output != "": - process.output = options.output -if options.errout != "": - process.errout = options.errout +(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) +CPUClass.numThreads = numThreads + +# Check -- do not allow SMT with multiple CPUs +if options.smt and options.num_cpus > 1: + fatal("You cannot use SMT with multiple CPUs!") +np = options.num_cpus +system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], + mem_mode = test_mem_mode, + mem_ranges = [AddrRange(options.mem_size)], + cache_line_size = options.cacheline_size) -# By default, set workload to path of user-specified binary -workloads = options.cmd +if numThreads > 1: + system.multi_thread = True -if options.detailed: - #check for SMT workload - workloads = options.cmd.split(';') - if len(workloads) > 1: - process = [] - smt_idx = 0 - inputs = [] - outputs = [] - errouts = [] - - if options.input != "": - inputs = options.input.split(';') - if options.output != "": - outputs = options.output.split(';') - if options.errout != "": - errouts = options.errout.split(';') - - for wrkld in workloads: - smt_process = LiveProcess() - smt_process.executable = wrkld - smt_process.cmd = wrkld + " " + options.options - if inputs and inputs[smt_idx]: - smt_process.input = inputs[smt_idx] - if outputs and outputs[smt_idx]: - smt_process.output = outputs[smt_idx] - if errouts and errouts[smt_idx]: - smt_process.errout = errouts[smt_idx] - process += [smt_process, ] - smt_idx += 1 +# Create a top-level voltage domain +system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) -(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) +# Create a source clock for the system and set the clock period +system.clk_domain = SrcClockDomain(clock = options.sys_clock, + voltage_domain = system.voltage_domain) -CPUClass.clock = '2GHz' -CPUClass.numThreads = len(workloads) +# Create a CPU voltage domain +system.cpu_voltage_domain = VoltageDomain() -np = options.num_cpus +# Create a separate clock domain for the CPUs +system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, + voltage_domain = + system.cpu_voltage_domain) -system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], - physmem = PhysicalMemory(range=AddrRange("512MB")), - membus = Bus(), mem_mode = test_mem_mode) +# If elastic tracing is enabled, then configure the cpu and attach the elastic +# trace probe +if options.elastic_trace_en: + CpuConfig.config_etrace(CPUClass, system.cpu, options) -system.physmem.port = system.membus.port +# All cpus belong to a common cpu_clk_domain, therefore running at a common +# frequency. +for cpu in system.cpu: + cpu.clk_domain = system.cpu_clk_domain -if options.l2cache: - system.l2 = L2Cache(size='2MB') - system.tol2bus = Bus() - system.l2.cpu_side = system.tol2bus.port - system.l2.mem_side = system.membus.port +if is_kvm_cpu(CPUClass) or is_kvm_cpu(FutureClass): + if buildEnv['TARGET_ISA'] == 'x86': + system.kvm_vm = KvmVM() + for process in multiprocesses: + process.useArchPT = True + process.kvmInSE = True + else: + fatal("KvmCPU can only be used in SE mode with x86") + +# Sanity check +if options.fastmem: + if CPUClass != AtomicSimpleCPU: + fatal("Fastmem can only be used with atomic CPU!") + if (options.caches or options.l2cache): + fatal("You cannot use fastmem in combination with caches!") + +if options.simpoint_profile: + if not options.fastmem: + # Atomic CPU checked with fastmem option already + fatal("SimPoint generation should be done with atomic cpu and fastmem") + if np > 1: + fatal("SimPoint generation not supported with more than one CPUs") for i in xrange(np): - if options.caches: - system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), - L1Cache(size = '64kB')) - if options.l2cache: - system.cpu[i].connectMemPorts(system.tol2bus) + if options.smt: + system.cpu[i].workload = multiprocesses + elif len(multiprocesses) == 1: + system.cpu[i].workload = multiprocesses[0] else: - system.cpu[i].connectMemPorts(system.membus) - system.cpu[i].workload = process + system.cpu[i].workload = multiprocesses[i] if options.fastmem: - system.cpu[0].physmem_port = system.physmem.port + system.cpu[i].fastmem = True + + if options.simpoint_profile: + system.cpu[i].addSimPointProbe(options.simpoint_interval) -root = Root(system = system) + if options.checker: + system.cpu[i].addCheckerCpu() + + system.cpu[i].createThreads() + +if options.ruby: + if options.cpu_type == "atomic" or options.cpu_type == "AtomicSimpleCPU": + print >> sys.stderr, "Ruby does not work with atomic cpu!!" + sys.exit(1) + + Ruby.create_system(options, False, system) + assert(options.num_cpus == len(system.ruby._cpu_ports)) + + system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, + voltage_domain = system.voltage_domain) + for i in xrange(np): + ruby_port = system.ruby._cpu_ports[i] + + # Create the interrupt controller and connect its ports to Ruby + # Note that the interrupt controller is always present but only + # in x86 does it have message ports that need to be connected + system.cpu[i].createInterruptController() + + # Connect the cpu's cache ports to Ruby + system.cpu[i].icache_port = ruby_port.slave + system.cpu[i].dcache_port = ruby_port.slave + if buildEnv['TARGET_ISA'] == 'x86': + system.cpu[i].interrupts[0].pio = ruby_port.master + system.cpu[i].interrupts[0].int_master = ruby_port.slave + system.cpu[i].interrupts[0].int_slave = ruby_port.master + system.cpu[i].itb.walker.port = ruby_port.slave + system.cpu[i].dtb.walker.port = ruby_port.slave +else: + MemClass = Simulation.setMemClass(options) + system.membus = SystemXBar() + system.system_port = system.membus.slave + CacheConfig.config_cache(options, system) + MemConfig.config_mem(options, system) +root = Root(full_system = False, system = system) Simulation.run(options, root, system, FutureClass)