X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=configs%2Fruby%2FRuby.py;h=3c43fa6c6ab7b2583830352c954a5cc2bd02d152;hb=b80e574d01a0453acfe33084f288ac6fb3cd9cbb;hp=75b891b1fbe1cd48e2b6c25a3608468b8ae34c35;hpb=d5b5d89b34da1cd311974bffd3834bff451efe0e;p=gem5.git diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py index 75b891b1f..3c43fa6c6 100644 --- a/configs/ruby/Ruby.py +++ b/configs/ruby/Ruby.py @@ -106,6 +106,33 @@ def create_system(options, system, piobus = None, dma_ports = []): system.ruby = RubySystem(no_mem_vec = options.use_map) ruby = system.ruby + # Set the network classes based on the command line options + if options.garnet_network == "fixed": + NetworkClass = GarnetNetwork_d + IntLinkClass = GarnetIntLink_d + ExtLinkClass = GarnetExtLink_d + RouterClass = GarnetRouter_d + InterfaceClass = GarnetNetworkInterface_d + + elif options.garnet_network == "flexible": + NetworkClass = GarnetNetwork + IntLinkClass = GarnetIntLink + ExtLinkClass = GarnetExtLink + RouterClass = GarnetRouter + InterfaceClass = GarnetNetworkInterface + + else: + NetworkClass = SimpleNetwork + IntLinkClass = SimpleIntLink + ExtLinkClass = SimpleExtLink + RouterClass = Switch + InterfaceClass = None + + # Instantiate the network object so that the controllers can connect to it. + network = NetworkClass(ruby_system = ruby, topology = options.topology, + routers = [], ext_links = [], int_links = [], netifs = []) + ruby.network = network + protocol = buildEnv['PROTOCOL'] exec "import %s" % protocol try: @@ -120,6 +147,7 @@ def create_system(options, system, piobus = None, dma_ports = []): # independent of the protocol and kept in the protocol-agnostic # part (i.e. here). sys_port_proxy = RubyPortProxy(ruby_system = ruby) + # Give the system port proxy a SimObject parent without creating a # full-fledged controller system.sys_port_proxy = sys_port_proxy @@ -127,46 +155,25 @@ def create_system(options, system, piobus = None, dma_ports = []): # Connect the system port for loading of binaries etc system.system_port = system.sys_port_proxy.slave - - # - # Set the network classes based on the command line options - # - if options.garnet_network == "fixed": - class NetworkClass(GarnetNetwork_d): pass - class IntLinkClass(GarnetIntLink_d): pass - class ExtLinkClass(GarnetExtLink_d): pass - class RouterClass(GarnetRouter_d): pass - elif options.garnet_network == "flexible": - class NetworkClass(GarnetNetwork): pass - class IntLinkClass(GarnetIntLink): pass - class ExtLinkClass(GarnetExtLink): pass - class RouterClass(GarnetRouter): pass - else: - class NetworkClass(SimpleNetwork): pass - class IntLinkClass(SimpleIntLink): pass - class ExtLinkClass(SimpleExtLink): pass - class RouterClass(Switch): pass - - # Create the network topology - network = NetworkClass(ruby_system = ruby, topology = topology.description, - routers = [], ext_links = [], int_links = []) topology.makeTopology(options, network, IntLinkClass, ExtLinkClass, - RouterClass) + RouterClass) + + if InterfaceClass != None: + netifs = [InterfaceClass(id=i) for (i,n) in enumerate(network.ext_links)] + network.netifs = netifs if options.network_fault_model: assert(options.garnet_network == "fixed") network.enable_fault_model = True network.fault_model = FaultModel() - # # Loop through the directory controlers. # Determine the total memory size of the ruby system and verify it is equal # to physmem. However, if Ruby memory is using sparse memory in SE # mode, then the system should not back-up the memory state with # the Memory Vector and thus the memory size bytes should stay at 0. # Also set the numa bits to the appropriate values. - # total_mem_size = MemorySize('0B') ruby.block_size_bytes = options.cacheline_size @@ -187,8 +194,6 @@ def create_system(options, system, piobus = None, dma_ports = []): phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) assert(total_mem_size.value == phys_mem_size) - - ruby.network = network ruby.mem_size = total_mem_size # Connect the cpu sequencers and the piobus @@ -200,6 +205,6 @@ def create_system(options, system, piobus = None, dma_ports = []): if buildEnv['TARGET_ISA'] == "x86": cpu_seq.pio_slave_port = piobus.master - ruby._cpu_ruby_ports = cpu_sequencers + ruby._cpu_ports = cpu_sequencers ruby.num_of_sequencers = len(cpu_sequencers) ruby.random_seed = options.random_seed