X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=configure;h=77bab3062880b745cdf0128660d58c44584e4b17;hb=089f0fa4cf1885b2333f4522140ae3747f2e367b;hp=eddc14746644bd2e00a9a248aa95053e4dc54413;hpb=c71db7787b63fc1ab0c57672c9e469711748bda9;p=riscv-isa-sim.git

diff --git a/configure b/configure
index eddc147..77bab30 100755
--- a/configure
+++ b/configure
@@ -706,6 +706,7 @@ with_fesvr
 enable_commitlog
 enable_histogram
 enable_dirty
+enable_misaligned
 '
       ac_precious_vars='build_alias
 host_alias
@@ -1352,6 +1353,8 @@ Optional Features:
   --enable-histogram      Enable PC histogram generation
   --enable-dirty          Enable hardware management of PTE accessed and dirty
                           bits
+  --enable-misaligned     Enable hardware support for misaligned loads and
+                          stores
 
 Optional Packages:
   --with-PACKAGE[=ARG]    use PACKAGE [ARG=yes]
@@ -4679,6 +4682,19 @@ if test "x$enable_dirty" = "xyes"; then :
 $as_echo "#define RISCV_ENABLE_DIRTY /**/" >>confdefs.h
 
 
+fi
+
+# Check whether --enable-misaligned was given.
+if test "${enable_misaligned+set}" = set; then :
+  enableval=$enable_misaligned;
+fi
+
+if test "x$enable_misaligned" = "xyes"; then :
+
+
+$as_echo "#define RISCV_ENABLE_MISALIGNED /**/" >>confdefs.h
+
+
 fi