X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=cpu%2FChangeLog;h=3fbbd89e3ea4ea05f8baa09e4aa8825c7bb26837;hb=c7c7219d3a06a714e04e73ebd029811e6bd5bd37;hp=f2d1d7d4203e085cecfa6d10ce7ffc37637d79d0;hpb=4970f871a701ce55f5018f31bca1b478448c57ff;p=binutils-gdb.git diff --git a/cpu/ChangeLog b/cpu/ChangeLog index f2d1d7d4203..3fbbd89e3ea 100644 --- a/cpu/ChangeLog +++ b/cpu/ChangeLog @@ -1,3 +1,159 @@ +2009-01-07 Hans-Peter Nilsson + + * frv.cpu (mabshs): Explicitly sign-extend arguments of abs to DI. + (DI-ext-HI, DI-ext-UHI, DI-ext-DI): New pmacros. + (media-arith-sat-semantics): Explicitly sign- or zero-extend + arguments of "operation" to DI using "mode" and the new pmacros. + +2009-01-03 Hans-Peter Nilsson + + * cris.cpu (cris-implemented-writable-specregs-v32): Correct size + of number 2, PID. + +2008-12-23 Jon Beniston + + * lm32.cpu: New file. + * lm32.opc: New file. + +2008-01-29 Alan Modra + + * mt.opc (parse_imm16): Apply 2007-09-26 opcodes/mt-asm.c change + to source. + +2007-10-22 Hans-Peter Nilsson + + * cris.cpu (movs, movu): Use result of extension operation when + updating flags. + +2007-07-04 Nick Clifton + + * cris.cpu: Update copyright notice to refer to GPLv3. + * frv.cpu, frv.opc, iq10.cpu, iq2000m.cpu, iq2000.opc, m32c.cpu, + m32c.opc, m32r.cpu, m32r.opc, mt.cpu, mt.opc, sh64-compact.cpu, + sh64-media.cpu, sh.cpu, sh.opc, simplify.inc, xc16x.cpu, + xc16x.opc: Likewise. + * iq2000.cpu: Fix copyright notice to refer to FSF. + +2007-04-30 Mark Salter + + * frv.cpu (spr-names): Support new coprocessor SPR registers. + +2007-04-20 Nick Clifton + + * xc16x.cpu: Restore after accidentally overwriting this file with + xc16x.opc. + +2007-03-29 DJ Delorie + + * m32c.cpu (Imm-8-s4n): Fix print hook. + (Lab-24-8, Lab-32-8, Lab-40-8): Fix. + (arith-jnz-imm4-dst-defn): Make relaxable. + (arith-jnz16-imm4-dst-defn): Fix encodings. + +2007-03-20 DJ Delorie + + * m32c.cpu (f-dsp-40-u20, f-dsp-48-u20, Dsp-40-u20, Dsp-40-u20, + mem20): New. + (src16-16-20-An-relative-*): New. + (dst16-*-20-An-relative-*): New. + (dst16-16-16sa-*): New + (dst16-16-16ar-*): New + (dst32-16-16sa-Unprefixed-*): New + (jsri): Fix operands. + (setzx): Fix encoding. + +2007-03-08 Alan Modra + + * m32r.opc: Formatting. + +2006-05-22 Nick Clifton + + * iq2000.cpu: Fix include paths for iq2000m.cpu and iq10.cpu. + +2006-04-10 DJ Delorie + + * m32c.opc (parse_unsigned_bitbase): Take a new parameter which + decides if this function accepts symbolic constants or not. + (parse_signed_bitbase): Likewise. + (parse_unsigned_bitbase8): Pass the new parameter. + (parse_unsigned_bitbase11): Likewise. + (parse_unsigned_bitbase16): Likewise. + (parse_unsigned_bitbase19): Likewise. + (parse_unsigned_bitbase27): Likewise. + (parse_signed_bitbase8): Likewise. + (parse_signed_bitbase11): Likewise. + (parse_signed_bitbase19): Likewise. + +2006-03-13 DJ Delorie + + * m32c.cpu (Bit3-S): New. + (btst:s): New. + * m32c.opc (parse_bit3_S): New. + + * m32c.cpu (decimal-subtraction16-insn): Add second operand. + (btst): Add optional :G suffix for MACH32. + (or.b:S): New. + (pop.w:G): Add optional :G suffix for MACH16. + (push.b.imm): Fix syntax. + +2006-03-10 DJ Delorie + + * m32c.cpu (mul.l): New. + (mulu.l): New. + +2006-03-03 Shrirang Khisti + + * m32c.cpu (RL_TYPE): New attribute, with macros. + (Lab-8-24): Add RELAX. + (unary-insn-defn-g, binary-arith-imm-dst-defn, + binary-arith-imm4-dst-defn): Add 1ADDR attribute. + (binary-arith-src-dst-defn): Add 2ADDR attribute. + (jcnd16-5, jcnd16, jcnd32, jmp16.s, jmp16.b, jmp16.w, jmp16.a, + jmp32.s, jmp32.b, jmp32.w, jmp32.a, jsr16.w, jsr16.a): Add JUMP + attribute. + (jsri16, jsri32): Add 1ADDR attribute. + (jsr32.w, jsr32.a): Add JUMP attribute. + +2006-02-17 Shrirang Khisti + Anil Paranjape + Shilin Shakti + + * xc16x.cpu: New file containing complete CGEN specific XC16X CPU + description. + * xc16x.opc: New file containing supporting XC16C routines. + +2006-02-10 Nick Clifton + + * iq2000.opc (parse_hi16): Truncate shifted values to 16 bits. + +2006-01-06 DJ Delorie + + * m32c.cpu (mov.w:q): Fix mode. + (push32.b.imm): Likewise, for the comment. + +2005-12-16 Nathan Sidwell + + Second part of ms1 to mt renaming. + * mt.cpu (define-arch, define-isa): Set name to mt. + (define-mach): Adjust. + * mt.opc (CGEN_ASM_HASH): Update. + (mt_asm_hash, mt_cgen_insn_supported): Renamed. + (parse_loopsize, parse_imm16): Adjust. + +2005-12-13 DJ Delorie + + * m32c.cpu (jsri): Fix order so register names aren't treated as + symbols. + (indexb, indexbd, indexbs, indexl, indexld, indexls, indexw, + indexwd, indexws): Fix encodings. + 2005-12-12 Nathan Sidwell * mt.cpu: Rename from ms1.cpu.