X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=cpu%2Fbase.hh;h=4a44ab804ac9e0486cd70c34935df9b9b8894acf;hb=adf47c95b0e1cdea9f17569f6c26a118f32f574b;hp=0cb81e93beac5f383ed7ed63821cf45631e6d316;hpb=3011a7ed0b58c5db117c1718c345d8e00c5160de;p=gem5.git

diff --git a/cpu/base.hh b/cpu/base.hh
index 0cb81e93b..4a44ab804 100644
--- a/cpu/base.hh
+++ b/cpu/base.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2002-2004 The Regents of The University of Michigan
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -32,12 +32,13 @@
 #include <vector>
 
 #include "base/statistics.hh"
+#include "config/full_system.hh"
 #include "cpu/sampler/sampler.hh"
 #include "sim/eventq.hh"
 #include "sim/sim_object.hh"
 #include "targetarch/isa_traits.hh"
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 class System;
 #endif
 
@@ -55,7 +56,7 @@ class BaseCPU : public SimObject
     inline Tick cycles(int numCycles) const { return clock * numCycles; }
     inline Tick curCycle() const { return curTick / clock; }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
   protected:
     uint64_t interrupts[NumInterruptLevels];
     uint64_t intstatus;
@@ -75,6 +76,18 @@ class BaseCPU : public SimObject
 
     bool check_interrupts() const { return intstatus != 0; }
     uint64_t intr_status() const { return intstatus; }
+
+    class ProfileEvent : public Event
+    {
+      private:
+        BaseCPU *cpu;
+        int interval;
+
+      public:
+        ProfileEvent(BaseCPU *cpu, int interval);
+        void process();
+    };
+    ProfileEvent *profileEvent;
 #endif
 
   protected:
@@ -109,9 +122,13 @@ class BaseCPU : public SimObject
         Tick clock;
         bool functionTrace;
         Tick functionTraceStart;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
         System *system;
+        int cpu_id;
+        Tick profile;
 #endif
+
+        Params();
     };
 
     const Params *params;
@@ -120,13 +137,14 @@ class BaseCPU : public SimObject
     virtual ~BaseCPU();
 
     virtual void init();
+    virtual void startup();
     virtual void regStats();
 
     void registerExecContexts();
 
     /// Prepare for another CPU to take over execution.  When it is
     /// is ready (drained pipe) it signals the sampler.
-    virtual void switchOut(SamplingCPU *);
+    virtual void switchOut(Sampler *);
 
     /// Take over execution from the given CPU.  Used for warm-up and
     /// sampling.
@@ -152,7 +170,7 @@ class BaseCPU : public SimObject
      */
     EventQueue **comLoadEventQueue;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     System *system;
 
     /**