X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=cpu%2Fbase.hh;h=4a44ab804ac9e0486cd70c34935df9b9b8894acf;hb=adf47c95b0e1cdea9f17569f6c26a118f32f574b;hp=e28f15884c4f90fcc7ef1f68174b93f0a9176925;hpb=4f2480a18bdf98792e2ebf3471ce7cd3109ef824;p=gem5.git diff --git a/cpu/base.hh b/cpu/base.hh index e28f15884..4a44ab804 100644 --- a/cpu/base.hh +++ b/cpu/base.hh @@ -32,12 +32,13 @@ #include #include "base/statistics.hh" +#include "config/full_system.hh" #include "cpu/sampler/sampler.hh" #include "sim/eventq.hh" #include "sim/sim_object.hh" #include "targetarch/isa_traits.hh" -#ifdef FULL_SYSTEM +#if FULL_SYSTEM class System; #endif @@ -55,7 +56,7 @@ class BaseCPU : public SimObject inline Tick cycles(int numCycles) const { return clock * numCycles; } inline Tick curCycle() const { return curTick / clock; } -#ifdef FULL_SYSTEM +#if FULL_SYSTEM protected: uint64_t interrupts[NumInterruptLevels]; uint64_t intstatus; @@ -75,6 +76,18 @@ class BaseCPU : public SimObject bool check_interrupts() const { return intstatus != 0; } uint64_t intr_status() const { return intstatus; } + + class ProfileEvent : public Event + { + private: + BaseCPU *cpu; + int interval; + + public: + ProfileEvent(BaseCPU *cpu, int interval); + void process(); + }; + ProfileEvent *profileEvent; #endif protected: @@ -109,10 +122,13 @@ class BaseCPU : public SimObject Tick clock; bool functionTrace; Tick functionTraceStart; -#ifdef FULL_SYSTEM +#if FULL_SYSTEM System *system; int cpu_id; + Tick profile; #endif + + Params(); }; const Params *params; @@ -121,6 +137,7 @@ class BaseCPU : public SimObject virtual ~BaseCPU(); virtual void init(); + virtual void startup(); virtual void regStats(); void registerExecContexts(); @@ -153,7 +170,7 @@ class BaseCPU : public SimObject */ EventQueue **comLoadEventQueue; -#ifdef FULL_SYSTEM +#if FULL_SYSTEM System *system; /**