X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=cpu%2Fbpf.cpu;h=13dde7094c8b2557719ab8976e424553cf7ea64e;hb=243cf0f69c36c4ee09c3c2b0bc7a97dc16119c51;hp=89a27fe128d8813b4d9fc621333b4278ae5086d8;hpb=c54a9b56696e584c2b8c7146caac337c063f5516;p=binutils-gdb.git diff --git a/cpu/bpf.cpu b/cpu/bpf.cpu index 89a27fe128d..13dde7094c8 100644 --- a/cpu/bpf.cpu +++ b/cpu/bpf.cpu @@ -32,8 +32,12 @@ (name bpf) (comment "Linux kernel BPF") (insn-lsb0? #t) - (machs bpf) - (isas ebpfle ebpfbe)) + ;; XXX explain the default-alignment setting is for the simulator. + ;; It is confusing that the simulator follows the emulated memory + ;; access conventions for fetching instructions by pieces... + (default-alignment unaligned) + (machs bpf xbpf) + (isas ebpfle ebpfbe xbpfle xbpfbe)) ;;;; The ISAs @@ -94,34 +98,46 @@ ;; Length of an unknown instruction. Used by disassembly and by the ;; simulator's invalid insn handler. (default-insn-bitsize 64) - ;; Number of bits of insn that can be initially fetched. XXX this - ;; should be 64 (the size of the smallest insn) but until CGEN - ;; gets fixed to place constant fields in their own words, we have - ;; to use this workaround to avoid the opcode byte to be placed at - ;; the wrong side of the instruction when assembling in - ;; big-endian. - (base-insn-bitsize 8))) + ;; Number of bits of insn that can be initially fetched. This is + ;; the size of the smallest insn. + (base-insn-bitsize 64))) (define-bpf-isa le) (define-bpf-isa be) -(define-pmacro all-isas () (ISA ebpfle,ebpfbe)) +(define-pmacro (define-xbpf-isa x-endian) + (define-isa + (name (.sym xbpf x-endian)) + (comment "The xBPF instruction set") + (default-insn-word-bitsize 64) + (default-insn-bitsize 64) + (base-insn-bitsize 64))) + +(define-xbpf-isa le) +(define-xbpf-isa be) + +(define-pmacro all-isas () (ISA ebpfle,ebpfbe,xbpfle,xbpfbe)) +(define-pmacro xbpf-isas () (ISA xbpfle,xbpfbe)) + +(define-pmacro (endian-isas x-endian) + ((ISA (.sym ebpf x-endian) (.sym xbpf x-endian)))) ;;;; Hardware Hierarchy ;; -;; bpf architecture -;; | -;; bpfbf cpu-family -;; | -;; bpf machine -;; | -;; bpf-def model +;; bpf architecture +;; | +;; bpfbf cpu-family +;; / \ +;; bpf xbpf machine +;; | | +;; bpf-def xbpf-def model (define-cpu (name bpfbf) (comment "Linux kernel eBPF virtual CPU") - (word-bitsize 32)) + (insn-endian big) + (word-bitsize 64)) (define-mach (name bpf) @@ -142,6 +158,25 @@ () ; profile action (default) )) +(define-mach + (name xbpf) + (comment "Experimental BPF") + (cpu bpfbf) + (isas ebpfle ebpfbe xbpfle xbpfbe)) + +(define-model + (name xbpf-def) + (comment "xBPF default model") + (mach xbpf) + (unit u-exec "execution unit" () + 1 ; issue + 1 ; done + () ; state + () ; inputs + () ; outputs + () ; profile action (default) + )) + ;;;; Hardware Elements ;; eBPF programs can access 10 general-purpose registers which are @@ -150,7 +185,7 @@ (define-hardware (name h-gpr) (comment "General Purpose Registers") - (attrs all-isas (MACH bpf)) + (attrs all-isas (MACH bpf xbpf)) (type register DI (16)) (indices keyword "%" ;; XXX the frame pointer fp is read-only, so it should @@ -159,13 +194,19 @@ (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7) (r8 8) (r9 9) (fp 10) ;; Additional names recognized when assembling. - (a 0) (ctx 6) (r10 10)))) + (r0 0) (r6 6) (r10 10)))) ;; The program counter. CGEN requires it, even if it is not visible ;; to eBPF programs. -(dnh h-pc "program counter" (PC PROFILE) (pc) () () ()) - +(define-hardware + (name h-pc) + (comment "program counter") + (attrs PC PROFILE all-isas) + (type pc UDI) + (get () (raw-reg h-pc)) + (set (newval) (set (raw-reg h-pc) newval))) + ;; A 64-bit h-sint to be used by the imm64 operand below. XXX this ;; shouldn't be needed, as h-sint is supposed to be able to hold ;; 64-bit values. However, in practice CGEN limits h-sint to 32 bits @@ -208,6 +249,8 @@ (ADD #x0) (SUB #x1) (MUL #x2) (DIV #x3) (OR #x4) (AND #x5) (LSH #x6) (RSH #x7) (NEG #x8) (MOD #x9) (XOR #xa) (MOV #xb) (ARSH #xc) (END #xd) + ;; xBPF-only: signed div, signed mod + (SDIV #xe) (SMOD #xf) ;; Codes for OP_CLASS_JMP (JA #x0) (JEQ #x1) (JGT #x2) (JGE #x3) (JSET #x4) (JNE #x5) (JSGT #x6) (JSGE #x7) (CALL #x8) (EXIT #x9) @@ -252,11 +295,11 @@ ;; NOT use registers, where endianness is irrelevant i.e. f-regs is a ;; constant 0 opcode. -(dwf f-dstle "eBPF dst register field" ((ISA ebpfle)) 8 8 3 4 UINT) -(dwf f-srcle "eBPF source register field" ((ISA ebpfle)) 8 8 7 4 UINT) +(dwf f-dstle "eBPF dst register field" ((ISA ebpfle xbpfle)) 8 8 3 4 UINT) +(dwf f-srcle "eBPF source register field" ((ISA ebpfle xbpfle)) 8 8 7 4 UINT) -(dwf f-dstbe "eBPF dst register field" ((ISA ebpfbe)) 8 8 7 4 UINT) -(dwf f-srcbe "eBPF source register field" ((ISA ebpfbe)) 8 8 3 4 UINT) +(dwf f-dstbe "eBPF dst register field" ((ISA ebpfbe xbpfbe)) 8 8 7 4 UINT) +(dwf f-srcbe "eBPF source register field" ((ISA ebpfbe xbpfbe)) 8 8 3 4 UINT) (dwf f-regs "eBPF registers field" (all-isas) 8 8 7 8 UINT) @@ -266,7 +309,7 @@ ;; difficulty: we put them in their own instruction word so the ;; byte-endianness will be properly applied. -(dwf f-offset16 "eBPF offset field" (all-isas) 16 16 15 16 INT) +(dwf f-offset16 "eBPF offset field" (all-isas) 16 16 15 16 HI) (dwf f-imm32 "eBPF 32-bit immediate field" (all-isas) 32 32 31 32 INT) ;; For the disjoint 64-bit signed immediate, however, we need to use a @@ -296,11 +339,11 @@ ;; A couple of source and destination register operands are defined ;; for each ISA: ebpfle and ebpfbe. -(dno dstle "destination register" ((ISA ebpfle)) h-gpr f-dstle) -(dno srcle "source register" ((ISA ebpfle)) h-gpr f-srcle) +(dno dstle "destination register" ((ISA ebpfle xbpfle)) h-gpr f-dstle) +(dno srcle "source register" ((ISA ebpfle xbpfle)) h-gpr f-srcle) -(dno dstbe "destination register" ((ISA ebpfbe)) h-gpr f-dstbe) -(dno srcbe "source register" ((ISA ebpfbe)) h-gpr f-srcbe) +(dno dstbe "destination register" ((ISA ebpfbe xbpfbe)) h-gpr f-dstbe) +(dno srcbe "source register" ((ISA ebpfbe xbpfbe)) h-gpr f-srcbe) ;; Jump instructions have a 16-bit PC-relative address. ;; CALL instructions have a 32-bit PC-relative address. @@ -361,60 +404,103 @@ ;; ADD[32]{i,r}le for the little-endian ISA ;; ADD[32]{i,r}be for the big-endian ISA ;; -;; The `i' variants perform `src OP dst -> dst' operations. -;; The `r' variants perform `dst OP imm32 -> dst' operations. +;; The `i' variants perform `dst OP imm32 -> dst' operations. +;; The `r' variants perform `dst OP src -> dst' operations. ;; ;; The variants with 32 in their name are of ALU class. Otherwise ;; they are ALU64 class. -(define-pmacro (define-alu-insn-un x-basename x-suffix x-op-class x-op-code x-endian) +(define-pmacro (define-alu-insn-un x-basename x-suffix x-op-class x-op-code + x-endian x-mode x-semop) (dni (.sym x-basename x-suffix x-endian) (.str x-basename x-suffix) - ((ISA (.sym ebpf x-endian))) + (endian-isas x-endian) (.str x-basename x-suffix " $dst" x-endian) (+ (f-imm32 0) (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian) - x-op-class OP_SRC_K x-op-code) () ())) + x-op-class OP_SRC_K x-op-code) + (set x-mode (.sym dst x-endian) (x-semop x-mode (.sym dst x-endian))) + ())) -(define-pmacro (define-alu-insn-bin x-basename x-suffix x-op-class x-op-code x-endian) +(define-pmacro (define-alu-insn-bin x-basename x-suffix x-op-class x-op-code + x-endian x-mode x-semop x-isas) (begin + ;; dst = dst OP immediate (dni (.sym x-basename x-suffix "i" x-endian) (.str x-basename x-suffix " immediate") - ((ISA (.sym ebpf x-endian))) + (.splice (.unsplice x-isas)) (.str x-basename x-suffix " $dst" x-endian ",$imm32") (+ imm32 (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian) - x-op-class OP_SRC_K x-op-code) () ()) + x-op-class OP_SRC_K x-op-code) + (set x-mode (.sym dst x-endian) (x-semop x-mode (.sym dst x-endian) imm32)) + ()) + ;; dst = dst OP src (dni (.sym x-basename x-suffix "r" x-endian) (.str x-basename x-suffix " register") - ((ISA (.sym ebpf x-endian))) + (.splice (.unsplice x-isas)) (.str x-basename x-suffix " $dst" x-endian ",$src" x-endian) (+ (f-imm32 0) (f-offset16 0) (.sym src x-endian) (.sym dst x-endian) - x-op-class OP_SRC_X x-op-code) () ()))) + x-op-class OP_SRC_X x-op-code) + (set x-mode (.sym dst x-endian) + (x-semop x-mode (.sym dst x-endian) (.sym src x-endian))) + ()))) -(define-pmacro (daiu x-basename x-op-code x-endian) +(define-pmacro (define-alu-insn-mov x-basename x-suffix x-op-class x-op-code + x-endian x-mode) (begin - (define-alu-insn-un x-basename "" OP_CLASS_ALU64 x-op-code x-endian) - (define-alu-insn-un x-basename "32" OP_CLASS_ALU x-op-code x-endian))) + (dni (.sym mov x-suffix "i" x-endian) + (.str mov x-suffix " immediate") + (endian-isas x-endian) + (.str x-basename x-suffix " $dst" x-endian ",$imm32") + (+ imm32 (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian) + x-op-class OP_SRC_K x-op-code) + (set x-mode (.sym dst x-endian) imm32) + ()) + (dni (.sym mov x-suffix "r" x-endian) + (.str mov x-suffix " register") + (endian-isas x-endian) + (.str x-basename x-suffix " $dst" x-endian ",$src" x-endian) + (+ (f-imm32 0) (f-offset16 0) (.sym src x-endian) (.sym dst x-endian) + x-op-class OP_SRC_X x-op-code) + (set x-mode (.sym dst x-endian) (.sym src x-endian)) + ()))) + -(define-pmacro (daib x-basename x-op-code x-endian) +;; Unary ALU instructions (neg) +(define-pmacro (daiu x-basename x-op-code x-endian x-semop) (begin - (define-alu-insn-bin x-basename "" OP_CLASS_ALU64 x-op-code x-endian) - (define-alu-insn-bin x-basename "32" OP_CLASS_ALU x-op-code x-endian))) + (define-alu-insn-un x-basename "" OP_CLASS_ALU64 x-op-code x-endian DI x-semop) + (define-alu-insn-un x-basename "32" OP_CLASS_ALU x-op-code x-endian USI x-semop))) + +;; Binary ALU instructions (all the others) +;; For ALU32: DST = (u32) DST OP (u32) SRC is correct semantics +(define-pmacro (daib x-basename x-op-code x-endian x-semop x-isas) + (begin + (define-alu-insn-bin x-basename "" OP_CLASS_ALU64 x-op-code x-endian DI x-semop x-isas) + (define-alu-insn-bin x-basename "32" OP_CLASS_ALU x-op-code x-endian USI x-semop x-isas))) + +;; Move ALU instructions (mov) +(define-pmacro (daim x-basename x-op-code x-endian) + (begin + (define-alu-insn-mov x-basename "" OP_CLASS_ALU64 x-op-code x-endian DI) + (define-alu-insn-mov x-basename "32" OP_CLASS_ALU x-op-code x-endian USI))) (define-pmacro (define-alu-instructions x-endian) (begin - (daib add OP_CODE_ADD x-endian) - (daib sub OP_CODE_SUB x-endian) - (daib mul OP_CODE_MUL x-endian) - (daib div OP_CODE_DIV x-endian) - (daib or OP_CODE_OR x-endian) - (daib and OP_CODE_AND x-endian) - (daib lsh OP_CODE_LSH x-endian) - (daib rsh OP_CODE_RSH x-endian) - (daib mod OP_CODE_MOD x-endian) - (daib xor OP_CODE_XOR x-endian) - (daib mov OP_CODE_MOV x-endian) - (daib arsh OP_CODE_ARSH x-endian) - (daiu neg OP_CODE_NEG x-endian))) + (daib add OP_CODE_ADD x-endian add (endian-isas x-endian)) + (daib sub OP_CODE_SUB x-endian sub (endian-isas x-endian)) + (daib mul OP_CODE_MUL x-endian mul (endian-isas x-endian)) + (daib div OP_CODE_DIV x-endian udiv (endian-isas x-endian)) + (daib or OP_CODE_OR x-endian or (endian-isas x-endian)) + (daib and OP_CODE_AND x-endian and (endian-isas x-endian)) + (daib lsh OP_CODE_LSH x-endian sll (endian-isas x-endian)) + (daib rsh OP_CODE_RSH x-endian srl (endian-isas x-endian)) + (daib mod OP_CODE_MOD x-endian umod (endian-isas x-endian)) + (daib xor OP_CODE_XOR x-endian xor (endian-isas x-endian)) + (daib arsh OP_CODE_ARSH x-endian sra (endian-isas x-endian)) + (daib sdiv OP_CODE_SDIV x-endian div ((ISA (.sym xbpf x-endian)))) + (daib smod OP_CODE_SMOD x-endian mod ((ISA (.sym xbpf x-endian)))) + (daiu neg OP_CODE_NEG x-endian neg) + (daim mov OP_CODE_MOV x-endian))) (define-alu-instructions le) (define-alu-instructions be) @@ -435,10 +521,13 @@ (define-pmacro (define-endian-insn x-suffix x-op-src x-endian) (dni (.sym "end" x-suffix x-endian) (.str "end" x-suffix " register") - ((ISA (.sym ebpf x-endian))) + (endian-isas x-endian) (.str "end" x-suffix " $dst" x-endian ",$endsize") (+ (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian) endsize - OP_CLASS_ALU x-op-src OP_CODE_END) () ())) + OP_CLASS_ALU x-op-src OP_CODE_END) + (set (.sym dst x-endian) + (c-call DI (.str "bpfbf_end" x-suffix) (.sym dst x-endian) endsize)) + ())) (define-endian-insn "le" OP_SRC_K le) (define-endian-insn "be" OP_SRC_X le) @@ -457,11 +546,13 @@ (define-pmacro (define-lddw x-endian) (dni (.sym lddw x-endian) (.str "lddw" x-endian) - ((ISA (.sym ebpf x-endian))) + (endian-isas x-endian) (.str "lddw $dst" x-endian ",$imm64") (+ imm64 (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian) - OP_CLASS_LD OP_SIZE_DW OP_MODE_IMM) () ())) + OP_CLASS_LD OP_SIZE_DW OP_MODE_IMM) + (set DI (.sym dst x-endian) imm64) + ())) (define-lddw le) (define-lddw be) @@ -471,19 +562,29 @@ ;; ;; LDABS{w,h,b,dw} -(define-pmacro (dlabs x-suffix x-size) +(define-pmacro (dlabs x-suffix x-size x-smode) (dni (.sym "ldabs" x-suffix) (.str "ldabs" x-suffix) (all-isas) (.str "ldabs" x-suffix " $imm32") (+ imm32 (f-offset16 0) (f-regs 0) OP_CLASS_LD OP_MODE_ABS (.sym OP_SIZE_ x-size)) - () ())) - -(dlabs "w" W) -(dlabs "h" H) -(dlabs "b" B) -(dlabs "dw" DW) + (set x-smode + (reg x-smode h-gpr 0) + (mem x-smode + (add DI + (mem DI + (add DI + (reg DI h-gpr 6) ;; Pointer to struct sk_buff + (c-call "bpfbf_skb_data_offset"))) + imm32))) + ;; XXX this clobbers R1-R5 + ())) + +(dlabs "w" W SI) +(dlabs "h" H HI) +(dlabs "b" B QI) +(dlabs "dw" DW DI) ;; The indirect load instructions are non-generic loads designed to be ;; used in socket filters. They come in several variants: @@ -491,21 +592,33 @@ ;; LDIND{w,h,b,dw}le for the little-endian ISA ;; LDIND[w,h,b,dw}be for the big-endian ISA -(define-pmacro (dlind x-suffix x-size x-endian) +(define-pmacro (dlind x-suffix x-size x-endian x-smode) (dni (.sym "ldind" x-suffix x-endian) (.str "ldind" x-suffix) - ((ISA (.sym ebpf x-endian))) + (endian-isas x-endian) (.str "ldind" x-suffix " $src" x-endian ",$imm32") (+ imm32 (f-offset16 0) ((.sym f-dst x-endian) 0) (.sym src x-endian) OP_CLASS_LD OP_MODE_IND (.sym OP_SIZE_ x-size)) - () ())) + (set x-smode + (reg x-smode h-gpr 0) + (mem x-smode + (add DI + (mem DI + (add DI + (reg DI h-gpr 6) ;; Pointer to struct sk_buff + (c-call "bpfbf_skb_data_offset"))) + (add DI + (.sym src x-endian) + imm32)))) + ;; XXX this clobbers R1-R5 + ())) (define-pmacro (define-ldind x-endian) (begin - (dlind "w" W x-endian) - (dlind "h" H x-endian) - (dlind "b" B x-endian) - (dlind "dw" DW x-endian))) + (dlind "w" W x-endian SI) + (dlind "h" H x-endian HI) + (dlind "b" B x-endian QI) + (dlind "dw" DW x-endian DI))) (define-ldind le) (define-ldind be) @@ -520,35 +633,41 @@ ;; Loads operate on [$SRC+-OFFSET] -> $DST ;; Stores operate on $SRC -> [$DST+-OFFSET] -(define-pmacro (dxli x-basename x-suffix x-size x-endian) +(define-pmacro (dxli x-basename x-suffix x-size x-endian x-mode) (dni (.sym x-basename x-suffix x-endian) (.str x-basename x-suffix) - ((ISA (.sym ebpf x-endian))) + (endian-isas x-endian) (.str x-basename x-suffix " $dst" x-endian ",[$src" x-endian "+$offset16]") (+ (f-imm32 0) offset16 (.sym src x-endian) (.sym dst x-endian) OP_CLASS_LDX (.sym OP_SIZE_ x-size) OP_MODE_MEM) - () ())) + (set x-mode + (.sym dst x-endian) + (mem x-mode (add DI (.sym src x-endian) offset16))) + ())) -(define-pmacro (dxsi x-basename x-suffix x-size x-endian) +(define-pmacro (dxsi x-basename x-suffix x-size x-endian x-mode) (dni (.sym x-basename x-suffix x-endian) (.str x-basename x-suffix) - ((ISA (.sym ebpf x-endian))) + (endian-isas x-endian) (.str x-basename x-suffix " [$dst" x-endian "+$offset16],$src" x-endian) (+ (f-imm32 0) offset16 (.sym src x-endian) (.sym dst x-endian) OP_CLASS_STX (.sym OP_SIZE_ x-size) OP_MODE_MEM) - () ())) + (set x-mode + (mem x-mode (add DI (.sym dst x-endian) offset16)) + (.sym src x-endian)) ;; XXX address is section-relative + ())) (define-pmacro (define-ldstx-insns x-endian) (begin - (dxli "ldx" "w" W x-endian) - (dxli "ldx" "h" H x-endian) - (dxli "ldx" "b" B x-endian) - (dxli "ldx" "dw" DW x-endian) + (dxli "ldx" "w" W x-endian SI) + (dxli "ldx" "h" H x-endian HI) + (dxli "ldx" "b" B x-endian QI) + (dxli "ldx" "dw" DW x-endian DI) - (dxsi "stx" "w" W x-endian) - (dxsi "stx" "h" H x-endian) - (dxsi "stx" "b" B x-endian) - (dxsi "stx" "dw" DW x-endian))) + (dxsi "stx" "w" W x-endian SI) + (dxsi "stx" "h" H x-endian HI) + (dxsi "stx" "b" B x-endian QI) + (dxsi "stx" "dw" DW x-endian DI))) (define-ldstx-insns le) (define-ldstx-insns be) @@ -559,20 +678,24 @@ ;; ST{b,h,w,dw}le for the little-endian ISA ;; ST{b,h,w,dw}be for the big-endian ISA -(define-pmacro (dsti x-suffix x-size x-endian) +(define-pmacro (dsti x-suffix x-size x-endian x-mode) (dni (.sym "st" x-suffix x-endian) (.str "st" x-suffix) - ((ISA (.sym ebpf x-endian))) + (endian-isas x-endian) (.str "st" x-suffix " [$dst" x-endian "+$offset16],$imm32") (+ imm32 offset16 ((.sym f-src x-endian) 0) (.sym dst x-endian) - OP_CLASS_ST (.sym OP_SIZE_ x-size) OP_MODE_MEM) () ())) + OP_CLASS_ST (.sym OP_SIZE_ x-size) OP_MODE_MEM) + (set x-mode + (mem x-mode (add DI (.sym dst x-endian) offset16)) + imm32) ;; XXX address is section-relative + ())) (define-pmacro (define-st-insns x-endian) (begin - (dsti "b" B x-endian) - (dsti "h" H x-endian) - (dsti "w" W x-endian) - (dsti "dw" DW x-endian))) + (dsti "b" B x-endian QI) + (dsti "h" H x-endian HI) + (dsti "w" W x-endian SI) + (dsti "dw" DW x-endian DI))) (define-st-insns le) (define-st-insns be) @@ -588,78 +711,145 @@ ;; J{eq,gt,ge,lt,le,set,ne.sgt,sge,slt,sle}[32]{i,r}be for the ;; big-endian ISA. -(define-pmacro (define-cond-jump-insn x-cond x-suffix x-op-class x-op-code x-endian) +(define-pmacro (define-cond-jump-insn x-cond x-suffix x-op-class x-op-code x-endian x-mode x-semop) (begin (dni (.sym j x-cond x-suffix i x-endian) (.str j x-cond x-suffix " i") - ((ISA (.sym ebpf x-endian))) + (endian-isas x-endian) (.str "j" x-cond x-suffix " $dst" x-endian ",$imm32,$disp16") (+ imm32 disp16 ((.sym f-src x-endian) 0) (.sym dst x-endian) - x-op-class OP_SRC_K (.sym OP_CODE_ x-op-code)) () ()) + x-op-class OP_SRC_K (.sym OP_CODE_ x-op-code)) + (if VOID (x-semop x-mode (.sym dst x-endian) imm32) + (set DI + (reg DI h-pc) (add DI (reg DI h-pc) + (mul DI (add HI disp16 1) 8)))) + ()) (dni (.sym j x-cond x-suffix r x-endian) (.str j x-cond x-suffix " r") - ((ISA (.sym ebpf x-endian))) + (endian-isas x-endian) (.str "j" x-cond x-suffix " $dst" x-endian ",$src" x-endian ",$disp16") (+ (f-imm32 0) disp16 (.sym src x-endian) (.sym dst x-endian) - x-op-class OP_SRC_X (.sym OP_CODE_ x-op-code)) () ()))) - -(define-pmacro (dcji x-cond x-op-code x-endian) + x-op-class OP_SRC_X (.sym OP_CODE_ x-op-code)) + (if VOID (x-semop x-mode (.sym dst x-endian) (.sym src x-endian)) + (set DI + (reg DI h-pc) (add DI (reg DI h-pc) + (mul DI (add HI disp16 1) 8)))) + ()))) + +(define-pmacro (dcji x-cond x-op-code x-endian x-semop) (begin - (define-cond-jump-insn x-cond "" OP_CLASS_JMP x-op-code x-endian) - (define-cond-jump-insn x-cond "32" OP_CLASS_JMP32 x-op-code x-endian))) + (define-cond-jump-insn x-cond "" OP_CLASS_JMP x-op-code x-endian DI x-semop) + (define-cond-jump-insn x-cond "32" OP_CLASS_JMP32 x-op-code x-endian SI x-semop ))) (define-pmacro (define-condjump-insns x-endian) (begin - (dcji "eq" JEQ x-endian) - (dcji "gt" JGT x-endian) - (dcji "ge" JGE x-endian) - (dcji "lt" JLT x-endian) - (dcji "le" JLE x-endian) - (dcji "set" JSET x-endian) - (dcji "ne" JNE x-endian) - (dcji "sgt" JSGT x-endian) - (dcji "sge" JSGE x-endian) - (dcji "slt" JSLT x-endian) - (dcji "sle" JSLE x-endian))) + (dcji "eq" JEQ x-endian eq) + (dcji "gt" JGT x-endian gtu) + (dcji "ge" JGE x-endian geu) + (dcji "lt" JLT x-endian ltu) + (dcji "le" JLE x-endian leu) + (dcji "set" JSET x-endian and) + (dcji "ne" JNE x-endian ne) + (dcji "sgt" JSGT x-endian gt) + (dcji "sge" JSGE x-endian ge) + (dcji "slt" JSLT x-endian lt) + (dcji "sle" JSLE x-endian le))) (define-condjump-insns le) (define-condjump-insns be) -;; The jump-always, `call' and `exit' instructions dont make use of -;; either source nor destination registers, so only one variant per +;; The `call' instruction doesn't make use of registers, but the +;; semantic routine should have access to the src register in order to +;; properly interpret the meaning of disp32. Therefore we need one +;; version per ISA. + +(define-pmacro (define-call-insn x-endian) + (dni (.sym call x-endian) + "call" + (endian-isas x-endian) + "call $disp32" + (+ disp32 (f-offset16 0) (f-regs 0) + OP_CLASS_JMP OP_SRC_K OP_CODE_CALL) + (c-call VOID + "bpfbf_call" disp32 (ifield (.sym f-src x-endian))) + ())) + +(define-call-insn le) +(define-call-insn be) + +(define-pmacro (define-callr-insn x-endian) + (dni (.sym callr x-endian) + "callr" + ((ISA (.sym xbpf x-endian))) + (.str "call $dst" x-endian) + (+ (f-imm32 0) (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian) + OP_CLASS_JMP OP_SRC_X OP_CODE_CALL) + (c-call VOID + "bpfbf_callr" (ifield (.sym f-dst x-endian))) + ())) + +(define-callr-insn le) +(define-callr-insn be) + +;; The jump-always and `exit' instructions dont make use of either +;; source nor destination registers, so only one variant per ;; instruction is defined. (dni ja "ja" (all-isas) "ja $disp16" (+ (f-imm32 0) disp16 (f-regs 0) - OP_CLASS_JMP OP_SRC_K OP_CODE_JA) () ()) - -(dni call "call" (all-isas) "call $disp32" - (+ disp32 (f-offset16 0) (f-regs 0) - OP_CLASS_JMP OP_SRC_K OP_CODE_CALL) () ()) + OP_CLASS_JMP OP_SRC_K OP_CODE_JA) + (set DI (reg DI h-pc) (add DI (reg DI h-pc) + (mul DI (add HI disp16 1) 8))) + ()) (dni "exit" "exit" (all-isas) "exit" (+ (f-imm32 0) (f-offset16 0) (f-regs 0) - OP_CLASS_JMP (f-op-src 0) OP_CODE_EXIT) () ()) + OP_CLASS_JMP (f-op-src 0) OP_CODE_EXIT) + (c-call VOID "bpfbf_exit") + ()) ;;; Atomic instructions ;; The atomic exchange-and-add instructions come in two flavors: one ;; for swapping 64-bit quantities and another for 32-bit quantities. +(define-pmacro (sem-exchange-and-add x-endian x-mode) + (sequence VOID ((x-mode tmp)) + ;; XXX acquire lock in simulator... as a hardware element? + (set x-mode tmp (mem x-mode (add DI (.sym dst x-endian) offset16))) + (set x-mode + (mem x-mode (add DI (.sym dst x-endian) offset16)) + (add x-mode tmp (.sym src x-endian))))) + (define-pmacro (define-atomic-insns x-endian) (begin (dni (.str "xadddw" x-endian) "xadddw" - ((ISA (.sym ebpf x-endian))) + (endian-isas x-endian) (.str "xadddw [$dst" x-endian "+$offset16],$src" x-endian) (+ (f-imm32 0) (.sym src x-endian) (.sym dst x-endian) - offset16 OP_MODE_XADD OP_SIZE_DW OP_CLASS_STX) () ()) + offset16 OP_MODE_XADD OP_SIZE_DW OP_CLASS_STX) + (sem-exchange-and-add x-endian DI) + ()) (dni (.str "xaddw" x-endian) "xaddw" - ((ISA (.sym ebpf x-endian))) + (endian-isas x-endian) (.str "xaddw [$dst" x-endian "+$offset16],$src" x-endian) (+ (f-imm32 0) (.sym src x-endian) (.sym dst x-endian) - offset16 OP_MODE_XADD OP_SIZE_W OP_CLASS_STX) () ()))) + offset16 OP_MODE_XADD OP_SIZE_W OP_CLASS_STX) + (sem-exchange-and-add x-endian SI) + ()))) (define-atomic-insns le) (define-atomic-insns be) + +;;; Breakpoint instruction + +;; The brkpt instruction is used by the BPF simulator and it doesn't +;; really belong to the eBPF instruction set. + +(dni "brkpt" "brkpt" (all-isas) "brkpt" + (+ (f-imm32 0) (f-offset16 0) (f-regs 0) + OP_CLASS_ALU OP_SRC_X OP_CODE_NEG) + (c-call VOID "bpfbf_breakpoint") + ())