X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=cpu%2Fexec_context.hh;h=6a17951f95bd693473bec2006cf58136026f452b;hb=5aa71721193c49016ffa69934b44ce38672e4eed;hp=d6140d52fe5d378275259a027ea30b3c79a2224c;hpb=c12a665c3120b61ed4e09da5d8a52c57406763d5;p=gem5.git

diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index d6140d52f..6a17951f9 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2001-2004 The Regents of The University of Michigan
+ * Copyright (c) 2001-2005 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -26,12 +26,13 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __EXEC_CONTEXT_HH__
-#define __EXEC_CONTEXT_HH__
+#ifndef __CPU_EXEC_CONTEXT_HH__
+#define __CPU_EXEC_CONTEXT_HH__
 
-#include "sim/host.hh"
+#include "config/full_system.hh"
+#include "mem/functional/functional.hh"
 #include "mem/mem_req.hh"
-#include "mem/functional_mem/functional_memory.hh"
+#include "sim/host.hh"
 #include "sim/serialize.hh"
 #include "targetarch/byte_swap.hh"
 
@@ -40,7 +41,7 @@ class FunctionalMemory;
 class PhysicalMemory;
 class BaseCPU;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 
 #include "sim/system.hh"
 #include "targetarch/alpha_memory.hh"
@@ -121,7 +122,7 @@ class ExecContext
     // it belongs.  For full-system mode, this is the system CPU ID.
     int cpu_id;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     FunctionalMemory *mem;
     AlphaITB *itb;
     AlphaDTB *dtb;
@@ -176,7 +177,7 @@ class ExecContext
     unsigned storeCondFailures;
 
     // constructor: initialize context from given process structure
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
                 AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem);
 #else
@@ -193,7 +194,7 @@ class ExecContext
     void serialize(std::ostream &os);
     void unserialize(Checkpoint *cp, const std::string &section);
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     bool validInstAddr(Addr addr) { return true; }
     bool validDataAddr(Addr addr) { return true; }
     int getInstAsid() { return regs.instAsid(); }
@@ -253,7 +254,7 @@ class ExecContext
     template <class T>
     Fault read(MemReqPtr &req, T &data)
     {
-#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
+#if FULL_SYSTEM && defined(TARGET_ALPHA)
         if (req->flags & LOCKED) {
             MiscRegFile *cregs = &req->xc->regs.miscRegs;
             cregs->lock_addr = req->paddr;
@@ -263,14 +264,14 @@ class ExecContext
 
         Fault error;
         error = mem->read(req, data);
-        data = htoa(data);
+        data = gtoh(data);
         return error;
     }
 
     template <class T>
     Fault write(MemReqPtr &req, T &data)
     {
-#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
+#if FULL_SYSTEM && defined(TARGET_ALPHA)
 
         MiscRegFile *cregs;
 
@@ -313,7 +314,7 @@ class ExecContext
         }
 
 #endif
-        return mem->write(req, (T)htoa(data));
+        return mem->write(req, (T)htog(data));
     }
 
     virtual bool misspeculating();
@@ -404,7 +405,7 @@ class ExecContext
         regs.miscRegs.fpcr = val;
     }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     uint64_t readIpr(int idx, Fault &fault);
     Fault setIpr(int idx, uint64_t val);
     int readIntrFlag() { return regs.intrflag; }
@@ -423,7 +424,7 @@ class ExecContext
 
     void trap(Fault fault);
 
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
     IntReg getSyscallArg(int i)
     {
         return regs.intRegFile[ArgumentReg0 + i];
@@ -467,4 +468,4 @@ ExecContext::misspeculating()
     return false;
 }
 
-#endif // __EXEC_CONTEXT_HH__
+#endif // __CPU_EXEC_CONTEXT_HH__