X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=cpu%2Fexec_context.hh;h=8437a558541887aa3b38087361dcca57bdfd48a4;hb=bd878a09045e811b0ad626ec15ae9e5fd76d62e1;hp=ccb01f486a85971e800082e09b4eead912a9a9eb;hpb=7c089b2001afb93fe51b1a89456b15fd0d00c794;p=gem5.git

diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index ccb01f486..8437a5585 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2001-2004 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -31,7 +31,9 @@
 
 #include "sim/host.hh"
 #include "mem/mem_req.hh"
+#include "mem/functional_mem/functional_memory.hh"
 #include "sim/serialize.hh"
+#include "targetarch/byte_swap.hh"
 
 // forward declaration: see functional_memory.hh
 class FunctionalMemory;
@@ -40,15 +42,12 @@ class BaseCPU;
 
 #ifdef FULL_SYSTEM
 
-#include "targetarch/alpha_memory.hh"
-class MemoryController;
-
-#include "kern/tru64/kernel_stats.hh"
 #include "sim/system.hh"
+#include "targetarch/alpha_memory.hh"
 
-#ifdef FS_MEASURE
-#include "sim/sw_context.hh"
-#endif
+class MemoryController;
+class StaticInstBase;
+namespace Kernel { class Binning; class Statistics; }
 
 #else // !FULL_SYSTEM
 
@@ -106,17 +105,15 @@ class ExecContext
     /// Set the status to Halted.
     void halt();
 
-#ifdef FULL_SYSTEM
-  public:
-    KernelStats kernelStats;
-#endif
-
   public:
     RegFile regs;	// correct-path register context
 
     // pointer to CPU associated with this context
     BaseCPU *cpu;
 
+    // Current instruction
+    MachInst inst;
+
     // Index of hardware thread context on the CPU that this represents.
     int thread_num;
 
@@ -125,21 +122,22 @@ class ExecContext
     int cpu_id;
 
 #ifdef FULL_SYSTEM
-
     FunctionalMemory *mem;
-    AlphaItb *itb;
-    AlphaDtb *dtb;
+    AlphaITB *itb;
+    AlphaDTB *dtb;
     System *system;
 
     // the following two fields are redundant, since we can always
     // look them up through the system pointer, but we'll leave them
     // here for now for convenience
-    MemoryController *memCtrl;
+    MemoryController *memctrl;
     PhysicalMemory *physmem;
 
-#ifdef FS_MEASURE
-    SWContext *swCtx;
-#endif
+    Kernel::Binning *kernelBinning;
+    Kernel::Statistics *kernelStats;
+    bool bin;
+    bool fnbin;
+    void execute(const StaticInstBase *inst);
 
 #else
     Process *process;
@@ -180,13 +178,13 @@ class ExecContext
     // constructor: initialize context from given process structure
 #ifdef FULL_SYSTEM
     ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
-                AlphaItb *_itb, AlphaDtb *_dtb, FunctionalMemory *_dem);
+                AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem);
 #else
     ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
     ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
                 int _asid);
 #endif
-    virtual ~ExecContext() {}
+    virtual ~ExecContext();
 
     virtual void takeOverFrom(ExecContext *oldContext);
 
@@ -198,8 +196,8 @@ class ExecContext
 #ifdef FULL_SYSTEM
     bool validInstAddr(Addr addr) { return true; }
     bool validDataAddr(Addr addr) { return true; }
-    int getInstAsid() { return ITB_ASN_ASN(regs.ipr[TheISA::IPR_ITB_ASN]); }
-    int getDataAsid() { return DTB_ASN_ASN(regs.ipr[TheISA::IPR_DTB_ASN]); }
+    int getInstAsid() { return regs.instAsid(); }
+    int getDataAsid() { return regs.dataAsid(); }
 
     Fault translateInstReq(MemReqPtr &req)
     {
@@ -262,7 +260,11 @@ class ExecContext
             cregs->lock_flag = true;
         }
 #endif
-        return mem->read(req, data);
+
+        Fault error;
+        error = mem->read(req, data);
+        data = htoa(data);
+        return error;
     }
 
     template <class T>
@@ -311,12 +313,24 @@ class ExecContext
         }
 
 #endif
-        return mem->write(req, data);
+        return mem->write(req, (T)htoa(data));
     }
 
     virtual bool misspeculating();
 
 
+    MachInst getInst() { return inst; }
+
+    void setInst(MachInst new_inst)
+    {
+        inst = new_inst;
+    }
+
+    Fault instRead(MemReqPtr &req)
+    {
+        return mem->read(req, inst);
+    }
+
     //
     // New accessors for new decoder.
     //
@@ -393,11 +407,22 @@ class ExecContext
 #ifdef FULL_SYSTEM
     uint64_t readIpr(int idx, Fault &fault);
     Fault setIpr(int idx, uint64_t val);
+    int readIntrFlag() { return regs.intrflag; }
+    void setIntrFlag(int val) { regs.intrflag = val; }
     Fault hwrei();
+    bool inPalMode() { return AlphaISA::PcPAL(regs.pc); }
     void ev5_trap(Fault fault);
     bool simPalCheck(int palFunc);
 #endif
 
+    /** Meant to be more generic trap function to be
+     *  called when an instruction faults.
+     *  @param fault The fault generated by executing the instruction.
+     *  @todo How to do this properly so it's dependent upon ISA only?
+     */
+
+    void trap(Fault fault);
+
 #ifndef FULL_SYSTEM
     IntReg getSyscallArg(int i)
     {