X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=cpu.py;h=eabe9d85f2157e4ce02c2049e90a8535aaf37243;hb=bd2c1c1d66e3d82d1080f77382e8af2c41559db6;hp=c8dafdeb3a10938d0a4d0c34270a07b1e0132b5b;hpb=e103247b196ca128bfbf4b4c6c0d68e63e64b98b;p=rv32.git

diff --git a/cpu.py b/cpu.py
index c8dafde..eabe9d8 100644
--- a/cpu.py
+++ b/cpu.py
@@ -622,6 +622,11 @@ class CPU(Module):
         self.comb += self.get_csr_op_is_valid(csr_op_is_valid, csr_number,
                                               csr_reads, csr_writes)
 
+        # TODO
+        cycle_counter   = Signal(64); # TODO: implement cycle_counter
+        time_counter    = Signal(64); # TODO: implement time_counter
+        instret_counter = Signal(64); # TODO: implement instret_counter
+
 if __name__ == "__main__":
     example = CPU()
     print(verilog.convert(example,