X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=crypto_router_asic.mdwn;h=c877516d2e762d702700ff82ea5ec0bcb4c855f1;hb=b796022efab330deb729e3c89f5ef47ce86bb81f;hp=24191cefb8bcd4e7d855846d12f270d4d8d20d89;hpb=d58486e51ad21516b955d2d739423e783b03f9e5;p=libreriscv.git

diff --git a/crypto_router_asic.mdwn b/crypto_router_asic.mdwn
index 24191cefb..c877516d2 100644
--- a/crypto_router_asic.mdwn
+++ b/crypto_router_asic.mdwn
@@ -1,7 +1,18 @@
 # Crypto-router ASIC
 
+<img src="https://www.ngi.eu/wp-content/uploads/sites/48/2020/04/Logo_Pointer.png" width="200px" />
+<img src="https://ngi.eu/wp-content/uploads/sites/77/2017/10/bandiera_stelle.png" width="50px" /><span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</span>
+<img src="https://nlnet.nl/image/logos/NGIAssure_tag.svg" width="130px" />
+<span>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</span>
+<img src="https://www.artandtechnology.nl/logo.jpg" width="130px" />
+
+**This project has received funding from the European Union’s Horizon 2020 research and innovation programme within the framework of the NGI-POINTER Project funded under grant agreement No 871528**
+
+**This project has received funding from the European Union’s Horizon 2020 research and innovation programme within the framework of the NGI-ASSURE Project funded under grant agreement No 957073.**
+
 * NLnet page: [[nlnet_2021_crypto_router]]
 * Top-level bugreport: <https://bugs.libre-soc.org/show_bug.cgi?id=589>
+* ASIC/IO Pin specification page: [[crypto_router_asic/crypto_router_pinspec]]
 
 # Specifications
 
@@ -12,7 +23,9 @@ All of these are entirely Libre-Licensed or are to be written as Libre-Licensed:
   OpenPOWER CPU with
   [[openpower/sv/bitmanip]] extensions
 * 180/130 nm (TBD)
-* 5x [[shakti/m_class/RGMII]] Gigabit Ethernet PHYs
+* 5x [[shakti/m_class/RGMII]] Gigabit Ethernet PHYs with
+  [SRAM](https://github.com/adamgreig/daqnet/blob/master/gateware/daqnet/ethernet/rmii.py)
+   on-chip, built-in.
 * 2x USB [[shakti/m_class/ULPI]] PHYs
 * Direct DMA interface (independent bulk transfer)
 * [JTAG](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/jtag.py;hb=HEAD),
@@ -51,7 +64,7 @@ These may be achieved as follows:
   Example [bpermd proof](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/formal/proof_bpermd.py;hb=HEAD)
   and individual unit tests for the
   [Logical pipeline](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/test/test_pipe_caller.py;hb=HEAD)
-* [Litex sim.py](https://git.libre-soc.org/?p=libresoc-litex.git;a=blob;f=sim.py;hb=HEAD)
+* simulation
   with some peripherals developed in c++ as verilator modules
 * nmigen-based OpenPOWER Libre-SOC core co-simulation such as
   this unit test,