X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=crypto_router_asic.mdwn;h=c877516d2e762d702700ff82ea5ec0bcb4c855f1;hb=f4c06f2c90ef7d8c38f39306713f37aad6d4564f;hp=c91744b12f6133fb85a1625b483c050d38c5076d;hpb=3d08fba12e5c7a16b8db25be0dbc6256088334d4;p=libreriscv.git
diff --git a/crypto_router_asic.mdwn b/crypto_router_asic.mdwn
index c91744b12..c877516d2 100644
--- a/crypto_router_asic.mdwn
+++ b/crypto_router_asic.mdwn
@@ -1,7 +1,18 @@
# Crypto-router ASIC
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+**This project has received funding from the European Unionâs Horizon 2020 research and innovation programme within the framework of the NGI-POINTER Project funded under grant agreement No 871528**
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+**This project has received funding from the European Unionâs Horizon 2020 research and innovation programme within the framework of the NGI-ASSURE Project funded under grant agreement No 957073.**
+
* NLnet page: [[nlnet_2021_crypto_router]]
* Top-level bugreport:
+* ASIC/IO Pin specification page: [[crypto_router_asic/crypto_router_pinspec]]
# Specifications
@@ -53,7 +64,7 @@ These may be achieved as follows:
Example [bpermd proof](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/formal/proof_bpermd.py;hb=HEAD)
and individual unit tests for the
[Logical pipeline](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/test/test_pipe_caller.py;hb=HEAD)
-* [Litex sim.py](https://git.libre-soc.org/?p=libresoc-litex.git;a=blob;f=sim.py;hb=HEAD)
+* simulation
with some peripherals developed in c++ as verilator modules
* nmigen-based OpenPOWER Libre-SOC core co-simulation such as
this unit test,