X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=debug%2Ftargets%2FRISC-V%2Fspike32.py;h=a831ecbb2af2ae63d9e5a0cbcfbe870885cefa0b;hb=4dddbc79ada7f0a836cf538676c57c8df103ccf6;hp=e80f60a07a51e6ae38ee0b2afad51f201e1f0146;hpb=3a44725d27f6b2c77f0ca912d792b6856fde6a17;p=riscv-tests.git

diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py
index e80f60a..a831ecb 100644
--- a/debug/targets/RISC-V/spike32.py
+++ b/debug/targets/RISC-V/spike32.py
@@ -6,12 +6,15 @@ class spike32_hart(targets.Hart):
     ram = 0x10000000
     ram_size = 0x10000000
     instruction_hardware_breakpoint_count = 4
-    reset_vector = 0x1000
-    link_script_path = "spike64.lds"
+    reset_vectors = [0x1000]
+    link_script_path = "spike32.lds"
 
 class spike32(targets.Target):
     harts = [spike32_hart()]
-    openocd_config_path = "spike.cfg"
+    openocd_config_path = "spike-1.cfg"
+    timeout_sec = 30
+    implements_custom_test = True
 
     def create(self):
-        return testlib.Spike(self)
+        # 64-bit FPRs on 32-bit target
+        return testlib.Spike(self, isa="RV32IMAFDC")