X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=dev%2Fide_ctrl.hh;h=b29e5ae9a1d3bc797b18e3f374d287ff07321670;hb=c9e6a15196a87fd1aa923b9ee0f6ff736ad6d33b;hp=cfdef8e3a2d9c7798e39858fd3301b55afb3ba71;hpb=07448480fc4c6d17d9645c051977fcc5fe392f6c;p=gem5.git

diff --git a/dev/ide_ctrl.hh b/dev/ide_ctrl.hh
index cfdef8e3a..b29e5ae9a 100644
--- a/dev/ide_ctrl.hh
+++ b/dev/ide_ctrl.hh
@@ -74,10 +74,6 @@
 #define UDMACTL (5)
 #define UDMATIM (6)
 
-// PCI Command bit fields
-#define BME     0x04 // Bus master function enable
-#define IOSE    0x01 // I/O space enable
-
 typedef enum RegType {
     COMMAND_BLOCK = 0,
     CONTROL_BLOCK,
@@ -148,6 +144,10 @@ class IdeController : public PciDev
     /** Select the disk based on a pointer */
     int getDisk(IdeDisk *diskPtr);
 
+  public:
+    /** See if a disk is selected based on its pointer */
+    bool isDiskSelected(IdeDisk *diskPtr);
+
   public:
     /**
      * Constructs and initializes this controller.
@@ -167,7 +167,7 @@ class IdeController : public PciDev
                   MemoryController *mmu, PciConfigAll *cf,
                   PciConfigData *cd, Tsunami *t,
                   uint32_t bus_num, uint32_t dev_num, uint32_t func_num,
-                  Bus *host_bus, HierParams *hier);
+                  Bus *host_bus, Tick pio_latency, HierParams *hier);
 
     /**
      * Deletes the connected devices.
@@ -198,12 +198,6 @@ class IdeController : public PciDev
      */
     virtual Fault write(MemReqPtr &req, const uint8_t *data);
 
-    /**
-     * Cache access timing specific to device
-     * @param req Memory request
-     */
-    Tick cacheAccess(MemReqPtr &req);
-
     /**
      * Serialize this object to the given output stream.
      * @param os The stream to serialize to.
@@ -217,5 +211,11 @@ class IdeController : public PciDev
      */
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 
+    /**
+     * Return how long this access will take.
+     * @param req the memory request to calcuate
+     * @return Tick when the request is done
+     */
+    Tick cacheAccess(MemReqPtr &req);
 };
 #endif // __IDE_CTRL_HH_