X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=dev%2Fns_gige.hh;h=181837c8df5d241971eab37b012734b906ee300d;hb=466284b5d29ad0d44c1b020353cf7521be2b90de;hp=50472d5bc0dfb48bc822ff14b9914f201f7c22a1;hpb=29789443ba5471c954617d8a21f5db94c6512f02;p=gem5.git diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh index 50472d5bc..181837c8d 100644 --- a/dev/ns_gige.hh +++ b/dev/ns_gige.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2004 The Regents of The University of Michigan + * Copyright (c) 2004-2005 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -26,7 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* @file +/** @file * Device module for modelling the National Semiconductor * DP83820 ethernet controller */ @@ -45,6 +45,17 @@ #include "mem/bus/bus.hh" #include "sim/eventq.hh" +// Hash filtering constants +const uint16_t FHASH_ADDR = 0x100; +const uint16_t FHASH_SIZE = 0x100; + +// EEPROM constants +const uint8_t EEPROM_READ = 0x2; +const uint8_t EEPROM_SIZE = 64; // Size in words of NSC93C46 EEPROM +const uint8_t EEPROM_PMATCH2_ADDR = 0xA; // EEPROM Address of PMATCH word 2 +const uint8_t EEPROM_PMATCH1_ADDR = 0xB; // EEPROM Address of PMATCH word 1 +const uint8_t EEPROM_PMATCH0_ADDR = 0xC; // EEPROM Address of PMATCH word 0 + /** * Ethernet device registers */ @@ -69,6 +80,8 @@ struct dp_regs { uint32_t pcr; uint32_t rfcr; uint32_t rfdr; + uint32_t brar; + uint32_t brdr; uint32_t srr; uint32_t mibc; uint32_t vrcr; @@ -89,6 +102,12 @@ struct dp_rom { * the linux driver doesn't use any other ROM */ uint8_t perfectMatch[ETH_ADDR_LEN]; + + /** + * for hash table memory. + * used by the freebsd driver + */ + uint8_t filterHash[FHASH_SIZE]; }; class NSGigEInt; @@ -99,7 +118,7 @@ class Bus; class PciConfigAll; /** - * NS DP82830 Ethernet device model + * NS DP83820 Ethernet device model */ class NSGigE : public PciDev { @@ -137,14 +156,20 @@ class NSGigE : public PciDev dmaWriteWaiting }; + /** EEPROM State Machine States */ + enum EEPROMState + { + eepromStart, + eepromGetOpcode, + eepromGetAddress, + eepromRead + }; + private: Addr addr; static const Addr size = sizeof(dp_regs); protected: - typedef std::deque pktbuf_t; - typedef pktbuf_t::iterator pktiter_t; - /** device register file */ dp_regs regs; dp_rom rom; @@ -172,8 +197,14 @@ class NSGigE : public PciDev bool txDmaFree; /** DescCaches */ - ns_desc txDescCache; - ns_desc rxDescCache; + ns_desc32 txDesc32; + ns_desc32 rxDesc32; + ns_desc64 txDesc64; + ns_desc64 rxDesc64; + + /* state machine cycle time */ + Tick clock; + inline Tick cycles(int numCycles) const { return numCycles * clock; } /* tx State Machine */ TxState txState; @@ -205,8 +236,25 @@ class NSGigE : public PciDev uint32_t rxDescCnt; DmaState rxDmaState; + struct RegWriteData { + Addr daddr; + uint32_t value; + RegWriteData(Addr da, uint32_t val) : daddr(da), value(val) {} + }; + + std::vector > writeQueue; + bool pioDelayWrite; + bool extstsEnable; + /** EEPROM State Machine */ + EEPROMState eepromState; + bool eepromClk; + uint8_t eepromBitsToRx; + uint8_t eepromOpcode; + uint8_t eepromAddress; + uint16_t eepromData; + protected: Tick dmaReadDelay; Tick dmaWriteDelay; @@ -249,7 +297,6 @@ class NSGigE : public PciDev bool dmaDescFree; bool dmaDataFree; - protected: Tick txDelay; Tick rxDelay; @@ -261,12 +308,16 @@ class NSGigE : public PciDev void rxKick(); Tick rxKickTick; typedef EventWrapper RxKickEvent; - friend class RxKickEvent; + friend void RxKickEvent::process(); + RxKickEvent rxKickEvent; void txKick(); Tick txKickTick; typedef EventWrapper TxKickEvent; - friend class TxKickEvent; + friend void TxKickEvent::process(); + TxKickEvent txKickEvent; + + void eepromKick(); /** * Retransmit event @@ -279,7 +330,7 @@ class NSGigE : public PciDev txKick(); } typedef EventWrapper TxEvent; - friend class TxEvent; + friend void TxEvent::process(); TxEvent txEvent; void txDump() const; @@ -295,6 +346,7 @@ class NSGigE : public PciDev bool acceptUnicast; bool acceptPerfect; bool acceptArp; + bool multicastHashEnable; PhysicalMemory *physmem; @@ -313,7 +365,7 @@ class NSGigE : public PciDev void cpuIntrClear(); typedef EventWrapper IntrEvent; - friend class IntrEvent; + friend void IntrEvent::process(); IntrEvent *intrEvent; NSGigEInt *interface; @@ -322,12 +374,15 @@ class NSGigE : public PciDev { PhysicalMemory *pmem; HierParams *hier; + Bus *pio_bus; Bus *header_bus; Bus *payload_bus; + Tick clock; Tick intr_delay; Tick tx_delay; Tick rx_delay; Tick pio_latency; + bool pio_delay_write; bool dma_desc_free; bool dma_data_free; Tick dma_read_delay; @@ -338,17 +393,20 @@ class NSGigE : public PciDev Net::EthAddr eaddr; uint32_t tx_fifo_size; uint32_t rx_fifo_size; + bool rx_thread; + bool tx_thread; + bool dma_no_allocate; }; NSGigE(Params *params); ~NSGigE(); const Params *params() const { return (const Params *)_params; } - virtual void WriteConfig(int offset, int size, uint32_t data); - virtual void ReadConfig(int offset, int size, uint8_t *data); + virtual void writeConfig(int offset, int size, const uint8_t *data); + virtual void readConfig(int offset, int size, uint8_t *data); - virtual Fault read(MemReqPtr &req, uint8_t *data); - virtual Fault write(MemReqPtr &req, const uint8_t *data); + virtual Fault * read(MemReqPtr &req, uint8_t *data); + virtual Fault * write(MemReqPtr &req, const uint8_t *data); bool cpuIntrPending() const; void cpuIntrAck() { cpuIntrClear(); }