X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=dev%2Fns_gige.hh;h=181837c8df5d241971eab37b012734b906ee300d;hb=466284b5d29ad0d44c1b020353cf7521be2b90de;hp=a8d8d1f18dac194b06cd0f2220b019038b770471;hpb=7ca7b343ff9949293a005aab9aec06cc7fb98093;p=gem5.git diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh index a8d8d1f18..181837c8d 100644 --- a/dev/ns_gige.hh +++ b/dev/ns_gige.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2004 The Regents of The University of Michigan + * Copyright (c) 2004-2005 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -26,31 +26,35 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* @file +/** @file * Device module for modelling the National Semiconductor * DP83820 ethernet controller */ -#ifndef __NS_GIGE_HH__ -#define __NS_GIGE_HH__ +#ifndef __DEV_NS_GIGE_HH__ +#define __DEV_NS_GIGE_HH__ -//#include "base/range.hh" +#include "base/inet.hh" +#include "base/statistics.hh" #include "dev/etherint.hh" #include "dev/etherpkt.hh" -#include "sim/eventq.hh" +#include "dev/io_device.hh" #include "dev/ns_gige_reg.h" -#include "base/statistics.hh" #include "dev/pcidev.hh" -#include "dev/tsunami.hh" -#include "dev/io_device.hh" +#include "dev/pktfifo.hh" #include "mem/bus/bus.hh" +#include "sim/eventq.hh" -/** defined by the NS83820 data sheet */ -#define MAX_TX_FIFO_SIZE 8192 -#define MAX_RX_FIFO_SIZE 32768 +// Hash filtering constants +const uint16_t FHASH_ADDR = 0x100; +const uint16_t FHASH_SIZE = 0x100; -/** length of ethernet address in bytes */ -#define EADDR_LEN 6 +// EEPROM constants +const uint8_t EEPROM_READ = 0x2; +const uint8_t EEPROM_SIZE = 64; // Size in words of NSC93C46 EEPROM +const uint8_t EEPROM_PMATCH2_ADDR = 0xA; // EEPROM Address of PMATCH word 2 +const uint8_t EEPROM_PMATCH1_ADDR = 0xB; // EEPROM Address of PMATCH word 1 +const uint8_t EEPROM_PMATCH0_ADDR = 0xC; // EEPROM Address of PMATCH word 0 /** * Ethernet device registers @@ -76,6 +80,8 @@ struct dp_regs { uint32_t pcr; uint32_t rfcr; uint32_t rfdr; + uint32_t brar; + uint32_t brdr; uint32_t srr; uint32_t mibc; uint32_t vrcr; @@ -91,11 +97,19 @@ struct dp_regs { }; struct dp_rom { - /** for perfect match memory. the linux driver doesn't use any other ROM */ - uint8_t perfectMatch[EADDR_LEN]; + /** + * for perfect match memory. + * the linux driver doesn't use any other ROM + */ + uint8_t perfectMatch[ETH_ADDR_LEN]; + + /** + * for hash table memory. + * used by the freebsd driver + */ + uint8_t filterHash[FHASH_SIZE]; }; -class IntrControl; class NSGigEInt; class PhysicalMemory; class BaseInterface; @@ -104,7 +118,7 @@ class Bus; class PciConfigAll; /** - * NS DP82830 Ethernet device model + * NS DP83820 Ethernet device model */ class NSGigE : public PciDev { @@ -142,18 +156,20 @@ class NSGigE : public PciDev dmaWriteWaiting }; - private: - /** pointer to the chipset */ - Tsunami *tsunami; + /** EEPROM State Machine States */ + enum EEPROMState + { + eepromStart, + eepromGetOpcode, + eepromGetAddress, + eepromRead + }; private: Addr addr; static const Addr size = sizeof(dp_regs); protected: - typedef std::deque pktbuf_t; - typedef pktbuf_t::iterator pktiter_t; - /** device register file */ dp_regs regs; dp_rom rom; @@ -167,8 +183,8 @@ class NSGigE : public PciDev /*** BASIC STRUCTURES FOR TX/RX ***/ /* Data FIFOs */ - pktbuf_t txFifo; - pktbuf_t rxFifo; + PacketFifo txFifo; + PacketFifo rxFifo; /** various helper vars */ PacketPtr txPacket; @@ -181,15 +197,21 @@ class NSGigE : public PciDev bool txDmaFree; /** DescCaches */ - ns_desc txDescCache; - ns_desc rxDescCache; + ns_desc32 txDesc32; + ns_desc32 rxDesc32; + ns_desc64 txDesc64; + ns_desc64 rxDesc64; + + /* state machine cycle time */ + Tick clock; + inline Tick cycles(int numCycles) const { return numCycles * clock; } /* tx State Machine */ TxState txState; + bool txEnable; + /** Current Transmit Descriptor Done */ bool CTDD; - /** current amt of free space in txDataFifo in bytes */ - uint32_t txFifoAvail; /** halt the tx state machine after next packet */ bool txHalt; /** ptr to the next byte in the current fragment */ @@ -200,12 +222,12 @@ class NSGigE : public PciDev /** rx State Machine */ RxState rxState; + bool rxEnable; + /** Current Receive Descriptor Done */ bool CRDD; /** num of bytes in the current packet being drained from rxDataFifo */ uint32_t rxPktBytes; - /** number of bytes in the rxFifo */ - uint32_t rxFifoCnt; /** halt the rx state machine after current packet */ bool rxHalt; /** ptr to the next byte in current fragment */ @@ -214,8 +236,25 @@ class NSGigE : public PciDev uint32_t rxDescCnt; DmaState rxDmaState; + struct RegWriteData { + Addr daddr; + uint32_t value; + RegWriteData(Addr da, uint32_t val) : daddr(da), value(val) {} + }; + + std::vector > writeQueue; + bool pioDelayWrite; + bool extstsEnable; + /** EEPROM State Machine */ + EEPROMState eepromState; + bool eepromClk; + uint8_t eepromBitsToRx; + uint8_t eepromOpcode; + uint8_t eepromAddress; + uint16_t eepromData; + protected: Tick dmaReadDelay; Tick dmaWriteDelay; @@ -258,7 +297,6 @@ class NSGigE : public PciDev bool dmaDescFree; bool dmaDataFree; - protected: Tick txDelay; Tick rxDelay; @@ -270,19 +308,29 @@ class NSGigE : public PciDev void rxKick(); Tick rxKickTick; typedef EventWrapper RxKickEvent; - friend class RxKickEvent; + friend void RxKickEvent::process(); + RxKickEvent rxKickEvent; void txKick(); Tick txKickTick; typedef EventWrapper TxKickEvent; - friend class TxKickEvent; + friend void TxKickEvent::process(); + TxKickEvent txKickEvent; + + void eepromKick(); /** * Retransmit event */ void transmit(); - typedef EventWrapper TxEvent; - friend class TxEvent; + void txEventTransmit() + { + transmit(); + if (txState == txFifoBlock) + txKick(); + } + typedef EventWrapper TxEvent; + friend void TxEvent::process(); TxEvent txEvent; void txDump() const; @@ -292,19 +340,19 @@ class NSGigE : public PciDev * receive address filter */ bool rxFilterEnable; - bool rxFilter(PacketPtr packet); + bool rxFilter(const PacketPtr &packet); bool acceptBroadcast; bool acceptMulticast; bool acceptUnicast; bool acceptPerfect; bool acceptArp; + bool multicastHashEnable; PhysicalMemory *physmem; /** * Interrupt management */ - IntrControl *intctrl; void devIntrPost(uint32_t interrupts); void devIntrClear(uint32_t interrupts); void devIntrChangeMask(); @@ -317,35 +365,48 @@ class NSGigE : public PciDev void cpuIntrClear(); typedef EventWrapper IntrEvent; - friend class IntrEvent; + friend void IntrEvent::process(); IntrEvent *intrEvent; - - /** - * Hardware checksum support - */ - bool udpChecksum(PacketPtr packet, bool gen); - bool tcpChecksum(PacketPtr packet, bool gen); - bool ipChecksum(PacketPtr packet, bool gen); - uint16_t checksumCalc(uint16_t *pseudo, uint16_t *buf, uint32_t len); - NSGigEInt *interface; public: - NSGigE(const std::string &name, IntrControl *i, Tick intr_delay, - PhysicalMemory *pmem, Tick tx_delay, Tick rx_delay, - MemoryController *mmu, HierParams *hier, Bus *header_bus, - Bus *payload_bus, Tick pio_latency, bool dma_desc_free, - bool dma_data_free, Tick dma_read_delay, Tick dma_write_delay, - Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf, - PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev, - uint32_t func, bool rx_filter, const int eaddr[6]); + struct Params : public PciDev::Params + { + PhysicalMemory *pmem; + HierParams *hier; + Bus *pio_bus; + Bus *header_bus; + Bus *payload_bus; + Tick clock; + Tick intr_delay; + Tick tx_delay; + Tick rx_delay; + Tick pio_latency; + bool pio_delay_write; + bool dma_desc_free; + bool dma_data_free; + Tick dma_read_delay; + Tick dma_write_delay; + Tick dma_read_factor; + Tick dma_write_factor; + bool rx_filter; + Net::EthAddr eaddr; + uint32_t tx_fifo_size; + uint32_t rx_fifo_size; + bool rx_thread; + bool tx_thread; + bool dma_no_allocate; + }; + + NSGigE(Params *params); ~NSGigE(); + const Params *params() const { return (const Params *)_params; } - virtual void WriteConfig(int offset, int size, uint32_t data); - virtual void ReadConfig(int offset, int size, uint8_t *data); + virtual void writeConfig(int offset, int size, const uint8_t *data); + virtual void readConfig(int offset, int size, uint8_t *data); - virtual Fault read(MemReqPtr &req, uint8_t *data); - virtual Fault write(MemReqPtr &req, const uint8_t *data); + virtual Fault * read(MemReqPtr &req, uint8_t *data); + virtual Fault * write(MemReqPtr &req, const uint8_t *data); bool cpuIntrPending() const; void cpuIntrAck() { cpuIntrClear(); } @@ -366,21 +427,51 @@ class NSGigE : public PciDev Stats::Scalar<> rxBytes; Stats::Scalar<> txPackets; Stats::Scalar<> rxPackets; - Stats::Scalar<> txIPChecksums; - Stats::Scalar<> rxIPChecksums; - Stats::Scalar<> txTCPChecksums; - Stats::Scalar<> rxTCPChecksums; + Stats::Scalar<> txIpChecksums; + Stats::Scalar<> rxIpChecksums; + Stats::Scalar<> txTcpChecksums; + Stats::Scalar<> rxTcpChecksums; + Stats::Scalar<> txUdpChecksums; + Stats::Scalar<> rxUdpChecksums; Stats::Scalar<> descDmaReads; Stats::Scalar<> descDmaWrites; Stats::Scalar<> descDmaRdBytes; Stats::Scalar<> descDmaWrBytes; + Stats::Formula totBandwidth; + Stats::Formula totPackets; + Stats::Formula totBytes; + Stats::Formula totPacketRate; Stats::Formula txBandwidth; Stats::Formula rxBandwidth; Stats::Formula txPacketRate; Stats::Formula rxPacketRate; - - private: - Tick pioLatency; + Stats::Scalar<> postedSwi; + Stats::Formula coalescedSwi; + Stats::Scalar<> totalSwi; + Stats::Scalar<> postedRxIdle; + Stats::Formula coalescedRxIdle; + Stats::Scalar<> totalRxIdle; + Stats::Scalar<> postedRxOk; + Stats::Formula coalescedRxOk; + Stats::Scalar<> totalRxOk; + Stats::Scalar<> postedRxDesc; + Stats::Formula coalescedRxDesc; + Stats::Scalar<> totalRxDesc; + Stats::Scalar<> postedTxOk; + Stats::Formula coalescedTxOk; + Stats::Scalar<> totalTxOk; + Stats::Scalar<> postedTxIdle; + Stats::Formula coalescedTxIdle; + Stats::Scalar<> totalTxIdle; + Stats::Scalar<> postedTxDesc; + Stats::Formula coalescedTxDesc; + Stats::Scalar<> totalTxDesc; + Stats::Scalar<> postedRxOrn; + Stats::Formula coalescedRxOrn; + Stats::Scalar<> totalRxOrn; + Stats::Formula coalescedTotal; + Stats::Scalar<> postedInterrupts; + Stats::Scalar<> droppedPackets; public: Tick cacheAccess(MemReqPtr &req); @@ -398,8 +489,8 @@ class NSGigEInt : public EtherInt NSGigEInt(const std::string &name, NSGigE *d) : EtherInt(name), dev(d) { dev->setInterface(this); } - virtual bool recvPacket(PacketPtr &pkt) { return dev->recvPacket(pkt); } + virtual bool recvPacket(PacketPtr pkt) { return dev->recvPacket(pkt); } virtual void sendDone() { dev->transferDone(); } }; -#endif // __NS_GIGE_HH__ +#endif // __DEV_NS_GIGE_HH__