X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=dev%2Fns_gige.hh;h=90711d63fc3e72e4b908d5d553187e1548a0ce0e;hb=e904ef37636ec7381cba003a3c9451a088a38190;hp=6405dc6342a55515b6ab1b46c63faa0d80dc6a57;hpb=0650e4a43f45b68aebc2e06c01bda1ac0e094e5e;p=gem5.git

diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh
index 6405dc634..90711d63f 100644
--- a/dev/ns_gige.hh
+++ b/dev/ns_gige.hh
@@ -31,27 +31,19 @@
  * DP83820 ethernet controller
  */
 
-#ifndef __NS_GIGE_HH__
-#define __NS_GIGE_HH__
+#ifndef __DEV_NS_GIGE_HH__
+#define __DEV_NS_GIGE_HH__
 
-//#include "base/range.hh"
+#include "base/inet.hh"
+#include "base/statistics.hh"
 #include "dev/etherint.hh"
 #include "dev/etherpkt.hh"
-#include "sim/eventq.hh"
+#include "dev/io_device.hh"
 #include "dev/ns_gige_reg.h"
-#include "base/statistics.hh"
 #include "dev/pcidev.hh"
-#include "dev/tsunami.hh"
-#include "dev/io_device.hh"
+#include "dev/pktfifo.hh"
 #include "mem/bus/bus.hh"
-
-/** defined by the NS83820 data sheet */
-//these are now params for the device
-//#define MAX_TX_FIFO_SIZE 8192
-//#define MAX_RX_FIFO_SIZE 32768
-
-/** length of ethernet address in bytes */
-#define EADDR_LEN 6
+#include "sim/eventq.hh"
 
 /**
  * Ethernet device registers
@@ -92,8 +84,11 @@ struct dp_regs {
 };
 
 struct dp_rom {
-    /** for perfect match memory.  the linux driver doesn't use any other ROM */
-    uint8_t perfectMatch[EADDR_LEN];
+    /**
+     * for perfect match memory.
+     * the linux driver doesn't use any other ROM
+     */
+    uint8_t perfectMatch[ETH_ADDR_LEN];
 };
 
 class IntrControl;
@@ -143,10 +138,6 @@ class NSGigE : public PciDev
         dmaWriteWaiting
     };
 
-  private:
-    /** pointer to the chipset */
-    Tsunami *tsunami;
-
   private:
     Addr addr;
     static const Addr size = sizeof(dp_regs);
@@ -168,10 +159,8 @@ class NSGigE : public PciDev
 
     /*** BASIC STRUCTURES FOR TX/RX ***/
     /* Data FIFOs */
-    pktbuf_t txFifo;
-    uint32_t maxTxFifoSize;
-    pktbuf_t rxFifo;
-    uint32_t maxRxFifoSize;
+    PacketFifo txFifo;
+    PacketFifo rxFifo;
 
     /** various helper vars */
     PacketPtr txPacket;
@@ -189,10 +178,10 @@ class NSGigE : public PciDev
 
     /* tx State Machine */
     TxState txState;
+    bool txEnable;
+
     /** Current Transmit Descriptor Done */
     bool CTDD;
-    /** current amt of free space in txDataFifo in bytes */
-    uint32_t txFifoAvail;
     /** halt the tx state machine after next packet */
     bool txHalt;
     /** ptr to the next byte in the current fragment */
@@ -203,12 +192,12 @@ class NSGigE : public PciDev
 
     /** rx State Machine */
     RxState rxState;
+    bool rxEnable;
+
     /** Current Receive Descriptor Done */
     bool CRDD;
     /** num of bytes in the current packet being drained from rxDataFifo */
     uint32_t rxPktBytes;
-    /** number of bytes in the rxFifo */
-    uint32_t rxFifoCnt;
     /** halt the rx state machine after current packet */
     bool rxHalt;
     /** ptr to the next byte in current fragment */
@@ -301,7 +290,7 @@ class NSGigE : public PciDev
      * receive address filter
      */
     bool rxFilterEnable;
-    bool rxFilter(PacketPtr packet);
+    bool rxFilter(const PacketPtr &packet);
     bool acceptBroadcast;
     bool acceptMulticast;
     bool acceptUnicast;
@@ -328,28 +317,34 @@ class NSGigE : public PciDev
     typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent;
     friend class IntrEvent;
     IntrEvent *intrEvent;
-
-    /**
-     * Hardware checksum support
-     */
-    bool udpChecksum(PacketPtr packet, bool gen);
-    bool tcpChecksum(PacketPtr packet, bool gen);
-    bool ipChecksum(PacketPtr packet, bool gen);
-    uint16_t checksumCalc(uint16_t *pseudo, uint16_t *buf, uint32_t len);
-
     NSGigEInt *interface;
 
   public:
-    NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
-           PhysicalMemory *pmem, Tick tx_delay, Tick rx_delay,
-           MemoryController *mmu, HierParams *hier, Bus *header_bus,
-           Bus *payload_bus, Tick pio_latency, bool dma_desc_free,
-           bool dma_data_free, Tick dma_read_delay, Tick dma_write_delay,
-           Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
-           PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
-           uint32_t func, bool rx_filter, const int eaddr[6],
-           uint32_t tx_fifo_size, uint32_t rx_fifo_size);
+    struct Params : public PciDev::Params
+    {
+        PhysicalMemory *pmem;
+        HierParams *hier;
+        Bus *header_bus;
+        Bus *payload_bus;
+        Tick intr_delay;
+        Tick tx_delay;
+        Tick rx_delay;
+        Tick pio_latency;
+        bool dma_desc_free;
+        bool dma_data_free;
+        Tick dma_read_delay;
+        Tick dma_write_delay;
+        Tick dma_read_factor;
+        Tick dma_write_factor;
+        bool rx_filter;
+        Net::EthAddr eaddr;
+        uint32_t tx_fifo_size;
+        uint32_t rx_fifo_size;
+    };
+
+    NSGigE(Params *params);
     ~NSGigE();
+    const Params *params() const { return (const Params *)_params; }
 
     virtual void WriteConfig(int offset, int size, uint32_t data);
     virtual void ReadConfig(int offset, int size, uint8_t *data);
@@ -376,10 +371,12 @@ class NSGigE : public PciDev
     Stats::Scalar<> rxBytes;
     Stats::Scalar<> txPackets;
     Stats::Scalar<> rxPackets;
-    Stats::Scalar<> txIPChecksums;
-    Stats::Scalar<> rxIPChecksums;
-    Stats::Scalar<> txTCPChecksums;
-    Stats::Scalar<> rxTCPChecksums;
+    Stats::Scalar<> txIpChecksums;
+    Stats::Scalar<> rxIpChecksums;
+    Stats::Scalar<> txTcpChecksums;
+    Stats::Scalar<> rxTcpChecksums;
+    Stats::Scalar<> txUdpChecksums;
+    Stats::Scalar<> rxUdpChecksums;
     Stats::Scalar<> descDmaReads;
     Stats::Scalar<> descDmaWrites;
     Stats::Scalar<> descDmaRdBytes;
@@ -405,8 +402,8 @@ class NSGigEInt : public EtherInt
     NSGigEInt(const std::string &name, NSGigE *d)
         : EtherInt(name), dev(d) { dev->setInterface(this); }
 
-    virtual bool recvPacket(PacketPtr &pkt) { return dev->recvPacket(pkt); }
+    virtual bool recvPacket(PacketPtr pkt) { return dev->recvPacket(pkt); }
     virtual void sendDone() { dev->transferDone(); }
 };
 
-#endif // __NS_GIGE_HH__
+#endif // __DEV_NS_GIGE_HH__