X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=dev%2Fns_gige.hh;h=90711d63fc3e72e4b908d5d553187e1548a0ce0e;hb=e904ef37636ec7381cba003a3c9451a088a38190;hp=cb65507205f9baba0d7fe3d90b87251f718e5eac;hpb=bf8de77465e3cbfcc9188c263080e9dc29a89f19;p=gem5.git diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh index cb6550720..90711d63f 100644 --- a/dev/ns_gige.hh +++ b/dev/ns_gige.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2003 The Regents of The University of Michigan + * Copyright (c) 2004 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -31,26 +31,19 @@ * DP83820 ethernet controller */ -#ifndef __NS_GIGE_HH__ -#define __NS_GIGE_HH__ +#ifndef __DEV_NS_GIGE_HH__ +#define __DEV_NS_GIGE_HH__ -//#include "base/range.hh" +#include "base/inet.hh" +#include "base/statistics.hh" #include "dev/etherint.hh" #include "dev/etherpkt.hh" -#include "sim/eventq.hh" +#include "dev/io_device.hh" #include "dev/ns_gige_reg.h" -#include "base/statistics.hh" #include "dev/pcidev.hh" -#include "dev/tsunami.hh" -#include "dev/io_device.hh" +#include "dev/pktfifo.hh" #include "mem/bus/bus.hh" - -/** defined by the NS83820 data sheet */ -#define MAX_TX_FIFO_SIZE 8192 -#define MAX_RX_FIFO_SIZE 32768 - -/** length of ethernet address in bytes */ -#define EADDR_LEN 6 +#include "sim/eventq.hh" /** * Ethernet device registers @@ -91,12 +84,15 @@ struct dp_regs { }; struct dp_rom { - /** for perfect match memory. the linux driver doesn't use any other ROM */ - uint8_t perfectMatch[EADDR_LEN]; + /** + * for perfect match memory. + * the linux driver doesn't use any other ROM + */ + uint8_t perfectMatch[ETH_ADDR_LEN]; }; class IntrControl; -class EtherDevInt; +class NSGigEInt; class PhysicalMemory; class BaseInterface; class HierParams; @@ -106,7 +102,7 @@ class PciConfigAll; /** * NS DP82830 Ethernet device model */ -class EtherDev : public PciDev +class NSGigE : public PciDev { public: /** Transmit State Machine states */ @@ -142,10 +138,6 @@ class EtherDev : public PciDev dmaWriteWaiting }; - private: - /** pointer to the chipset */ - Tsunami *tsunami; - private: Addr addr; static const Addr size = sizeof(dp_regs); @@ -158,21 +150,27 @@ class EtherDev : public PciDev dp_regs regs; dp_rom rom; - /*** BASIC STRUCTURES FOR TX/RX ***/ + /** pci settings */ + bool ioEnable; +#if 0 + bool memEnable; + bool bmEnable; +#endif + + /*** BASIC STRUCTURES FOR TX/RX ***/ /* Data FIFOs */ - pktbuf_t txFifo; - pktbuf_t rxFifo; + PacketFifo txFifo; + PacketFifo rxFifo; /** various helper vars */ + PacketPtr txPacket; + PacketPtr rxPacket; uint8_t *txPacketBufPtr; uint8_t *rxPacketBufPtr; uint32_t txXferLen; uint32_t rxXferLen; - uint32_t txPktXmitted; bool rxDmaFree; bool txDmaFree; - PacketPtr txPacket; - PacketPtr rxPacket; /** DescCaches */ ns_desc txDescCache; @@ -180,12 +178,10 @@ class EtherDev : public PciDev /* tx State Machine */ TxState txState; + bool txEnable; + /** Current Transmit Descriptor Done */ bool CTDD; - /** amt of data in the txDataFifo in bytes (logical) */ - uint32_t txFifoCnt; - /** current amt of free space in txDataFifo in bytes */ - uint32_t txFifoAvail; /** halt the tx state machine after next packet */ bool txHalt; /** ptr to the next byte in the current fragment */ @@ -196,12 +192,12 @@ class EtherDev : public PciDev /** rx State Machine */ RxState rxState; + bool rxEnable; + /** Current Receive Descriptor Done */ bool CRDD; /** num of bytes in the current packet being drained from rxDataFifo */ uint32_t rxPktBytes; - /** number of bytes in the rxFifo */ - uint32_t rxFifoCnt; /** halt the rx state machine after current packet */ bool rxHalt; /** ptr to the next byte in current fragment */ @@ -236,20 +232,20 @@ class EtherDev : public PciDev void txDmaWriteCopy(); void rxDmaReadDone(); - friend class EventWrapper; - EventWrapper rxDmaReadEvent; + friend class EventWrapper; + EventWrapper rxDmaReadEvent; void rxDmaWriteDone(); - friend class EventWrapper; - EventWrapper rxDmaWriteEvent; + friend class EventWrapper; + EventWrapper rxDmaWriteEvent; void txDmaReadDone(); - friend class EventWrapper; - EventWrapper txDmaReadEvent; + friend class EventWrapper; + EventWrapper txDmaReadEvent; void txDmaWriteDone(); - friend class EventWrapper; - EventWrapper txDmaWriteEvent; + friend class EventWrapper; + EventWrapper txDmaWriteEvent; bool dmaDescFree; bool dmaDataFree; @@ -261,34 +257,29 @@ class EtherDev : public PciDev void txReset(); void rxReset(); - void regsReset() { - memset(®s, 0, sizeof(regs)); - regs.config = 0x80000000; - regs.mear = 0x12; - regs.isr = 0x00608000; - regs.txcfg = 0x120; - regs.rxcfg = 0x4; - regs.srr = 0x0103; - regs.mibc = 0x2; - regs.vdr = 0x81; - regs.tesr = 0xc000; - } + void regsReset(); void rxKick(); Tick rxKickTick; - typedef EventWrapper RxKickEvent; + typedef EventWrapper RxKickEvent; friend class RxKickEvent; void txKick(); Tick txKickTick; - typedef EventWrapper TxKickEvent; + typedef EventWrapper TxKickEvent; friend class TxKickEvent; /** * Retransmit event */ void transmit(); - typedef EventWrapper TxEvent; + void txEventTransmit() + { + transmit(); + if (txState == txFifoBlock) + txKick(); + } + typedef EventWrapper TxEvent; friend class TxEvent; TxEvent txEvent; @@ -299,7 +290,7 @@ class EtherDev : public PciDev * receive address filter */ bool rxFilterEnable; - bool rxFilter(PacketPtr packet); + bool rxFilter(const PacketPtr &packet); bool acceptBroadcast; bool acceptMulticast; bool acceptUnicast; @@ -323,30 +314,37 @@ class EtherDev : public PciDev void cpuInterrupt(); void cpuIntrClear(); - typedef EventWrapper IntrEvent; + typedef EventWrapper IntrEvent; friend class IntrEvent; IntrEvent *intrEvent; - - /** - * Hardware checksum support - */ - bool udpChecksum(PacketPtr packet, bool gen); - bool tcpChecksum(PacketPtr packet, bool gen); - bool ipChecksum(PacketPtr packet, bool gen); - uint16_t checksumCalc(uint16_t *pseudo, uint16_t *buf, uint32_t len); - - EtherDevInt *interface; + NSGigEInt *interface; public: - EtherDev(const std::string &name, IntrControl *i, Tick intr_delay, - PhysicalMemory *pmem, Tick tx_delay, Tick rx_delay, - MemoryController *mmu, HierParams *hier, Bus *header_bus, - Bus *payload_bus, Tick pio_latency, bool dma_desc_free, - bool dma_data_free, Tick dma_read_delay, Tick dma_write_delay, - Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf, - PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev, - uint32_t func, bool rx_filter, const int eaddr[6], Addr addr); - ~EtherDev(); + struct Params : public PciDev::Params + { + PhysicalMemory *pmem; + HierParams *hier; + Bus *header_bus; + Bus *payload_bus; + Tick intr_delay; + Tick tx_delay; + Tick rx_delay; + Tick pio_latency; + bool dma_desc_free; + bool dma_data_free; + Tick dma_read_delay; + Tick dma_write_delay; + Tick dma_read_factor; + Tick dma_write_factor; + bool rx_filter; + Net::EthAddr eaddr; + uint32_t tx_fifo_size; + uint32_t rx_fifo_size; + }; + + NSGigE(Params *params); + ~NSGigE(); + const Params *params() const { return (const Params *)_params; } virtual void WriteConfig(int offset, int size, uint32_t data); virtual void ReadConfig(int offset, int size, uint8_t *data); @@ -360,7 +358,7 @@ class EtherDev : public PciDev bool recvPacket(PacketPtr packet); void transferDone(); - void setInterface(EtherDevInt *i) { assert(!interface); interface = i; } + void setInterface(NSGigEInt *i) { assert(!interface); interface = i; } virtual void serialize(std::ostream &os); virtual void unserialize(Checkpoint *cp, const std::string §ion); @@ -369,17 +367,24 @@ class EtherDev : public PciDev void regStats(); private: - Statistics::Scalar<> txBytes; - Statistics::Scalar<> rxBytes; - Statistics::Scalar<> txPackets; - Statistics::Scalar<> rxPackets; - Statistics::Formula txBandwidth; - Statistics::Formula rxBandwidth; - Statistics::Formula txPacketRate; - Statistics::Formula rxPacketRate; - - private: - Tick pioLatency; + Stats::Scalar<> txBytes; + Stats::Scalar<> rxBytes; + Stats::Scalar<> txPackets; + Stats::Scalar<> rxPackets; + Stats::Scalar<> txIpChecksums; + Stats::Scalar<> rxIpChecksums; + Stats::Scalar<> txTcpChecksums; + Stats::Scalar<> rxTcpChecksums; + Stats::Scalar<> txUdpChecksums; + Stats::Scalar<> rxUdpChecksums; + Stats::Scalar<> descDmaReads; + Stats::Scalar<> descDmaWrites; + Stats::Scalar<> descDmaRdBytes; + Stats::Scalar<> descDmaWrBytes; + Stats::Formula txBandwidth; + Stats::Formula rxBandwidth; + Stats::Formula txPacketRate; + Stats::Formula rxPacketRate; public: Tick cacheAccess(MemReqPtr &req); @@ -388,17 +393,17 @@ class EtherDev : public PciDev /* * Ethernet Interface for an Ethernet Device */ -class EtherDevInt : public EtherInt +class NSGigEInt : public EtherInt { private: - EtherDev *dev; + NSGigE *dev; public: - EtherDevInt(const std::string &name, EtherDev *d) + NSGigEInt(const std::string &name, NSGigE *d) : EtherInt(name), dev(d) { dev->setInterface(this); } - virtual bool recvPacket(PacketPtr &pkt) { return dev->recvPacket(pkt); } + virtual bool recvPacket(PacketPtr pkt) { return dev->recvPacket(pkt); } virtual void sendDone() { dev->transferDone(); } }; -#endif // __NS_GIGE_HH__ +#endif // __DEV_NS_GIGE_HH__