X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=dev%2Fns_gige_reg.h;h=eadc60d0331670bbc055123a837110e015b35eba;hb=466284b5d29ad0d44c1b020353cf7521be2b90de;hp=5b0f961c098b895275c8629f745f6d18d0ca2c2b;hpb=ddeaa4d5e158522f6106fa0afd1dcd52c1da1f21;p=gem5.git diff --git a/dev/ns_gige_reg.h b/dev/ns_gige_reg.h index 5b0f961c0..eadc60d03 100644 --- a/dev/ns_gige_reg.h +++ b/dev/ns_gige_reg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2003 The Regents of The University of Michigan + * Copyright (c) 2004-2005 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -26,67 +26,17 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* Portions of code taken from: */ - -/* ns83820.c by Benjamin LaHaise with contributions. - * - * Questions/comments/discussion to linux-ns83820@kvack.org. - * - * $Revision: 1.34.2.23 $ - * - * Copyright 2001 Benjamin LaHaise. - * Copyright 2001, 2002 Red Hat. - * - * Mmmm, chocolate vanilla mocha... - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - - - - - -/* @file +/** @file * Ethernet device register definitions for the National * Semiconductor DP83820 Ethernet controller */ -#ifndef _NS_GIGE_H -#define _NS_GIGE_H_ +#ifndef __DEV_NS_GIGE_REG_H__ +#define __DEV_NS_GIGE_REG_H__ -/* - * Configuration Register Map - */ -#define NS_ID 0x00 /* identification register */ -#define NS_CS 0x04 /* command and status register */ -#define NS_RID 0x08 /* revision ID register */ -#define NS_LAT 0x0C /* latency timer register */ -#define NS_IOA 0x10 /* IO base address register */ -#define NS_MA 0x14 /* memory address register */ -#define NS_MA1 0x18 /* memory address high dword register */ -#define NS_SID 0x2C /* subsystem identification register */ -#define NS_ROM 0x30 /* boot ROM configuration register */ -#define NS_CAPPTR 0x34 /* number of tx descriptors */ -#define NS_INT 0x3C /* interrupt select register */ -#define NS_PMCAP 0x40 /* power mgmt capabilities register */ -#define NS_PMCS 0x44 /* power mgmt control and status - register */ -/* Operational Register Map */ +/* Device Register Address Map */ #define CR 0x00 -#define CFG 0x04 +#define CFGR 0x04 #define MEAR 0x08 #define PTSCR 0x0c #define ISR 0x10 @@ -95,11 +45,11 @@ #define IHR 0x1c #define TXDP 0x20 #define TXDP_HI 0x24 -#define TXCFG 0x28 +#define TX_CFG 0x28 #define GPIOR 0x2c #define RXDP 0x30 #define RXDP_HI 0x34 -#define RXCFG 0x38 +#define RX_CFG 0x38 #define PQCR 0x3c #define WCSR 0x40 #define PCR 0x44 @@ -109,6 +59,8 @@ #define BRDR 0x54 #define SRR 0x58 #define MIBC 0x5c +#define MIB_START 0x60 +#define MIB_END 0x88 #define VRCR 0xbc #define VTCR 0xc0 #define VDR 0xc4 @@ -119,10 +71,11 @@ #define TANLPAR 0xec #define TANER 0xf0 #define TESR 0xf4 -#define LAST 0xf4 +#define M5REG 0xf8 +#define LAST 0xf8 #define RESERVED 0xfc -/* chip command register */ +/* Chip Command Register */ #define CR_TXE 0x00000001 #define CR_TXD 0x00000002 #define CR_RXE 0x00000004 @@ -133,37 +86,37 @@ #define CR_RST 0x00000100 /* configuration register */ -#define CFG_LNKSTS 0x80000000 -#define CFG_SPDSTS 0x60000000 -#define CFG_SPDSTS1 0x40000000 -#define CFG_SPDSTS0 0x20000000 -#define CFG_DUPSTS 0x10000000 -#define CFG_TBI_EN 0x01000000 -#define CFG_RESERVED 0x0e000000 -#define CFG_MODE_1000 0x00400000 -#define CFG_AUTO_1000 0x00200000 -#define CFG_PINT_CTL 0x001c0000 -#define CFG_PINT_DUPSTS 0x00100000 -#define CFG_PINT_LNKSTS 0x00080000 -#define CFG_PINT_SPDSTS 0x00040000 -#define CFG_TMRTEST 0x00020000 -#define CFG_MRM_DIS 0x00010000 -#define CFG_MWI_DIS 0x00008000 -#define CFG_T64ADDR 0x00004000 -#define CFG_PCI64_DET 0x00002000 -#define CFG_DATA64_EN 0x00001000 -#define CFG_M64ADDR 0x00000800 -#define CFG_PHY_RST 0x00000400 -#define CFG_PHY_DIS 0x00000200 -#define CFG_EXTSTS_EN 0x00000100 -#define CFG_REQALG 0x00000080 -#define CFG_SB 0x00000040 -#define CFG_POW 0x00000020 -#define CFG_EXD 0x00000010 -#define CFG_PESEL 0x00000008 -#define CFG_BROM_DIS 0x00000004 -#define CFG_EXT_125 0x00000002 -#define CFG_BEM 0x00000001 +#define CFGR_LNKSTS 0x80000000 +#define CFGR_SPDSTS 0x60000000 +#define CFGR_SPDSTS1 0x40000000 +#define CFGR_SPDSTS0 0x20000000 +#define CFGR_DUPSTS 0x10000000 +#define CFGR_TBI_EN 0x01000000 +#define CFGR_RESERVED 0x0e000000 +#define CFGR_MODE_1000 0x00400000 +#define CFGR_AUTO_1000 0x00200000 +#define CFGR_PINT_CTL 0x001c0000 +#define CFGR_PINT_DUPSTS 0x00100000 +#define CFGR_PINT_LNKSTS 0x00080000 +#define CFGR_PINT_SPDSTS 0x00040000 +#define CFGR_TMRTEST 0x00020000 +#define CFGR_MRM_DIS 0x00010000 +#define CFGR_MWI_DIS 0x00008000 +#define CFGR_T64ADDR 0x00004000 +#define CFGR_PCI64_DET 0x00002000 +#define CFGR_DATA64_EN 0x00001000 +#define CFGR_M64ADDR 0x00000800 +#define CFGR_PHY_RST 0x00000400 +#define CFGR_PHY_DIS 0x00000200 +#define CFGR_EXTSTS_EN 0x00000100 +#define CFGR_REQALG 0x00000080 +#define CFGR_SB 0x00000040 +#define CFGR_POW 0x00000020 +#define CFGR_EXD 0x00000010 +#define CFGR_PESEL 0x00000008 +#define CFGR_BROM_DIS 0x00000004 +#define CFGR_EXT_125 0x00000002 +#define CFGR_BEM 0x00000001 /* EEPROM access register */ #define MEAR_EEDI 0x00000001 @@ -182,6 +135,7 @@ #define PTSCR_RBIST_DONE 0x00000200 #define PTSCR_RBIST_EN 0x00000400 #define PTSCR_RBIST_RST 0x00002000 +#define PTSCR_RBIST_RDONLY 0x000003f9 /* interrupt status register */ #define ISR_RESERVE 0x80000000 @@ -216,45 +170,63 @@ #define ISR_RXERR 0x00000004 #define ISR_RXDESC 0x00000002 #define ISR_RXOK 0x00000001 +#define ISR_ALL 0x7FFFFFFF +#define ISR_DELAY (ISR_TXIDLE|ISR_TXDESC|ISR_TXOK| \ + ISR_RXIDLE|ISR_RXDESC|ISR_RXOK) +#define ISR_NODELAY (ISR_ALL & ~ISR_DELAY) +#define ISR_IMPL (ISR_SWI|ISR_TXIDLE|ISR_TXDESC|ISR_TXOK|ISR_RXORN| \ + ISR_RXIDLE|ISR_RXDESC|ISR_RXOK) +#define ISR_NOIMPL (ISR_ALL & ~ISR_IMPL) /* transmit configuration register */ -#define TXCFG_CSI 0x80000000 -#define TXCFG_HBI 0x40000000 -#define TXCFG_MLB 0x20000000 -#define TXCFG_ATP 0x10000000 -#define TXCFG_ECRETRY 0x00800000 -#define TXCFG_BRST_DIS 0x00080000 -#define TXCFG_MXDMA1024 0x00000000 -#define TXCFG_MXDMA512 0x00700000 -#define TXCFG_MXDMA256 0x00600000 -#define TXCFG_MXDMA128 0x00500000 -#define TXCFG_MXDMA64 0x00400000 -#define TXCFG_MXDMA32 0x00300000 -#define TXCFG_MXDMA16 0x00200000 -#define TXCFG_MXDMA8 0x00100000 - -#define TXCFG_FLTH_MASK 0x0000ff00 -#define TXCFG_DRTH_MASK 0x000000ff +#define TX_CFG_CSI 0x80000000 +#define TX_CFG_HBI 0x40000000 +#define TX_CFG_MLB 0x20000000 +#define TX_CFG_ATP 0x10000000 +#define TX_CFG_ECRETRY 0x00800000 +#define TX_CFG_BRST_DIS 0x00080000 +#define TX_CFG_MXDMA1024 0x00000000 +#define TX_CFG_MXDMA512 0x00700000 +#define TX_CFG_MXDMA256 0x00600000 +#define TX_CFG_MXDMA128 0x00500000 +#define TX_CFG_MXDMA64 0x00400000 +#define TX_CFG_MXDMA32 0x00300000 +#define TX_CFG_MXDMA16 0x00200000 +#define TX_CFG_MXDMA8 0x00100000 +#define TX_CFG_MXDMA 0x00700000 + +#define TX_CFG_FLTH_MASK 0x0000ff00 +#define TX_CFG_DRTH_MASK 0x000000ff /*general purpose I/O control register */ +#define GPIOR_UNUSED 0xffff8000 +#define GPIOR_GP5_IN 0x00004000 +#define GPIOR_GP4_IN 0x00002000 +#define GPIOR_GP3_IN 0x00001000 +#define GPIOR_GP2_IN 0x00000800 +#define GPIOR_GP1_IN 0x00000400 #define GPIOR_GP5_OE 0x00000200 #define GPIOR_GP4_OE 0x00000100 #define GPIOR_GP3_OE 0x00000080 #define GPIOR_GP2_OE 0x00000040 #define GPIOR_GP1_OE 0x00000020 +#define GPIOR_GP5_OUT 0x00000010 +#define GPIOR_GP4_OUT 0x00000008 #define GPIOR_GP3_OUT 0x00000004 +#define GPIOR_GP2_OUT 0x00000002 #define GPIOR_GP1_OUT 0x00000001 /* receive configuration register */ -#define RXCFG_AEP 0x80000000 -#define RXCFG_ARP 0x40000000 -#define RXCFG_STRIPCRC 0x20000000 -#define RXCFG_RX_FD 0x10000000 -#define RXCFG_ALP 0x08000000 -#define RXCFG_AIRL 0x04000000 -#define RXCFG_MXDMA512 0x00700000 -#define RXCFG_DRTH 0x0000003e -#define RXCFG_DRTH0 0x00000002 +#define RX_CFG_AEP 0x80000000 +#define RX_CFG_ARP 0x40000000 +#define RX_CFG_STRIPCRC 0x20000000 +#define RX_CFG_RX_FD 0x10000000 +#define RX_CFG_ALP 0x08000000 +#define RX_CFG_AIRL 0x04000000 +#define RX_CFG_MXDMA512 0x00700000 +#define RX_CFG_MXDMA 0x00700000 +#define RX_CFG_DRTH 0x0000003e +#define RX_CFG_DRTH0 0x00000002 /* pause control status register */ #define PCR_PSEN (1 << 31) @@ -323,27 +295,33 @@ #define TBISR_MR_AN_COMPLETE 0x00000004 /* TBI auto-negotiation advertisement register */ +#define TANAR_NP 0x00008000 +#define TANAR_RF2 0x00002000 +#define TANAR_RF1 0x00001000 #define TANAR_PS2 0x00000100 #define TANAR_PS1 0x00000080 -#define TANAR_HALF_DUP 0x00000040 -#define TANAR_FULL_DUP 0x00000020 - -/* - * descriptor format currently assuming link and bufptr - * are set for 32 bits,( may be wrong ) ASSUME32 - */ -struct ns_desc { - uint32_t link; /* link field to next descriptor in linked list */ - uint32_t bufptr; /* pointer to the first fragment or buffer */ - uint32_t cmdsts; /* command/status field */ - uint32_t extsts; /* extended status field for VLAN and IP info */ +#define TANAR_HALF_DUP 0x00000040 +#define TANAR_FULL_DUP 0x00000020 +#define TANAR_UNUSED 0x00000E1F + +/* M5 control register */ +#define M5REG_RESERVED 0xfffffffc +#define M5REG_RX_THREAD 0x00000002 +#define M5REG_TX_THREAD 0x00000001 + +struct ns_desc32 { + uint32_t link; /* link field to next descriptor in linked list */ + uint32_t bufptr; /* pointer to the first fragment or buffer */ + uint32_t cmdsts; /* command/status field */ + uint32_t extsts; /* extended status field for VLAN and IP info */ }; -/* ASSUME32 in bytes, how big the desc fields are */ -#define LINK_LEN 4 -#define BUFPTR_LEN 4 -#define CMDSTS_LEN 4 -#define EXTSTS_LEN 4 +struct ns_desc64 { + uint64_t link; /* link field to next descriptor in linked list */ + uint64_t bufptr; /* pointer to the first fragment or buffer */ + uint32_t cmdsts; /* command/status field */ + uint32_t extsts; /* extended status field for VLAN and IP info */ +}; /* cmdsts flags for descriptors */ #define CMDSTS_OWN 0x80000000 @@ -367,6 +345,6 @@ struct ns_desc { /* speed status */ -#define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0)) +#define SPDSTS_POLARITY (CFGR_SPDSTS1 | CFGR_SPDSTS0 | CFGR_DUPSTS | (lnksts ? CFGR_LNKSTS : 0)) -#endif /* _NS_GIGE_H_ */ +#endif /* __DEV_NS_GIGE_REG_H__ */