X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=dev%2Fpciconfigall.cc;h=1a138fb39345e5e63788ccf0a9c65e7441770277;hb=9e3d79694ca9e204bcbfa9c197db17b581dc7a29;hp=740a9b4acd7685070107806ed27c877d82f461d4;hpb=374e12c2de1d65bace95fb1db4bad122d7fff9ca;p=gem5.git diff --git a/dev/pciconfigall.cc b/dev/pciconfigall.cc index 740a9b4ac..1a138fb39 100644 --- a/dev/pciconfigall.cc +++ b/dev/pciconfigall.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2004 The Regents of The University of Michigan + * Copyright (c) 2004-2005 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -33,45 +33,78 @@ #include #include #include +#include +#include "arch/alpha/ev5.hh" #include "base/trace.hh" #include "dev/pciconfigall.hh" #include "dev/pcidev.hh" +#include "dev/pcireg.h" #include "mem/bus/bus.hh" #include "mem/bus/pio_interface.hh" #include "mem/bus/pio_interface_impl.hh" -#include "mem/functional_mem/memory_control.hh" +#include "mem/functional/memory_control.hh" #include "sim/builder.hh" #include "sim/system.hh" using namespace std; +using namespace TheISA; -PciConfigAll::PciConfigAll(const string &name, Addr a, MemoryController *mmu, - HierParams *hier, Bus *bus, Tick pio_latency) - : PioDevice(name), addr(a) +PciConfigAll::PciConfigAll(const string &name, + Addr a, MemoryController *mmu, + HierParams *hier, Bus *pio_bus, Tick pio_latency) + : PioDevice(name, NULL), addr(a) { - mmu->add_child(this, Range(addr, addr + size)); + mmu->add_child(this, RangeSize(addr, size)); - if (bus) { - pioInterface = newPioInterface(name, hier, bus, this, + if (pio_bus) { + pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this, &PciConfigAll::cacheAccess); - pioInterface->addAddrRange(addr, addr + size - 1); - pioLatency = pio_latency * bus->clockRatio; + pioInterface->addAddrRange(RangeSize(addr, size)); + pioLatency = pio_latency * pio_bus->clockRate; } // Make all the pointers to devices null for(int x=0; x < MAX_PCI_DEV; x++) for(int y=0; y < MAX_PCI_FUNC; y++) - devices[x][y] = NULL; + devices[x][y] = NULL; +} + +// If two interrupts share the same line largely bad things will happen. +// Since we don't track how many times an interrupt was set and correspondingly +// cleared two devices on the same interrupt line and assert and deassert each +// others interrupt "line". Interrupts will not work correctly. +void +PciConfigAll::startup() +{ + bitset<256> intLines; + PciDev *tempDev; + uint8_t intline; + + for (int x = 0; x < MAX_PCI_DEV; x++) { + for (int y = 0; y < MAX_PCI_FUNC; y++) { + if (devices[x][y] != NULL) { + tempDev = devices[x][y]; + intline = tempDev->interruptLine(); + if (intLines.test(intline)) + warn("Interrupt line %#X is used multiple times" + "(You probably want to fix this).\n", (uint32_t)intline); + else + intLines.set(intline); + } // devices != NULL + } // PCI_FUNC + } // PCI_DEV + } Fault PciConfigAll::read(MemReqPtr &req, uint8_t *data) { - DPRINTF(PciConfigAll, "read va=%#x size=%d\n", - req->vaddr, req->size); - Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)); + Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)); + + DPRINTF(PciConfigAll, "read va=%#x da=%#x size=%d\n", + req->vaddr, daddr, req->size); int device = (daddr >> 11) & 0x1F; int func = (daddr >> 8) & 0x7; @@ -81,16 +114,16 @@ PciConfigAll::read(MemReqPtr &req, uint8_t *data) switch (req->size) { // case sizeof(uint64_t): // *(uint64_t*)data = 0xFFFFFFFFFFFFFFFF; - // return No_Fault; + // return NoFault; case sizeof(uint32_t): *(uint32_t*)data = 0xFFFFFFFF; - return No_Fault; + return NoFault; case sizeof(uint16_t): *(uint16_t*)data = 0xFFFF; - return No_Fault; + return NoFault; case sizeof(uint8_t): *(uint8_t*)data = 0xFF; - return No_Fault; + return NoFault; default: panic("invalid access size(?) for PCI configspace!\n"); } @@ -99,8 +132,8 @@ PciConfigAll::read(MemReqPtr &req, uint8_t *data) case sizeof(uint32_t): case sizeof(uint16_t): case sizeof(uint8_t): - devices[device][func]->ReadConfig(reg, req->size, data); - return No_Fault; + devices[device][func]->readConfig(reg, req->size, data); + return NoFault; default: panic("invalid access size(?) for PCI configspace!\n"); } @@ -109,48 +142,31 @@ PciConfigAll::read(MemReqPtr &req, uint8_t *data) DPRINTFN("PCI Configspace ERROR: read daddr=%#x size=%d\n", daddr, req->size); - return No_Fault; + return NoFault; } Fault PciConfigAll::write(MemReqPtr &req, const uint8_t *data) { - Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)); + Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)); int device = (daddr >> 11) & 0x1F; int func = (daddr >> 8) & 0x7; int reg = daddr & 0xFF; - union { - uint8_t byte_value; - uint16_t half_value; - uint32_t word_value; - }; - if (devices[device][func] == NULL) panic("Attempting to write to config space on non-existant device\n"); - else { - switch (req->size) { - case sizeof(uint8_t): - byte_value = *(uint8_t*)data; - break; - case sizeof(uint16_t): - half_value = *(uint16_t*)data; - break; - case sizeof(uint32_t): - word_value = *(uint32_t*)data; - break; - default: - panic("invalid access size(?) for PCI configspace!\n"); - } - } + else if (req->size != sizeof(uint8_t) && + req->size != sizeof(uint16_t) && + req->size != sizeof(uint32_t)) + panic("invalid access size(?) for PCI configspace!\n"); DPRINTF(PciConfigAll, "write - va=%#x size=%d data=%#x\n", - req->vaddr, req->size, word_value); + req->vaddr, req->size, *(uint32_t*)data); - devices[device][func]->WriteConfig(reg, req->size, word_value); + devices[device][func]->writeConfig(reg, req->size, data); - return No_Fault; + return NoFault; } void @@ -186,7 +202,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll) SimObjectParam mmu; Param addr; Param mask; - SimObjectParam io_bus; + SimObjectParam pio_bus; Param pio_latency; SimObjectParam hier; @@ -197,7 +213,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll) INIT_PARAM(mmu, "Memory Controller"), INIT_PARAM(addr, "Device Address"), INIT_PARAM(mask, "Address Mask"), - INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL), + INIT_PARAM_DFLT(pio_bus, "The IO Bus to attach to", NULL), INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1), INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams) @@ -205,7 +221,7 @@ END_INIT_SIM_OBJECT_PARAMS(PciConfigAll) CREATE_SIM_OBJECT(PciConfigAll) { - return new PciConfigAll(getInstanceName(), addr, mmu, hier, io_bus, + return new PciConfigAll(getInstanceName(), addr, mmu, hier, pio_bus, pio_latency); }