X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=dev%2Fpciconfigall.cc;h=740a9b4acd7685070107806ed27c877d82f461d4;hb=f1f85c5470c67adc5071296c53e69abb0b47b09c;hp=4467ce1e51325aa7ae5183f1d01246c1cd7b15d2;hpb=3bc8cffc75c2e03a6a8fe5f4425940a16405f672;p=gem5.git

diff --git a/dev/pciconfigall.cc b/dev/pciconfigall.cc
index 4467ce1e5..740a9b4ac 100644
--- a/dev/pciconfigall.cc
+++ b/dev/pciconfigall.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2004 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -35,26 +35,29 @@
 #include <vector>
 
 #include "base/trace.hh"
-#include "cpu/exec_context.hh"
-#include "dev/scsi_ctrl.hh"
 #include "dev/pciconfigall.hh"
 #include "dev/pcidev.hh"
-#include "dev/tsunamireg.h"
-#include "dev/tsunami.hh"
+#include "mem/bus/bus.hh"
+#include "mem/bus/pio_interface.hh"
+#include "mem/bus/pio_interface_impl.hh"
 #include "mem/functional_mem/memory_control.hh"
 #include "sim/builder.hh"
 #include "sim/system.hh"
 
 using namespace std;
 
-PciConfigAll::PciConfigAll(const string &name, Tsunami *t, Addr a,
-                           MemoryController *mmu)
-    : FunctionalMemory(name), addr(a), tsunami(t)
+PciConfigAll::PciConfigAll(const string &name, Addr a, MemoryController *mmu,
+                           HierParams *hier, Bus *bus, Tick pio_latency)
+    : PioDevice(name), addr(a)
 {
     mmu->add_child(this, Range<Addr>(addr, addr + size));
 
-    // Put back pointer in tsunami
-    tsunami->pciconfig = this;
+    if (bus) {
+        pioInterface = newPioInterface(name, hier, bus, this,
+                                      &PciConfigAll::cacheAccess);
+        pioInterface->addAddrRange(addr, addr + size - 1);
+        pioLatency = pio_latency * bus->clockRatio;
+    }
 
     // Make all the pointers to devices null
     for(int x=0; x < MAX_PCI_DEV; x++)
@@ -103,7 +106,7 @@ PciConfigAll::read(MemReqPtr &req, uint8_t *data)
         }
     }
 
-    DPRINTFN("Tsunami PCI Configspace  ERROR: read  daddr=%#x size=%d\n",
+    DPRINTFN("PCI Configspace  ERROR: read  daddr=%#x size=%d\n",
              daddr, req->size);
 
     return No_Fault;
@@ -153,38 +156,57 @@ PciConfigAll::write(MemReqPtr &req, const uint8_t *data)
 void
 PciConfigAll::serialize(std::ostream &os)
 {
-    // code should be written
+    /*
+     * There is no state associated with this object that requires
+     * serialization.  The only real state are the device pointers
+     * which are all setup by the constructor of the PciDev class
+     */
 }
 
 void
 PciConfigAll::unserialize(Checkpoint *cp, const std::string &section)
 {
-    //code should be written
+    /*
+     * There is no state associated with this object that requires
+     * serialization.  The only real state are the device pointers
+     * which are all setup by the constructor of the PciDev class
+     */
+}
+
+Tick
+PciConfigAll::cacheAccess(MemReqPtr &req)
+{
+    return curTick + pioLatency;
 }
 
 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 
 BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
 
-    SimObjectParam<Tsunami *> tsunami;
     SimObjectParam<MemoryController *> mmu;
     Param<Addr> addr;
     Param<Addr> mask;
+    SimObjectParam<Bus*> io_bus;
+    Param<Tick> pio_latency;
+    SimObjectParam<HierParams *> hier;
 
 END_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
 
 BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
 
-    INIT_PARAM(tsunami, "Tsunami"),
     INIT_PARAM(mmu, "Memory Controller"),
     INIT_PARAM(addr, "Device Address"),
-    INIT_PARAM(mask, "Address Mask")
+    INIT_PARAM(mask, "Address Mask"),
+    INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
+    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
+    INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
 
 END_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
 
 CREATE_SIM_OBJECT(PciConfigAll)
 {
-    return new PciConfigAll(getInstanceName(), tsunami, addr, mmu);
+    return new PciConfigAll(getInstanceName(), addr, mmu, hier, io_bus,
+                            pio_latency);
 }
 
 REGISTER_SIM_OBJECT("PciConfigAll", PciConfigAll)