X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=dev%2Fpciconfigall.hh;h=6df03328615277d1ef6838f0e07f6980f49d1d9e;hb=466284b5d29ad0d44c1b020353cf7521be2b90de;hp=070643fd90fbb2f3b0ed93f67ad642055e4073d9;hpb=eac2d6a66863dcd7d5129ee5112ea49248f9efa8;p=gem5.git

diff --git a/dev/pciconfigall.hh b/dev/pciconfigall.hh
index 070643fd9..6df033286 100644
--- a/dev/pciconfigall.hh
+++ b/dev/pciconfigall.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -27,10 +27,6 @@
  */
 
 /*
- * @todo
- * Should derive Tsunami from common platform class so PCI will work with
- * multiple platforms
- *
  * @file
  * PCI Config space implementation.
  */
@@ -38,14 +34,16 @@
 #ifndef __PCICONFIGALL_HH__
 #define __PCICONFIGALL_HH__
 
-#include "mem/functional_mem/mmap_device.hh"
-#include "dev/tsunami.hh"
 #include "dev/pcireg.h"
+#include "base/range.hh"
+#include "dev/io_device.hh"
+
 
-#define MAX_PCI_DEV     32
-#define MAX_PCI_FUNC    8
+static const uint32_t MAX_PCI_DEV = 32;
+static const uint32_t MAX_PCI_FUNC = 8;
 
 class PciDev;
+class MemoryController;
 
 /**
  * PCI Config Space
@@ -54,38 +52,96 @@ class PciDev;
  * space and passes the requests on to TsunamiPCIDev devices as
  * appropriate.
  */
-class PCIConfigAll : public MmapDevice
+class PciConfigAll : public PioDevice
 {
   private:
+    Addr addr;
+    static const Addr size = 0xffffff;
 
-  protected:
-
-    /**
-      * Pointer to the Tsunmi Object so we can communicate
-      * to other Tsunami devices in need be.
-      * @todo Make this more generic for multiple platforms
-      */
-    Tsunami *tsunami;
-
-  public:
     /**
       * Pointers to all the devices that are registered with this
       * particular config space.
       */
     PciDev* devices[MAX_PCI_DEV][MAX_PCI_FUNC];
 
+  public:
     /**
-      * The default constructor.
-      */
-    PCIConfigAll(const std::string &name, Tsunami *t,
-                 Addr addr, Addr mask, MemoryController *mmu);
+     * Constructor for PCIConfigAll
+     * @param name name of the object
+     * @param a base address of the write
+     * @param mmu the memory controller
+     * @param hier object to store parameters universal the device hierarchy
+     * @param bus The bus that this device is attached to
+     */
+    PciConfigAll(const std::string &name, Addr a, MemoryController *mmu,
+                 HierParams *hier, Bus *pio_bus, Tick pio_latency);
+
 
-    virtual Fault read(MemReqPtr &req, uint8_t *data);
-    virtual Fault write(MemReqPtr &req, const uint8_t *data);
+    /**
+     * Check if a device exists.
+     * @param pcidev PCI device to check
+     * @param pcifunc PCI function to check
+     * @return true if device exists, false otherwise
+     */
+    bool deviceExists(uint32_t pcidev, uint32_t pcifunc)
+                     { return devices[pcidev][pcifunc] != NULL ? true : false; }
+
+    /**
+     * Registers a device with the config space object.
+     * @param pcidev PCI device to register
+     * @param pcifunc PCI function to register
+     * @param device device to register
+     */
+    void registerDevice(uint8_t pcidev, uint8_t pcifunc, PciDev *device)
+                        { devices[pcidev][pcifunc] = device; }
 
+    /**
+     * Read something in PCI config space. If the device does not exist
+     * -1 is returned, if the device does exist its PciDev::ReadConfig (or the
+     * virtual function that overrides) it is called.
+     * @param req Contains the address of the field to read.
+     * @param data Return the field read.
+     * @return The fault condition of the access.
+     */
+    virtual Fault * read(MemReqPtr &req, uint8_t *data);
+
+    /**
+     * Write to PCI config spcae. If the device does not exit the simulator
+     * panics. If it does it is passed on the PciDev::WriteConfig (or the virtual
+     * function that overrides it).
+     * @param req Contains the address to write to.
+     * @param data The data to write.
+     * @return The fault condition of the access.
+     */
+
+    virtual Fault * write(MemReqPtr &req, const uint8_t *data);
+
+    /**
+     * Start up function to check if more than one person is using an interrupt line
+     * and print a warning if such a case exists
+     */
+    virtual void startup();
+
+    /**
+     * Serialize this object to the given output stream.
+     * @param os The stream to serialize to.
+     */
     virtual void serialize(std::ostream &os);
+
+    /**
+     * Reconstruct the state of this object from a checkpoint.
+     * @param cp The checkpoint use.
+     * @param section The section name of this object
+     */
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 
+    /**
+     * Return how long this access will take.
+     * @param req the memory request to calcuate
+     * @return Tick when the request is done
+     */
+    Tick cacheAccess(MemReqPtr &req);
+
 };
 
 #endif // __PCICONFIGALL_HH__