X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=dev%2Fpcidev.cc;h=7b13aac8057e000d0e18833150339a6da6fffb33;hb=19fd3439c738e06be8c43078f520054011a385cc;hp=342561750d8816e71ec70619e84eee5c3d9cc38c;hpb=22f78a6d03fbc390eca538b906aedea9121ab9bb;p=gem5.git diff --git a/dev/pcidev.cc b/dev/pcidev.cc index 342561750..7b13aac80 100644 --- a/dev/pcidev.cc +++ b/dev/pcidev.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2003 The Regents of The University of Michigan + * Copyright (c) 2004 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -40,7 +40,6 @@ #include "base/str.hh" // for to_number #include "base/trace.hh" #include "dev/pciareg.h" -#include "dev/scsi_ctrl.hh" #include "dev/pcidev.hh" #include "dev/pciconfigall.hh" #include "mem/functional_mem/memory_control.hh" @@ -51,10 +50,10 @@ using namespace std; -PciDev::PciDev(const string &name, MemoryController *mmu, PCIConfigAll *cf, +PciDev::PciDev(const string &name, MemoryController *mmu, PciConfigAll *cf, PciConfigData *cd, uint32_t bus, uint32_t dev, uint32_t func) - : MmapDevice(name), MMU(mmu), ConfigSpace(cf), ConfigData(cd), - Bus(bus), Device(dev), Function(func) + : DmaDevice(name), mmu(mmu), configSpace(cf), configData(cd), busNum(bus), + deviceNum(dev), functionNum(func) { // copy the config data from the PciConfigData object if (cd) { @@ -65,10 +64,10 @@ PciDev::PciDev(const string &name, MemoryController *mmu, PCIConfigAll *cf, panic("NULL pointer to configuration data"); // Setup pointer in config space to point to this entry - if (cf->devices[dev][func] != NULL) + if (cf->deviceExists(dev,func)) panic("Two PCI devices occuping same dev: %#x func: %#x", dev, func); else - cf->devices[dev][func] = this; + cf->registerDevice(dev, func, this); } void @@ -76,25 +75,29 @@ PciDev::ReadConfig(int offset, int size, uint8_t *data) { switch(size) { case sizeof(uint32_t): - memcpy((uint32_t*)data, config.data + offset, sizeof(uint32_t)); + memcpy((uint8_t*)data, config.data + offset, sizeof(uint32_t)); + *(uint32_t*)data = htoa(*(uint32_t*)data); DPRINTF(PCIDEV, - "read device: %#x function: %#x register: %#x data: %#x\n", - Device, Function, offset, *(uint32_t*)(config.data + offset)); + "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n", + deviceNum, functionNum, offset, size, + *(uint32_t*)(config.data + offset)); break; case sizeof(uint16_t): - memcpy((uint16_t*)data, config.data + offset, sizeof(uint16_t)); + memcpy((uint8_t*)data, config.data + offset, sizeof(uint16_t)); + *(uint16_t*)data = htoa(*(uint16_t*)data); DPRINTF(PCIDEV, - "read device: %#x function: %#x register: %#x data: %#x\n", - Device, Function, offset, *(uint16_t*)(config.data + offset)); + "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n", + deviceNum, functionNum, offset, size, + *(uint16_t*)(config.data + offset)); break; case sizeof(uint8_t): memcpy((uint8_t*)data, config.data + offset, sizeof(uint8_t)); - printf("data: %#x\n", *(uint8_t*)(config.data + offset)); DPRINTF(PCIDEV, - "read device: %#x function: %#x register: %#x data: %#x\n", - Device, Function, offset, *(uint8_t*)(config.data + offset)); + "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n", + deviceNum, functionNum, offset, size, + (uint16_t)(*(uint8_t*)(config.data + offset))); break; default: @@ -115,8 +118,8 @@ PciDev::WriteConfig(int offset, int size, uint32_t data) word_value = data; DPRINTF(PCIDEV, - "write device: %#x function: %#x reg: %#x size: %#x data: %#x\n", - Device, Function, offset, size, word_value); + "write device: %#x function: %#x reg: %#x size: %d data: %#x\n", + deviceNum, functionNum, offset, size, word_value); barnum = (offset - PCI0_BASE_ADDR0) >> 2; @@ -125,6 +128,7 @@ PciDev::WriteConfig(int offset, int size, uint32_t data) switch (offset) { case PCI0_INTERRUPT_LINE: case PCI_CACHE_LINE_SIZE: + case PCI_LATENCY_TIMER: *(uint8_t *)&config.data[offset] = byte_value; break; @@ -179,15 +183,24 @@ PciDev::WriteConfig(int offset, int size, uint32_t data) (config.data[offset] & 0x3); if (word_value & ~0x1) { + Addr base_addr = (word_value & ~0x1) + TSUNAMI_PCI0_IO; + Addr base_size = BARSize[barnum]-1; + // It's never been set if (BARAddrs[barnum] == 0) - AddMapping((word_value & ~0x1) + TSUNAMI_PCI0_IO, - BARSize[barnum]-1, MMU); + mmu->add_child((FunctionalMemory *)this, + Range(base_addr, + base_addr + base_size)); else - ChangeMapping(BARAddrs[barnum], BARSize[barnum]-1, - (word_value & ~0x1) + TSUNAMI_PCI0_IO, - BARSize[barnum]-1, MMU); - BARAddrs[barnum] = (word_value & ~0x1) + TSUNAMI_PCI0_IO; + mmu->update_child((FunctionalMemory *)this, + Range(BARAddrs[barnum], + BARAddrs[barnum] + + base_size), + Range(base_addr, + base_addr + + base_size)); + + BARAddrs[barnum] = base_addr; } } else { @@ -196,17 +209,26 @@ PciDev::WriteConfig(int offset, int size, uint32_t data) (config.data[offset] & 0xF); if (word_value & ~0x3) { + Addr base_addr = (word_value & ~0x3) + + TSUNAMI_PCI0_MEMORY; + + Addr base_size = BARSize[barnum]-1; + // It's never been set if (BARAddrs[barnum] == 0) - AddMapping((word_value & ~0x3) + TSUNAMI_PCI0_MEMORY, - BARSize[barnum]-1, MMU); + mmu->add_child((FunctionalMemory *)this, + Range(base_addr, + base_addr + base_size)); else - ChangeMapping(BARAddrs[barnum], BARSize[barnum]-1, - (word_value & ~0x3) + - TSUNAMI_PCI0_MEMORY, - BARSize[barnum]-1, MMU); - BARAddrs[barnum] = (word_value & ~0x3) + - TSUNAMI_PCI0_MEMORY; + mmu->update_child((FunctionalMemory *)this, + Range(BARAddrs[barnum], + BARAddrs[barnum] + + base_size), + Range(base_addr, + base_addr + + base_size)); + + BARAddrs[barnum] = base_addr; } } } @@ -227,7 +249,7 @@ PciDev::WriteConfig(int offset, int size, uint32_t data) break; default: - panic("writing to a read only register"); + DPRINTF(PCIDEV, "Writing to a read only register"); } break; } @@ -236,31 +258,44 @@ PciDev::WriteConfig(int offset, int size, uint32_t data) void PciDev::serialize(ostream &os) { + SERIALIZE_ARRAY(BARSize, 6); + SERIALIZE_ARRAY(BARAddrs, 6); SERIALIZE_ARRAY(config.data, 64); } void PciDev::unserialize(Checkpoint *cp, const std::string §ion) { + UNSERIALIZE_ARRAY(BARSize, 6); + UNSERIALIZE_ARRAY(BARAddrs, 6); UNSERIALIZE_ARRAY(config.data, 64); + + // Add the MMU mappings for the BARs + for (int i=0; i < 6; i++) { + if (BARAddrs[i] != 0) + mmu->add_child((FunctionalMemory *)this, + Range(BARAddrs[i], + BARAddrs[i] + + BARSize[i] - 1)); + } } #ifndef DOXYGEN_SHOULD_SKIP_THIS BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData) - Param VendorID; - Param DeviceID; - Param Command; - Param Status; - Param Revision; - Param ProgIF; - Param SubClassCode; - Param ClassCode; - Param CacheLineSize; - Param LatencyTimer; - Param HeaderType; - Param BIST; + Param VendorID; + Param DeviceID; + Param Command; + Param Status; + Param Revision; + Param ProgIF; + Param SubClassCode; + Param ClassCode; + Param CacheLineSize; + Param LatencyTimer; + Param HeaderType; + Param BIST; Param BAR0; Param BAR1; Param BAR2; @@ -268,13 +303,13 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData) Param BAR4; Param BAR5; Param CardbusCIS; - Param SubsystemVendorID; - Param SubsystemID; + Param SubsystemVendorID; + Param SubsystemID; Param ExpansionROM; - Param InterruptLine; - Param InterruptPin; - Param MinimumGrant; - Param MaximumLatency; + Param InterruptLine; + Param InterruptPin; + Param MinimumGrant; + Param MaximumLatency; Param BAR0Size; Param BAR1Size; Param BAR2Size; @@ -325,33 +360,33 @@ CREATE_SIM_OBJECT(PciConfigData) { PciConfigData *data = new PciConfigData(getInstanceName()); - data->config.hdr.vendor = VendorID; - data->config.hdr.device = DeviceID; - data->config.hdr.command = Command; - data->config.hdr.status = Status; - data->config.hdr.revision = Revision; - data->config.hdr.progIF = ProgIF; - data->config.hdr.subClassCode = SubClassCode; - data->config.hdr.classCode = ClassCode; - data->config.hdr.cacheLineSize = CacheLineSize; - data->config.hdr.latencyTimer = LatencyTimer; - data->config.hdr.headerType = HeaderType; - data->config.hdr.bist = BIST; - - data->config.hdr.pci0.baseAddr0 = BAR0; - data->config.hdr.pci0.baseAddr1 = BAR1; - data->config.hdr.pci0.baseAddr2 = BAR2; - data->config.hdr.pci0.baseAddr3 = BAR3; - data->config.hdr.pci0.baseAddr4 = BAR4; - data->config.hdr.pci0.baseAddr5 = BAR5; - data->config.hdr.pci0.cardbusCIS = CardbusCIS; - data->config.hdr.pci0.subsystemVendorID = SubsystemVendorID; - data->config.hdr.pci0.subsystemID = SubsystemVendorID; - data->config.hdr.pci0.expansionROM = ExpansionROM; - data->config.hdr.pci0.interruptLine = InterruptLine; - data->config.hdr.pci0.interruptPin = InterruptPin; - data->config.hdr.pci0.minimumGrant = MinimumGrant; - data->config.hdr.pci0.maximumLatency = MaximumLatency; + data->config.hdr.vendor = htoa(VendorID); + data->config.hdr.device = htoa(DeviceID); + data->config.hdr.command = htoa(Command); + data->config.hdr.status = htoa(Status); + data->config.hdr.revision = htoa(Revision); + data->config.hdr.progIF = htoa(ProgIF); + data->config.hdr.subClassCode = htoa(SubClassCode); + data->config.hdr.classCode = htoa(ClassCode); + data->config.hdr.cacheLineSize = htoa(CacheLineSize); + data->config.hdr.latencyTimer = htoa(LatencyTimer); + data->config.hdr.headerType = htoa(HeaderType); + data->config.hdr.bist = htoa(BIST); + + data->config.hdr.pci0.baseAddr0 = htoa(BAR0); + data->config.hdr.pci0.baseAddr1 = htoa(BAR1); + data->config.hdr.pci0.baseAddr2 = htoa(BAR2); + data->config.hdr.pci0.baseAddr3 = htoa(BAR3); + data->config.hdr.pci0.baseAddr4 = htoa(BAR4); + data->config.hdr.pci0.baseAddr5 = htoa(BAR5); + data->config.hdr.pci0.cardbusCIS = htoa(CardbusCIS); + data->config.hdr.pci0.subsystemVendorID = htoa(SubsystemVendorID); + data->config.hdr.pci0.subsystemID = htoa(SubsystemVendorID); + data->config.hdr.pci0.expansionROM = htoa(ExpansionROM); + data->config.hdr.pci0.interruptLine = htoa(InterruptLine); + data->config.hdr.pci0.interruptPin = htoa(InterruptPin); + data->config.hdr.pci0.minimumGrant = htoa(MinimumGrant); + data->config.hdr.pci0.maximumLatency = htoa(MaximumLatency); data->BARSize[0] = BAR0Size; data->BARSize[1] = BAR1Size;