X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=dev%2Fpcidev.cc;h=9d568e6cce2f83634f9dd1f4ad2bc3566bccbe7e;hb=715176d450fe2c85d3a72d80cd5c2460f8c552cd;hp=fcd011123585d1c948ccc80239a58f49868cba64;hpb=69e1e10f5d940ee06d2c38f3a1b21c9992587f13;p=gem5.git

diff --git a/dev/pcidev.cc b/dev/pcidev.cc
index fcd011123..9d568e6cc 100644
--- a/dev/pcidev.cc
+++ b/dev/pcidev.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2004 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -39,61 +39,81 @@
 #include "base/misc.hh"
 #include "base/str.hh"	// for to_number
 #include "base/trace.hh"
-#include "dev/pciareg.h"
-#include "dev/scsi_ctrl.hh"
 #include "dev/pcidev.hh"
 #include "dev/pciconfigall.hh"
-#include "mem/functional_mem/memory_control.hh"
+#include "mem/bus/bus.hh"
+#include "mem/functional/memory_control.hh"
 #include "sim/builder.hh"
 #include "sim/param.hh"
-#include "sim/universe.hh"
+#include "sim/root.hh"
+#include "dev/tsunamireg.h"
 
 using namespace std;
 
-PciDev::PciDev(const string &name, PCIConfigAll *cf, uint32_t bus,
-               uint32_t dev, uint32_t func)
-    : MMapDevice(name), ConfigSpace(cf), Bus(bus), Device(dev), Function(func), MMU(mmu)
+PciDev::PciDev(Params *p)
+    : DmaDevice(p->name, p->plat), _params(p), plat(p->plat),
+      configData(p->configData)
 {
-    memset(config.data, 0, sizeof(config.data));
-    memset(BARAddrs, 0, sizeof(Addr) * 6);
+    // copy the config data from the PciConfigData object
+    if (configData) {
+        memcpy(config.data, configData->config.data, sizeof(config.data));
+        memcpy(BARSize, configData->BARSize, sizeof(BARSize));
+        memcpy(BARAddrs, configData->BARAddrs, sizeof(BARAddrs));
+    } else
+        panic("NULL pointer to configuration data");
 
     // Setup pointer in config space to point to this entry
-    if(cf->devices[dev][func] != NULL)
-        panic("Two PCI devices occuping same dev: %#x func: %#x", dev, func);
+    if (p->configSpace->deviceExists(p->deviceNum, p->functionNum))
+        panic("Two PCI devices occuping same dev: %#x func: %#x",
+              p->deviceNum, p->functionNum);
     else
-        cf->devices[dev][func] = this;
+        p->configSpace->registerDevice(p->deviceNum, p->functionNum, this);
 }
 
-
 void
 PciDev::ReadConfig(int offset, int size, uint8_t *data)
 {
+    if (offset >= PCI_DEVICE_SPECIFIC)
+        panic("Device specific PCI config space not implemented!\n");
+
     switch(size) {
-        case sizeof(uint32_t):
-            memcpy((uint32_t*)data, config.data + offset, sizeof(uint32_t));
-            DPRINTF(PCIDEV, "read device: %#x function: %#x register: %#x data: %#x\n",
-                Device, Function, offset, *(uint32_t*)(config.data + offset));
-            break;
-        case sizeof(uint16_t):
-            memcpy((uint16_t*)data, config.data + offset, sizeof(uint16_t));
-            DPRINTF(PCIDEV, "read device: %#x function: %#x register: %#x data: %#x\n",
-                Device, Function, offset, *(uint16_t*)(config.data + offset));
-            break;
-        case sizeof(uint8_t):
-            memcpy((uint8_t*)data, config.data + offset, sizeof(uint8_t));
-            printf("data: %#x\n", *(uint8_t*)(config.data + offset));
-            DPRINTF(PCIDEV, "read device: %#x function: %#x register: %#x data: %#x\n",
-                Device, Function, offset, *(uint8_t*)(config.data + offset));
-            break;
-        default:
-            panic("Invalid Read Size");
+      case sizeof(uint32_t):
+        memcpy((uint8_t*)data, config.data + offset, sizeof(uint32_t));
+        *(uint32_t*)data = htoa(*(uint32_t*)data);
+        DPRINTF(PCIDEV,
+                "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
+                params()->deviceNum, params()->functionNum, offset, size,
+                *(uint32_t*)(config.data + offset));
+        break;
+
+      case sizeof(uint16_t):
+        memcpy((uint8_t*)data, config.data + offset, sizeof(uint16_t));
+        *(uint16_t*)data = htoa(*(uint16_t*)data);
+        DPRINTF(PCIDEV,
+                "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
+                params()->deviceNum, params()->functionNum, offset, size,
+                *(uint16_t*)(config.data + offset));
+        break;
+
+      case sizeof(uint8_t):
+        memcpy((uint8_t*)data, config.data + offset, sizeof(uint8_t));
+        DPRINTF(PCIDEV,
+                "read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
+                params()->deviceNum, params()->functionNum, offset, size,
+                (uint16_t)(*(uint8_t*)(config.data + offset)));
+        break;
+
+      default:
+        panic("Invalid Read Size");
     }
 }
 
-
 void
 PciDev::WriteConfig(int offset, int size, uint32_t data)
 {
+    if (offset >= PCI_DEVICE_SPECIFIC)
+        panic("Device specific PCI config space not implemented!\n");
+
     uint32_t barnum;
 
     union {
@@ -103,8 +123,10 @@ PciDev::WriteConfig(int offset, int size, uint32_t data)
     };
     word_value = data;
 
-    DPRINTF(PCIDEV, "write device: %#x function: %#x register: %#x size: %#x data: %#x\n",
-                Device, Function, offset, size, word_value);
+    DPRINTF(PCIDEV,
+            "write device: %#x function: %#x reg: %#x size: %d data: %#x\n",
+            params()->deviceNum, params()->functionNum, offset, size,
+            word_value);
 
     barnum = (offset - PCI0_BASE_ADDR0) >> 2;
 
@@ -113,7 +135,8 @@ PciDev::WriteConfig(int offset, int size, uint32_t data)
         switch (offset) {
           case PCI0_INTERRUPT_LINE:
           case PCI_CACHE_LINE_SIZE:
-            *(uint8_t *)&config.data[offset] = byte_value;
+          case PCI_LATENCY_TIMER:
+            *(uint8_t *)&config.data[offset] = htoa(byte_value);
             break;
 
           default:
@@ -126,7 +149,7 @@ PciDev::WriteConfig(int offset, int size, uint32_t data)
           case PCI_COMMAND:
           case PCI_STATUS:
           case PCI_CACHE_LINE_SIZE:
-            *(uint16_t *)&config.data[offset] = half_value;
+            *(uint16_t *)&config.data[offset] = htoa(half_value);
             break;
 
           default:
@@ -145,92 +168,134 @@ PciDev::WriteConfig(int offset, int size, uint32_t data)
           case PCI0_BASE_ADDR3:
           case PCI0_BASE_ADDR4:
           case PCI0_BASE_ADDR5:
-              // Writing 0xffffffff to a BAR tells the card to set the value of the bar
-              // to size of memory it needs
-              if (word_value == 0xffffffff) {
-                 // This is I/O Space, bottom two bits are read only
-                  if(config.data[offset] & 0x1) {
-                    *(uint32_t *)&config.data[offset] =
+            // Writing 0xffffffff to a BAR tells the card to set the
+            // value of the bar
+            // to size of memory it needs
+            if (word_value == 0xffffffff) {
+                // This is I/O Space, bottom two bits are read only
+                if (htoa(config.data[offset]) & 0x1) {
+                    *(uint32_t *)&config.data[offset] = htoa(
                         ~(BARSize[barnum] - 1) |
-                        (config.data[offset] & 0x3);
-                  } else {
-                  // This is memory space, bottom four bits are read only
-                    *(uint32_t *)&config.data[offset] =
+                        (htoa(config.data[offset]) & 0x3));
+                } else {
+                    // This is memory space, bottom four bits are read only
+                    *(uint32_t *)&config.data[offset] = htoa(
                         ~(BARSize[barnum] - 1) |
-                        (config.data[offset] & 0xF);
-                  }
+                        (htoa(config.data[offset]) & 0xF));
+                }
+            } else {
+                MemoryController *mmu = params()->mmu;
+
+                // This is I/O Space, bottom two bits are read only
+                if(htoa(config.data[offset]) & 0x1) {
+                    *(uint32_t *)&config.data[offset] =
+                        htoa((word_value & ~0x3) |
+                        (htoa(config.data[offset]) & 0x3));
 
+                    if (word_value & ~0x1) {
+                        Addr base_addr = (word_value & ~0x1) + TSUNAMI_PCI0_IO;
+                        Addr base_size = BARSize[barnum];
 
-              } else {
-                  // This is I/O Space, bottom two bits are read only
-                  if(config.data[offset] & 0x1) {
-                    *(uint32_t *)&config.data[offset] = (word_value & ~0x3) |
-                                                        (config.data[offset] & 0x3);
-                    if (word_value) {
                         // It's never been set
-                        if (BARAddr[barnum] == 0)
-                            AddMapping(word_value, BARSize[barnum]-1, MMU);
+                        if (BARAddrs[barnum] == 0)
+                            mmu->add_child((FunctionalMemory *)this,
+                                           RangeSize(base_addr, base_size));
                         else
-                            UpdateMapping(BARAddr[barnum], BARSize[barnum]-1,
-                                          word_value, BARSize[barnum]-1, MMU);
-                        BARAddr[barnum] = word_value;
+                            mmu->update_child((FunctionalMemory *)this,
+                                              RangeSize(BARAddrs[barnum],
+                                                        base_size),
+                                              RangeSize(base_addr, base_size));
+
+                        BARAddrs[barnum] = base_addr;
                     }
 
-                  } else {
-                  // This is memory space, bottom four bits are read only
-                    *(uint32_t *)&config.data[offset] = (word_value & ~0xF) |
-                                                        (config.data[offset] & 0xF);
-                  }
-              }
+                } else {
+                    // This is memory space, bottom four bits are read only
+                    *(uint32_t *)&config.data[offset] =
+                        htoa((word_value & ~0xF) |
+                        (htoa(config.data[offset]) & 0xF));
+
+                    if (word_value & ~0x3) {
+                        Addr base_addr = (word_value & ~0x3) +
+                            TSUNAMI_PCI0_MEMORY;
+
+                        Addr base_size = BARSize[barnum];
+
+                        // It's never been set
+                        if (BARAddrs[barnum] == 0)
+                            mmu->add_child((FunctionalMemory *)this,
+                                           RangeSize(base_addr, base_size));
+                        else
+                            mmu->update_child((FunctionalMemory *)this,
+                                              RangeSize(BARAddrs[barnum],
+                                                        base_size),
+                                              RangeSize(base_addr, base_size));
+
+                        BARAddrs[barnum] = base_addr;
+                    }
+                 }
+            }
             break;
+
           case PCI0_ROM_BASE_ADDR:
-                    if (word_value == 0xfffffffe)
-                        *(uint32_t *)&config.data[offset] = 0xffffffff;
-                    else
-                        *(uint32_t *)&config.data[offset] = word_value;
-                break;
-          case PCI_COMMAND:
-                // This could also clear some of the error bits in the Status register
-                // However they should never get set, so lets ignore it for now
-                *(uint16_t *)&config.data[offset] = half_value;
-                break;
+            if (word_value == 0xfffffffe)
+                *(uint32_t *)&config.data[offset] = 0xffffffff;
+            else
+                *(uint32_t *)&config.data[offset] = htoa(word_value);
+            break;
 
+          case PCI_COMMAND:
+            // This could also clear some of the error bits in the Status
+            // register. However they should never get set, so lets ignore
+            // it for now
+            *(uint16_t *)&config.data[offset] = htoa(half_value);
+            break;
 
           default:
-            panic("writing to a read only register");
+            DPRINTF(PCIDEV, "Writing to a read only register");
         }
         break;
     }
-
 }
 
 void
 PciDev::serialize(ostream &os)
 {
+    SERIALIZE_ARRAY(BARSize, 6);
+    SERIALIZE_ARRAY(BARAddrs, 6);
     SERIALIZE_ARRAY(config.data, 64);
 }
 
 void
 PciDev::unserialize(Checkpoint *cp, const std::string &section)
 {
+    UNSERIALIZE_ARRAY(BARSize, 6);
+    UNSERIALIZE_ARRAY(BARAddrs, 6);
     UNSERIALIZE_ARRAY(config.data, 64);
-}
 
+    // Add the MMU mappings for the BARs
+    for (int i=0; i < 6; i++) {
+        if (BARAddrs[i] != 0)
+            params()->mmu->add_child(this, RangeSize(BARAddrs[i], BARSize[i]));
+    }
+}
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciDev)
-
-    Param<int> VendorID;
-    Param<int> DeviceID;
-    Param<int> Command;
-    Param<int> Status;
-    Param<int> Revision;
-    Param<int> ProgIF;
-    Param<int> SubClassCode;
-    Param<int> ClassCode;
-    Param<int> CacheLineSize;
-    Param<int> LatencyTimer;
-    Param<int> HeaderType;
-    Param<int> BIST;
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
+
+    Param<uint16_t> VendorID;
+    Param<uint16_t> DeviceID;
+    Param<uint16_t> Command;
+    Param<uint16_t> Status;
+    Param<uint8_t> Revision;
+    Param<uint8_t> ProgIF;
+    Param<uint8_t> SubClassCode;
+    Param<uint8_t> ClassCode;
+    Param<uint8_t> CacheLineSize;
+    Param<uint8_t> LatencyTimer;
+    Param<uint8_t> HeaderType;
+    Param<uint8_t> BIST;
     Param<uint32_t> BAR0;
     Param<uint32_t> BAR1;
     Param<uint32_t> BAR2;
@@ -238,13 +303,13 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciDev)
     Param<uint32_t> BAR4;
     Param<uint32_t> BAR5;
     Param<uint32_t> CardbusCIS;
-    Param<int> SubsystemVendorID;
-    Param<int> SubsystemID;
+    Param<uint16_t> SubsystemVendorID;
+    Param<uint16_t> SubsystemID;
     Param<uint32_t> ExpansionROM;
-    Param<int> InterruptLine;
-    Param<int> InterruptPin;
-    Param<int> MinimumGrant;
-    Param<int> MaximumLatency;
+    Param<uint8_t> InterruptLine;
+    Param<uint8_t> InterruptPin;
+    Param<uint8_t> MinimumGrant;
+    Param<uint8_t> MaximumLatency;
     Param<uint32_t> BAR0Size;
     Param<uint32_t> BAR1Size;
     Param<uint32_t> BAR2Size;
@@ -252,18 +317,9 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciDev)
     Param<uint32_t> BAR4Size;
     Param<uint32_t> BAR5Size;
 
-    SimObjectParam<MemoryController *> mmu;
-    SimObjectParam<PCIConfigAll*> cf;
-    Param<Addr> addr;
-    Param<Addr> mask;
-    Param<uint32_t> bus;
-    Param<uint32_t> device;
-    Param<uint32_t> func;
+END_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
 
-
-END_DECLARE_SIM_OBJECT_PARAMS(PciDev)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(PciDev)
+BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigData)
 
     INIT_PARAM(VendorID, "Vendor ID"),
     INIT_PARAM(DeviceID, "Device ID"),
@@ -296,56 +352,52 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(PciDev)
     INIT_PARAM_DFLT(BAR2Size, "Base Address Register 2 Size", 0x00),
     INIT_PARAM_DFLT(BAR3Size, "Base Address Register 3 Size", 0x00),
     INIT_PARAM_DFLT(BAR4Size, "Base Address Register 4 Size", 0x00),
-    INIT_PARAM_DFLT(BAR5Size, "Base Address Register 5 Size", 0x00),
-
-    INIT_PARAM(cf, "Pointer to Configspace device"),
-    INIT_PARAM(bus, "PCI Bus Number"),
-    INIT_PARAM(device, "PCI Device number"),
-    INIT_PARAM(func, "PCI Function Number")
+    INIT_PARAM_DFLT(BAR5Size, "Base Address Register 5 Size", 0x00)
 
+END_INIT_SIM_OBJECT_PARAMS(PciConfigData)
 
-END_INIT_SIM_OBJECT_PARAMS(PciDev)
-
-CREATE_SIM_OBJECT(PciDev)
+CREATE_SIM_OBJECT(PciConfigData)
 {
-    PciDev *dev = new PciDev(getInstanceName(), cf, bus, device, func);
-
-    dev->config.hdr.vendor = VendorID;
-    dev->config.hdr.device = DeviceID;
-    dev->config.hdr.command = Command;
-    dev->config.hdr.status = Status;
-    dev->config.hdr.revision = Revision;
-    dev->config.hdr.progIF = ProgIF;
-    dev->config.hdr.subClassCode = SubClassCode;
-    dev->config.hdr.classCode = ClassCode;
-    dev->config.hdr.cacheLineSize = CacheLineSize;
-    dev->config.hdr.latencyTimer = LatencyTimer;
-    dev->config.hdr.headerType = HeaderType;
-    dev->config.hdr.bist = BIST;
-
-    dev->config.hdr.pci0.baseAddr0 = BAR0;
-    dev->config.hdr.pci0.baseAddr1 = BAR1;
-    dev->config.hdr.pci0.baseAddr2 = BAR2;
-    dev->config.hdr.pci0.baseAddr3 = BAR3;
-    dev->config.hdr.pci0.baseAddr4 = BAR4;
-    dev->config.hdr.pci0.baseAddr5 = BAR5;
-    dev->config.hdr.pci0.cardbusCIS = CardbusCIS;
-    dev->config.hdr.pci0.subsystemVendorID = SubsystemVendorID;
-    dev->config.hdr.pci0.subsystemID = SubsystemVendorID;
-    dev->config.hdr.pci0.expansionROM = ExpansionROM;
-    dev->config.hdr.pci0.interruptLine = InterruptLine;
-    dev->config.hdr.pci0.interruptPin = InterruptPin;
-    dev->config.hdr.pci0.minimumGrant = MinimumGrant;
-    dev->config.hdr.pci0.maximumLatency = MaximumLatency;
-
-    dev->BARSize[0] = BAR0Size;
-    dev->BARSize[1] = BAR1Size;
-    dev->BARSize[2] = BAR2Size;
-    dev->BARSize[3] = BAR3Size;
-    dev->BARSize[4] = BAR4Size;
-    dev->BARSize[5] = BAR5Size;
-
-    return dev;
+    PciConfigData *data = new PciConfigData(getInstanceName());
+
+    data->config.hdr.vendor = htoa(VendorID);
+    data->config.hdr.device = htoa(DeviceID);
+    data->config.hdr.command = htoa(Command);
+    data->config.hdr.status = htoa(Status);
+    data->config.hdr.revision = htoa(Revision);
+    data->config.hdr.progIF = htoa(ProgIF);
+    data->config.hdr.subClassCode = htoa(SubClassCode);
+    data->config.hdr.classCode = htoa(ClassCode);
+    data->config.hdr.cacheLineSize = htoa(CacheLineSize);
+    data->config.hdr.latencyTimer = htoa(LatencyTimer);
+    data->config.hdr.headerType = htoa(HeaderType);
+    data->config.hdr.bist = htoa(BIST);
+
+    data->config.hdr.pci0.baseAddr0 = htoa(BAR0);
+    data->config.hdr.pci0.baseAddr1 = htoa(BAR1);
+    data->config.hdr.pci0.baseAddr2 = htoa(BAR2);
+    data->config.hdr.pci0.baseAddr3 = htoa(BAR3);
+    data->config.hdr.pci0.baseAddr4 = htoa(BAR4);
+    data->config.hdr.pci0.baseAddr5 = htoa(BAR5);
+    data->config.hdr.pci0.cardbusCIS = htoa(CardbusCIS);
+    data->config.hdr.pci0.subsystemVendorID = htoa(SubsystemVendorID);
+    data->config.hdr.pci0.subsystemID = htoa(SubsystemVendorID);
+    data->config.hdr.pci0.expansionROM = htoa(ExpansionROM);
+    data->config.hdr.pci0.interruptLine = htoa(InterruptLine);
+    data->config.hdr.pci0.interruptPin = htoa(InterruptPin);
+    data->config.hdr.pci0.minimumGrant = htoa(MinimumGrant);
+    data->config.hdr.pci0.maximumLatency = htoa(MaximumLatency);
+
+    data->BARSize[0] = BAR0Size;
+    data->BARSize[1] = BAR1Size;
+    data->BARSize[2] = BAR2Size;
+    data->BARSize[3] = BAR3Size;
+    data->BARSize[4] = BAR4Size;
+    data->BARSize[5] = BAR5Size;
+
+    return data;
 }
 
-REGISTER_SIM_OBJECT("PciDev", PciDev)
+REGISTER_SIM_OBJECT("PciConfigData", PciConfigData)
+
+#endif // DOXYGEN_SHOULD_SKIP_THIS