X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=dev%2Ftsunami.hh;h=0a7fdbcd92ac2858eed20f61482ca7704c06dc4e;hb=e9f3279334f714de7bbd1415377715cd00a763d5;hp=ef27ff18ead9aae8c4cdad67e9a5ba683acd5f98;hpb=59a6e9d705dd6d143534a42822634f67046ff16c;p=gem5.git

diff --git a/dev/tsunami.hh b/dev/tsunami.hh
index ef27ff18e..0a7fdbcd9 100644
--- a/dev/tsunami.hh
+++ b/dev/tsunami.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2004 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -37,13 +37,13 @@
 
 #include "dev/platform.hh"
 
-class AdaptecController;
+class IdeController;
 class TlaserClock;
-class EtherDev;
+class NSGigE;
 class TsunamiCChip;
 class TsunamiPChip;
 class TsunamiIO;
-class PCIConfigAll;
+class PciConfigAll;
 class System;
 
 /**
@@ -62,12 +62,9 @@ class Tsunami : public Platform
 
     /** Pointer to the system */
     System *system;
+
     /** Pointer to the TsunamiIO device which has the RTC */
     TsunamiIO *io;
-    /** Pointer to the SCSI controller device */
-    AdaptecController *scsi;
-    /** Pointer to the ethernet controller device */
-    EtherDev *ethernet;
 
     /** Pointer to the Tsunami CChip.
       * The chip contains some configuration information and
@@ -81,12 +78,6 @@ class Tsunami : public Platform
       */
     TsunamiPChip *pchip;
 
-    /** Pointer to the PCI Config Space
-      * The config space in Tsunami all needs to return
-      * -1 if a device is not there.
-      */
-    PCIConfigAll *pciconfig;
-
     int intr_sum_type[Tsunami::Max_CPUs];
     int ipi_pending[Tsunami::Max_CPUs];
 
@@ -98,10 +89,46 @@ class Tsunami : public Platform
       * @param intrcontrol pointer to the interrupt controller
       * @param intrFreq frequency that interrupts happen
       */
-    Tsunami(const std::string &name, System *s, SimConsole *con,
-            IntrControl *intctrl, int intrFreq);
+    Tsunami(const std::string &name, System *s, IntrControl *intctrl,
+            PciConfigAll *pci, int intrFreq);
+
+    /**
+     * Return the interrupting frequency to AlphaAccess
+     * @return frequency of RTC interrupts
+     */
+     virtual Tick intrFrequency();
+
+    /**
+     * Cause the cpu to post a serial interrupt to the CPU.
+     */
+    virtual void postConsoleInt();
 
+    /**
+     * Clear a posted CPU interrupt (id=55)
+     */
+    virtual void clearConsoleInt();
+
+    /**
+     * Cause the chipset to post a cpi interrupt to the CPU.
+     */
+    virtual void postPciInt(int line);
+
+    /**
+     * Clear a posted PCI->CPU interrupt
+     */
+    virtual void clearPciInt(int line);
+
+  /**
+     * Serialize this object to the given output stream.
+     * @param os The stream to serialize to.
+     */
     virtual void serialize(std::ostream &os);
+
+    /**
+     * Reconstruct the state of this object from a checkpoint.
+     * @param cp The checkpoint use.
+     * @param section The section name of this object
+     */
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 };