X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=dev%2Ftsunami.hh;h=db266d62d271a184607fa9f7fc3f7958370150b1;hb=19fd3439c738e06be8c43078f520054011a385cc;hp=4edf2113a929c8631aebd1e4275c5858ad0636bd;hpb=09c40bfe4376d12b933116e17b8175f34a194f67;p=gem5.git

diff --git a/dev/tsunami.hh b/dev/tsunami.hh
index 4edf2113a..db266d62d 100644
--- a/dev/tsunami.hh
+++ b/dev/tsunami.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003 The Regents of The University of Michigan
+ * Copyright (c) 2004 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -35,17 +35,16 @@
 #ifndef __TSUNAMI_HH__
 #define __TSUNAMI_HH__
 
-#include "sim/sim_object.hh"
+#include "dev/platform.hh"
 
-class IntrControl;
-class ConsoleListener;
-class SimConsole;
-class AdaptecController;
+class IdeController;
 class TlaserClock;
-class EtherDev;
+class NSGigE;
 class TsunamiCChip;
 class TsunamiPChip;
-class PCIConfigAll;
+class TsunamiIO;
+class PciConfigAll;
+class System;
 
 /**
   * Top level class for Tsunami Chipset emulation.
@@ -54,22 +53,21 @@ class PCIConfigAll;
   * read work
   */
 
-class Tsunami : public SimObject
+class Tsunami : public Platform
 {
   public:
 
     /** Max number of CPUs in a Tsunami */
     static const int Max_CPUs = 4;
 
-    /** Pointer to the interrupt controller (used to post and ack interrupts on the CPU) */
-    IntrControl *intrctrl;
-    /** Pointer to the UART emulation code */
-    SimConsole *cons;
-
-    /** Pointer to the SCSI controller device */
-    AdaptecController *scsi;
+    /** Pointer to the system */
+    System *system;
+    /** Pointer to the TsunamiIO device which has the RTC */
+    TsunamiIO *io;
+    /** Pointer to the disk controller device */
+    IdeController *disk_controller;
     /** Pointer to the ethernet controller device */
-    EtherDev *ethernet;
+    NSGigE *ethernet;
 
     /** Pointer to the Tsunami CChip.
       * The chip contains some configuration information and
@@ -83,17 +81,9 @@ class Tsunami : public SimObject
       */
     TsunamiPChip *pchip;
 
-    /** Pointer to the PCI Config Space
-      * The config space in Tsunami all needs to return
-      * -1 if a device is not there.
-      */
-    PCIConfigAll *pciconfig;
-
     int intr_sum_type[Tsunami::Max_CPUs];
     int ipi_pending[Tsunami::Max_CPUs];
 
-    int interrupt_frequency;
-
   public:
     /**
       * Constructor for the Tsunami Class.
@@ -102,10 +92,36 @@ class Tsunami : public SimObject
       * @param intrcontrol pointer to the interrupt controller
       * @param intrFreq frequency that interrupts happen
       */
-    Tsunami(const std::string &name, EtherDev *ethernet, SimConsole *con,
-            IntrControl *intctrl, int intrFreq);
+    Tsunami(const std::string &name, System *s, IntrControl *intctrl,
+            PciConfigAll *pci, int intrFreq);
 
+    /**
+     * Return the interrupting frequency to AlphaAccess
+     * @return frequency of RTC interrupts
+     */
+     virtual Tick intrFrequency();
+
+    /**
+     * Cause the cpu to post a serial interrupt to the CPU.
+     */
+    virtual void postConsoleInt();
+
+    /**
+     * Clear a posted CPU interrupt (id=55)
+     */
+    virtual void clearConsoleInt();
+
+    /**
+     * Serialize this object to the given output stream.
+     * @param os The stream to serialize to.
+     */
     virtual void serialize(std::ostream &os);
+
+    /**
+     * Reconstruct the state of this object from a checkpoint.
+     * @param cp The checkpoint use.
+     * @param section The section name of this object
+     */
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 };