X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=dev%2Ftsunami.hh;h=db266d62d271a184607fa9f7fc3f7958370150b1;hb=19fd3439c738e06be8c43078f520054011a385cc;hp=f45bb205969c0c151a9adb8585b9fc648f05d58a;hpb=0a585921f0675887df960ca100ae8bfc72ecc671;p=gem5.git diff --git a/dev/tsunami.hh b/dev/tsunami.hh index f45bb2059..db266d62d 100644 --- a/dev/tsunami.hh +++ b/dev/tsunami.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2003 The Regents of The University of Michigan + * Copyright (c) 2004 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -28,24 +28,23 @@ /** * @file - * Declaration of top level class for the Tsunami chipset. This class just retains pointers - * to all its children so the children can communicate + * Declaration of top level class for the Tsunami chipset. This class just + * retains pointers to all its children so the children can communicate. */ #ifndef __TSUNAMI_HH__ #define __TSUNAMI_HH__ -#include "sim/sim_object.hh" +#include "dev/platform.hh" -class IntrControl; -class ConsoleListener; -class SimConsole; -class AdaptecController; +class IdeController; class TlaserClock; -class EtherDev; +class NSGigE; class TsunamiCChip; class TsunamiPChip; -class TsunamiPCIConfig; +class TsunamiIO; +class PciConfigAll; +class System; /** * Top level class for Tsunami Chipset emulation. @@ -54,22 +53,21 @@ class TsunamiPCIConfig; * read work */ -class Tsunami : public SimObject +class Tsunami : public Platform { public: /** Max number of CPUs in a Tsunami */ static const int Max_CPUs = 4; - /** Pointer to the interrupt controller (used to post and ack interrupts on the CPU) */ - IntrControl *intrctrl; - /** Pointer to the UART emulation code */ - SimConsole *cons; - - /** Pointer to the SCSI controller device */ - AdaptecController *scsi; + /** Pointer to the system */ + System *system; + /** Pointer to the TsunamiIO device which has the RTC */ + TsunamiIO *io; + /** Pointer to the disk controller device */ + IdeController *disk_controller; /** Pointer to the ethernet controller device */ - EtherDev *ethernet; + NSGigE *ethernet; /** Pointer to the Tsunami CChip. * The chip contains some configuration information and @@ -83,27 +81,47 @@ class Tsunami : public SimObject */ TsunamiPChip *pchip; - /** Pointer to the Tsunami PCI Config Space - * The config space in tsunami all needs to return - * -1 if a device is not there. - */ - TsunamiPCIConfig *pciconfig; - int intr_sum_type[Tsunami::Max_CPUs]; int ipi_pending[Tsunami::Max_CPUs]; - int interrupt_frequency; - public: /** * Constructor for the Tsunami Class. - * @param + * @param name name of the object + * @param con pointer to the console + * @param intrcontrol pointer to the interrupt controller + * @param intrFreq frequency that interrupts happen */ - Tsunami(const std::string &name, AdaptecController *scsi, - EtherDev *ethernet, - SimConsole *, IntrControl *intctrl, int intrFreq); + Tsunami(const std::string &name, System *s, IntrControl *intctrl, + PciConfigAll *pci, int intrFreq); + /** + * Return the interrupting frequency to AlphaAccess + * @return frequency of RTC interrupts + */ + virtual Tick intrFrequency(); + + /** + * Cause the cpu to post a serial interrupt to the CPU. + */ + virtual void postConsoleInt(); + + /** + * Clear a posted CPU interrupt (id=55) + */ + virtual void clearConsoleInt(); + + /** + * Serialize this object to the given output stream. + * @param os The stream to serialize to. + */ virtual void serialize(std::ostream &os); + + /** + * Reconstruct the state of this object from a checkpoint. + * @param cp The checkpoint use. + * @param section The section name of this object + */ virtual void unserialize(Checkpoint *cp, const std::string §ion); };