X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=dev%2Ftsunami_cchip.hh;h=d33905bc0254172dd16f8f70ca0a523cecedf3c4;hb=8bbaaa7478bdddcd098c4da97f4ac1ba5a97ee67;hp=381fb58f194ec58075ad990c2bea47a930ccbaa9;hpb=93983de0cfa06e58f1d448782269ebd33341ae83;p=gem5.git diff --git a/dev/tsunami_cchip.hh b/dev/tsunami_cchip.hh index 381fb58f1..d33905bc0 100644 --- a/dev/tsunami_cchip.hh +++ b/dev/tsunami_cchip.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2003 The Regents of The University of Michigan + * Copyright (c) 2004 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -26,34 +26,36 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* @file +/** @file * Emulation of the Tsunami CChip CSRs */ #ifndef __TSUNAMI_CCHIP_HH__ #define __TSUNAMI_CCHIP_HH__ -#include "mem/functional_mem/functional_memory.hh" #include "dev/tsunami.hh" +#include "base/range.hh" +#include "dev/io_device.hh" -/* - * Tsunami CChip +/** + * Tsunami CChip CSR Emulation. This device includes all the interrupt + * handling code for the chipset. */ -class TsunamiCChip : public FunctionalMemory +class TsunamiCChip : public PioDevice { private: /** The base address of this device */ Addr addr; /** The size of mappad from the above address */ - static const Addr size = 0xfff; + static const Addr size = 0xfffffff; protected: - /** - * pointer to the tsunami object. - * This is our access to all the other tsunami - * devices. - */ + /** + * pointer to the tsunami object. + * This is our access to all the other tsunami + * devices. + */ Tsunami *tsunami; /** @@ -67,7 +69,6 @@ class TsunamiCChip : public FunctionalMemory * One exists for each CPU, the DRIR X DIM = DIR */ uint64_t dir[Tsunami::Max_CPUs]; - bool dirInterrupting[Tsunami::Max_CPUs]; /** * This register contains bits for each PCI interrupt @@ -75,17 +76,11 @@ class TsunamiCChip : public FunctionalMemory */ uint64_t drir; - /** - * The MISC register contains the CPU we are currently on - * as well as bits to ack RTC and IPI interrupts. - */ - uint64_t misc; - - /** Count of the number of pending IPIs on a CPU */ - uint64_t ipiInterrupting[Tsunami::Max_CPUs]; + /** Indicator of which CPUs have an IPI interrupt */ + uint64_t ipint; - /** Indicator of which CPUs have had an RTC interrupt */ - bool RTCInterrupting[Tsunami::Max_CPUs]; + /** Indicator of which CPUs have an RTC interrupt */ + uint64_t itint; public: /** @@ -95,9 +90,12 @@ class TsunamiCChip : public FunctionalMemory * @param t pointer back to the Tsunami object that we belong to. * @param a address we are mapped at. * @param mmu pointer to the memory controller that sends us events. + * @param hier object to store parameters universal the device hierarchy + * @param bus The bus that this device is attached to */ TsunamiCChip(const std::string &name, Tsunami *t, Addr a, - MemoryController *mmu); + MemoryController *mmu, HierParams *hier, Bus *bus, + Tick pio_latency); /** * Process a read to the CChip. @@ -133,6 +131,25 @@ class TsunamiCChip : public FunctionalMemory */ void clearDRIR(uint32_t interrupt); + /** + * post an ipi interrupt to the CPU. + * @param ipintr the cpu number to clear(bitvector) + */ + void clearIPI(uint64_t ipintr); + + /** + * clear a timer interrupt previously posted to the CPU. + * @param interrupt the cpu number to clear(bitvector) + */ + void clearITI(uint64_t itintr); + + /** + * request an interrupt be posted to the CPU. + * @param ipreq the cpu number to interrupt(bitvector) + */ + void reqIPI(uint64_t ipreq); + + /** * Serialize this object to the given output stream. * @param os The stream to serialize to. @@ -145,6 +162,13 @@ class TsunamiCChip : public FunctionalMemory * @param section The section name of this object */ virtual void unserialize(Checkpoint *cp, const std::string §ion); + + /** + * Return how long this access will take. + * @param req the memory request to calcuate + * @return Tick when the request is done + */ + Tick cacheAccess(MemReqPtr &req); }; #endif // __TSUNAMI_CCHIP_HH__