X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=dev%2Ftsunami_pchip.cc;h=46efc3dfe2183004f901e4fe606f3db35d281f53;hb=fc664f7ca6d4883e9efe7fb823cd903a867af7a9;hp=2ac3cae860699457c9c3005eb46f5c0414ac3823;hpb=9d0aa1399157bd90436409a7596377b4591a2d4a;p=gem5.git diff --git a/dev/tsunami_pchip.cc b/dev/tsunami_pchip.cc index 2ac3cae86..46efc3dfe 100644 --- a/dev/tsunami_pchip.cc +++ b/dev/tsunami_pchip.cc @@ -1,6 +1,32 @@ -/* $Id$ */ +/* + * Copyright (c) 2004-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ -/* @file +/** @file * Tsunami PChip (pci) */ @@ -9,26 +35,27 @@ #include #include "base/trace.hh" -#include "cpu/exec_context.hh" -#include "dev/console.hh" -#include "dev/etherdev.hh" -#include "dev/scsi_ctrl.hh" -#include "dev/tlaser_clock.hh" #include "dev/tsunami_pchip.hh" #include "dev/tsunamireg.h" #include "dev/tsunami.hh" -#include "mem/functional_mem/memory_control.hh" -#include "mem/functional_mem/physical_memory.hh" +#include "mem/bus/bus.hh" +#include "mem/bus/pio_interface.hh" +#include "mem/bus/pio_interface_impl.hh" +#include "mem/functional/memory_control.hh" +#include "mem/functional/physical.hh" #include "sim/builder.hh" #include "sim/system.hh" using namespace std; +//Should this be AlphaISA? +using namespace TheISA; TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a, - MemoryController *mmu) - : FunctionalMemory(name), addr(a), tsunami(t) + MemoryController *mmu, HierParams *hier, + Bus *pio_bus, Tick pio_latency) + : PioDevice(name, t), addr(a), tsunami(t) { - mmu->add_child(this, Range(addr, addr + size)); + mmu->add_child(this, RangeSize(addr, size)); for (int i = 0; i < 4; i++) { wsba[i] = 0; @@ -36,6 +63,17 @@ TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a, tba[i] = 0; } + if (pio_bus) { + pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this, + &TsunamiPChip::cacheAccess); + pioInterface->addAddrRange(RangeSize(addr, size)); + pioLatency = pio_latency * pio_bus->clockRate; + } + + + // initialize pchip control register + pctl = (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36); + //Set back pointer in tsunami tsunami->pchip = this; } @@ -46,7 +84,7 @@ TsunamiPChip::read(MemReqPtr &req, uint8_t *data) DPRINTF(Tsunami, "read va=%#x size=%d\n", req->vaddr, req->size); - Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6; + Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6; switch (req->size) { @@ -54,59 +92,60 @@ TsunamiPChip::read(MemReqPtr &req, uint8_t *data) switch(daddr) { case TSDEV_PC_WSBA0: *(uint64_t*)data = wsba[0]; - return No_Fault; + return NoFault; case TSDEV_PC_WSBA1: *(uint64_t*)data = wsba[1]; - return No_Fault; + return NoFault; case TSDEV_PC_WSBA2: *(uint64_t*)data = wsba[2]; - return No_Fault; + return NoFault; case TSDEV_PC_WSBA3: *(uint64_t*)data = wsba[3]; - return No_Fault; + return NoFault; case TSDEV_PC_WSM0: *(uint64_t*)data = wsm[0]; - return No_Fault; + return NoFault; case TSDEV_PC_WSM1: *(uint64_t*)data = wsm[1]; - return No_Fault; + return NoFault; case TSDEV_PC_WSM2: *(uint64_t*)data = wsm[2]; - return No_Fault; + return NoFault; case TSDEV_PC_WSM3: *(uint64_t*)data = wsm[3]; - return No_Fault; + return NoFault; case TSDEV_PC_TBA0: *(uint64_t*)data = tba[0]; - return No_Fault; + return NoFault; case TSDEV_PC_TBA1: *(uint64_t*)data = tba[1]; - return No_Fault; + return NoFault; case TSDEV_PC_TBA2: *(uint64_t*)data = tba[2]; - return No_Fault; + return NoFault; case TSDEV_PC_TBA3: *(uint64_t*)data = tba[3]; - return No_Fault; + return NoFault; case TSDEV_PC_PCTL: - // might want to change the clock?? - *(uint64_t*)data = 0x00; // try this - return No_Fault; + *(uint64_t*)data = pctl; + return NoFault; case TSDEV_PC_PLAT: panic("PC_PLAT not implemented\n"); case TSDEV_PC_RES: panic("PC_RES not implemented\n"); case TSDEV_PC_PERROR: - panic("PC_PERROR not implemented\n"); + *(uint64_t*)data = 0x00; + return NoFault; case TSDEV_PC_PERRMASK: - panic("PC_PERRMASK not implemented\n"); + *(uint64_t*)data = 0x00; + return NoFault; case TSDEV_PC_PERRSET: panic("PC_PERRSET not implemented\n"); case TSDEV_PC_TLBIV: panic("PC_TLBIV not implemented\n"); case TSDEV_PC_TLBIA: *(uint64_t*)data = 0x00; // shouldn't be readable, but linux - return No_Fault; + return NoFault; case TSDEV_PC_PMONCTL: panic("PC_PMONCTL not implemented\n"); case TSDEV_PC_PMONCNT: @@ -125,7 +164,7 @@ TsunamiPChip::read(MemReqPtr &req, uint8_t *data) } DPRINTFN("Tsunami PChip ERROR: read daddr=%#x size=%d\n", daddr, req->size); - return No_Fault; + return NoFault; } Fault @@ -134,7 +173,7 @@ TsunamiPChip::write(MemReqPtr &req, const uint8_t *data) DPRINTF(Tsunami, "write - va=%#x size=%d \n", req->vaddr, req->size); - Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6; + Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6; switch (req->size) { @@ -142,50 +181,49 @@ TsunamiPChip::write(MemReqPtr &req, const uint8_t *data) switch(daddr) { case TSDEV_PC_WSBA0: wsba[0] = *(uint64_t*)data; - return No_Fault; + return NoFault; case TSDEV_PC_WSBA1: wsba[1] = *(uint64_t*)data; - return No_Fault; + return NoFault; case TSDEV_PC_WSBA2: wsba[2] = *(uint64_t*)data; - return No_Fault; + return NoFault; case TSDEV_PC_WSBA3: wsba[3] = *(uint64_t*)data; - return No_Fault; + return NoFault; case TSDEV_PC_WSM0: wsm[0] = *(uint64_t*)data; - return No_Fault; + return NoFault; case TSDEV_PC_WSM1: wsm[1] = *(uint64_t*)data; - return No_Fault; + return NoFault; case TSDEV_PC_WSM2: wsm[2] = *(uint64_t*)data; - return No_Fault; + return NoFault; case TSDEV_PC_WSM3: wsm[3] = *(uint64_t*)data; - return No_Fault; + return NoFault; case TSDEV_PC_TBA0: tba[0] = *(uint64_t*)data; - return No_Fault; + return NoFault; case TSDEV_PC_TBA1: tba[1] = *(uint64_t*)data; - return No_Fault; + return NoFault; case TSDEV_PC_TBA2: tba[2] = *(uint64_t*)data; - return No_Fault; + return NoFault; case TSDEV_PC_TBA3: tba[3] = *(uint64_t*)data; - return No_Fault; + return NoFault; case TSDEV_PC_PCTL: - // might want to change the clock?? - //*(uint64_t*)data; // try this - return No_Fault; + pctl = *(uint64_t*)data; + return NoFault; case TSDEV_PC_PLAT: panic("PC_PLAT not implemented\n"); case TSDEV_PC_RES: panic("PC_RES not implemented\n"); case TSDEV_PC_PERROR: - panic("PC_PERROR not implemented\n"); + return NoFault; case TSDEV_PC_PERRMASK: panic("PC_PERRMASK not implemented\n"); case TSDEV_PC_PERRSET: @@ -193,7 +231,7 @@ TsunamiPChip::write(MemReqPtr &req, const uint8_t *data) case TSDEV_PC_TLBIV: panic("PC_TLBIV not implemented\n"); case TSDEV_PC_TLBIA: - return No_Fault; // value ignored, supposted to invalidate SG TLB + return NoFault; // value ignored, supposted to invalidate SG TLB case TSDEV_PC_PMONCTL: panic("PC_PMONCTL not implemented\n"); case TSDEV_PC_PMONCNT: @@ -213,7 +251,7 @@ TsunamiPChip::write(MemReqPtr &req, const uint8_t *data) DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size); - return No_Fault; + return NoFault; } #define DMA_ADDR_MASK ULL(0x3ffffffff) @@ -233,12 +271,29 @@ TsunamiPChip::translatePciToDma(Addr busAddr) Addr pteAddr; Addr dmaAddr; +#if 0 + DPRINTF(IdeDisk, "Translation for bus address: %#x\n", busAddr); for (int i = 0; i < 4; i++) { + DPRINTF(IdeDisk, "(%d) base:%#x mask:%#x\n", + i, wsba[i], wsm[i]); + windowBase = wsba[i]; - windowMask = ~wsm[i] & (0x7ff << 20); + windowMask = ~wsm[i] & (ULL(0xfff) << 20); if ((busAddr & windowMask) == (windowBase & windowMask)) { + DPRINTF(IdeDisk, "Would have matched %d (wb:%#x wm:%#x --> ba&wm:%#x wb&wm:%#x)\n", + i, windowBase, windowMask, (busAddr & windowMask), + (windowBase & windowMask)); + } + } +#endif + for (int i = 0; i < 4; i++) { + + windowBase = wsba[i]; + windowMask = ~wsm[i] & (ULL(0xfff) << 20); + + if ((busAddr & windowMask) == (windowBase & windowMask)) { if (wsba[i] & 0x1) { // see if enabled if (wsba[i] & 0x2) { // see if SG bit is set @@ -252,8 +307,8 @@ TsunamiPChip::translatePciToDma(Addr busAddr) to create an address for the SG page */ - tbaMask = ~(((wsm[i] & (0x7ff << 20)) >> 10) | 0x3ff); - baMask = (wsm[i] & (0x7ff << 20)) | (0x7f << 13); + tbaMask = ~(((wsm[i] & (ULL(0xfff) << 20)) >> 10) | ULL(0x3ff)); + baMask = (wsm[i] & (ULL(0xfff) << 20)) | (ULL(0x7f) << 13); pteAddr = (tba[i] & tbaMask) | ((busAddr & baMask) >> 10); memcpy((void *)&pteEntry, @@ -261,10 +316,10 @@ TsunamiPChip::translatePciToDma(Addr busAddr) physmem->dma_addr(pteAddr, sizeof(uint64_t)), sizeof(uint64_t)); - dmaAddr = ((pteEntry & ~0x1) << 12) | (busAddr & 0x1fff); + dmaAddr = ((pteEntry & ~ULL(0x1)) << 12) | (busAddr & ULL(0x1fff)); } else { - baMask = (wsm[i] & (0x7ff << 20)) | 0xfffff; + baMask = (wsm[i] & (ULL(0xfff) << 20)) | ULL(0xfffff); tbaMask = ~baMask; dmaAddr = (tba[i] & tbaMask) | (busAddr & baMask); } @@ -274,12 +329,14 @@ TsunamiPChip::translatePciToDma(Addr busAddr) } } - return 0; + // if no match was found, then return the original address + return busAddr; } void TsunamiPChip::serialize(std::ostream &os) { + SERIALIZE_SCALAR(pctl); SERIALIZE_ARRAY(wsba, 4); SERIALIZE_ARRAY(wsm, 4); SERIALIZE_ARRAY(tba, 4); @@ -288,16 +345,26 @@ TsunamiPChip::serialize(std::ostream &os) void TsunamiPChip::unserialize(Checkpoint *cp, const std::string §ion) { + UNSERIALIZE_SCALAR(pctl); UNSERIALIZE_ARRAY(wsba, 4); UNSERIALIZE_ARRAY(wsm, 4); UNSERIALIZE_ARRAY(tba, 4); } +Tick +TsunamiPChip::cacheAccess(MemReqPtr &req) +{ + return curTick + pioLatency; +} + BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip) SimObjectParam tsunami; SimObjectParam mmu; Param addr; + SimObjectParam pio_bus; + Param pio_latency; + SimObjectParam hier; END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip) @@ -305,13 +372,17 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip) INIT_PARAM(tsunami, "Tsunami"), INIT_PARAM(mmu, "Memory Controller"), - INIT_PARAM(addr, "Device Address") + INIT_PARAM(addr, "Device Address"), + INIT_PARAM_DFLT(pio_bus, "The IO Bus to attach to", NULL), + INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1), + INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams) END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip) CREATE_SIM_OBJECT(TsunamiPChip) { - return new TsunamiPChip(getInstanceName(), tsunami, addr, mmu); + return new TsunamiPChip(getInstanceName(), tsunami, addr, mmu, hier, + pio_bus, pio_latency); } REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)