X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=docs.mdwn;h=16ea0e58c4b06b8bf03166534229ef5c0f7d9caf;hb=502c36b10264586aed3fd9636624bfd1649b1a76;hp=6951ac33a0c54f2bf347343ba2c1a31f62f15220;hpb=4927cf20a9da84741127c96d191486ae81dbb544;p=libreriscv.git diff --git a/docs.mdwn b/docs.mdwn index 6951ac33a..16ea0e58c 100644 --- a/docs.mdwn +++ b/docs.mdwn @@ -3,24 +3,21 @@ A draft version of the specification is available at -## Codebase Structure +# Codebase Structure -The SOC is partitioned into three repositories. The subrepositories are -intended as standalone projects useful outside of LibreSOC. For example, +The SOC is partitioned into four repositories. The subrepositories are +intended as general purpose standalone projects useful outside of LibreSOC. For example, the IEE754 FPU repository is a general purpose IEEE754 toolkit for the construction of FSMs and arbitrary length pipelines. | Git Repo | Online docs | Description | Pypi | |----------|---------------|---------------|-------- | [SOC](https://git.libre-soc.org/?p=soc.git;a=tree) | [Libre-SOC](https://docs.libre-soc.org/soc/) | Main OpenPOWER Hybrid CPU-GPU | TBD | -| [FPU](https://git.libre-soc.org/?p=ieee754fpu.git;a=tree) | -- | Equivalent to hardfloat-3 | [libresoc-ieee754fpu](https://pypi.org/project/libresoc-ieee754fpu) | -| [nmutil](https://git.libre-soc.org/?p=nmutil.git;a=tree) | -- | Equivalent to Chisel3.util | [libresoc-nmutil](https://pypi.org/project/libresoc-nmutil) | +| [FPU](https://git.libre-soc.org/?p=ieee754fpu.git;a=tree) | [ieee754fpu](https://docs.libre-soc.org/ieee754fpu/) | Equivalent to hardfloat-3 | [libresoc-ieee754fpu](https://pypi.org/project/libresoc-ieee754fpu) | +| [nmutil](https://git.libre-soc.org/?p=nmutil.git;a=tree) | [nmutil](https://docs.libre-soc.org/nmutil/) | Equivalent to Chisel3.util | [libresoc-nmutil](https://pypi.org/project/libresoc-nmutil) | | [OpenPOWER ISA](https://git.libre-soc.org/?p=nmutil.git;a=tree) | [OpenPOWER ISA](https://docs.libre-soc.org/openpower-isa/) | Simulator, ISA spec compiler, co-simulation infrastructure | [libresoc-openpower-isa](https://pypi.org/project/libresoc-openpower-isa/) | - -Also see [[SOC Architecture|3d_gpu/architecture]] - -## Installing the Codebase +# Installing the Codebase Installation is much easier when using the [install scripts](https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=hdl-dev-repos;hb=HEAD). @@ -33,31 +30,32 @@ The chroot is useful to ensure stability and repeatable builds: no errors or issues introduced by libraries being wrong versions. Also relevant is the [gdb gcc build](https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=ppc64-gdb-gcc;hb=HEAD). - pip3 install virtualenv requests - mkdir ~/.virtualenvs && cd ~/.virtualenvs - python3 -m venv libresoc - source ~/.virtualenvs/libresoc/bin/activate - - cd ~; mkdir libresoc; cd libresoc - git clone https://git.libre-soc.org/git/nmutil.git - git clone https://git.libre-soc.org/git/openpower-isa.git - git clone https://git.libre-soc.org/git/c4m-jtag.git - git clone https://git.libre-soc.org/git/ieee754fpu.git - git clone https://git.libre-soc.org/git/soc.git - - cd nmutil; make develop; cd .. - cd openpower-isa; make develop; cd .. - cd c4m-jtag; make develop; cd .. - cd ieee754fpu; make develop; cd .. - cd soc; make gitupdate; make develop; cd .. - - python3 soc/src/soc/decoder/power_decoder.py - yosys -p "read_ilang decoder.il; show dec31" - -## Gtkwave Tutorial - -[[docs/gtkwave_tutorial]] - -## Formal proof notes - -[[docs/notes_on_formal_proofs]] +For a simple set of commands to follow, see [[HDL_workflow/devscripts]]. If +you prefer to do a manual install and explicitly install dependencies +yourself, in order to verify them, see [[HDL_workflow]] + +# Tutorials and documentation + +* [[SOC Architecture|3d_gpu/architecture]] +* Gtkwave Tutorial [[docs/gtkwave_tutorial]] +* Formal proof notes [[docs/notes_on_formal_proofs]] +* Learning nmigen [[docs/learning_nmigen]] +* Test API [[docs/testapi]] +* Pinmux and JTAG Boundary Scan [[docs/pinmux]] +* pypowersim python-based command-line simulator [[docs/pypowersim]] +* First steps [[docs/firststeps]] + +# SVP64 + +Currently in Draft form, [[openpower/sv/svp64]] is the basis of the +Supercomputing Cray-style Vectorisation of the Power ISA. + +# Checklist for adding an instruction + +TODO. use the commit diffs for these instructions as a guide + +* fmvis +* avgadd etc. +* int min/max +* ternlogi which included + adding a hardware implementation as well