X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=fpga%2Fu500vc707devkit%2Fscript%2Fprologue.tcl;h=0fca22835eeb9f5e12c70275096b135898dbb9b7;hb=c14985f3a78aa0f19f4e4c3eae42a3e8e512910c;hp=91fdf974d73fbb101a11a75eced8281f7d1e290b;hpb=3cf8128a3037cbe02a1542c43f7bf3798f6060b1;p=freedom-sifive.git

diff --git a/fpga/u500vc707devkit/script/prologue.tcl b/fpga/u500vc707devkit/script/prologue.tcl
index 91fdf97..0fca228 100644
--- a/fpga/u500vc707devkit/script/prologue.tcl
+++ b/fpga/u500vc707devkit/script/prologue.tcl
@@ -50,15 +50,10 @@ if {[info exists ::env(EXTRA_VSRCS)]} {
 #}
 
 set vsrc_top $::env(VSRC_TOP)
-set vsrc_consts $::env(VSRC_CONSTS)
 
-set_property verilog_define [list \
-                                 "VSRC_CONSTS=${vsrc_consts}" \
-                                 "VSRC_TOP=${vsrc_top}" \
-                                ] $obj
+set_property verilog_define [list "VSRC_TOP=${vsrc_top}"] $obj
 
 add_files -norecurse -fileset $obj $vsrc_top
-add_files -norecurse -fileset $obj $vsrc_consts
 
 if {[get_filesets -quiet sim_1] eq ""} {
   create_fileset -simset sim_1