X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=gas%2Fconfig%2Ftc-d10v.c;h=268f9517ec8021ef8e4f30bb3b4d84d068fc282e;hb=d0352a18a504a4e7b761f6b3264cf11347d8d056;hp=4a466fda4095ab191b2cd1abb62c06e2659a741a;hpb=edb89bfc5b7a844b6e44f089b605ebc576f031ba;p=binutils-gdb.git diff --git a/gas/config/tc-d10v.c b/gas/config/tc-d10v.c index 4a466fda409..268f9517ec8 100644 --- a/gas/config/tc-d10v.c +++ b/gas/config/tc-d10v.c @@ -1,6 +1,5 @@ /* tc-d10v.c -- Assembler code for the Mitsubishi D10V - - Copyright (C) 1996 Free Software Foundation. + Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation. This file is part of GAS, the GNU Assembler. @@ -35,7 +34,12 @@ const char FLT_CHARS[] = "dD"; int Optimizing = 0; -#define AT_WORD (-1) +#define AT_WORD_P(X) ((X)->X_op == O_right_shift \ + && (X)->X_op_symbol != NULL \ + && symbol_constant_p ((X)->X_op_symbol) \ + && S_GET_VALUE ((X)->X_op_symbol) == AT_WORD_RIGHT_SHIFT) +#define AT_WORD_RIGHT_SHIFT 2 + /* fixups */ #define MAX_INSN_FIXUPS (5) @@ -58,6 +62,18 @@ typedef struct _fixups static Fixups FixUps[2]; static Fixups *fixups; +static int do_not_ignore_hash = 0; + +typedef int packing_type; +#define PACK_UNSPEC (0) /* packing order not specified */ +#define PACK_PARALLEL (1) /* "||" */ +#define PACK_LEFT_RIGHT (2) /* "->" */ +#define PACK_RIGHT_LEFT (3) /* "<-" */ +static packing_type etype = PACK_UNSPEC; /* used by d10v_cleanup */ + +/* True if instruction swapping warnings should be inhibited. */ +static unsigned char flag_warn_suppress_instructionswap; /* --nowarnswap */ + /* local functions */ static int reg_name_search PARAMS ((char *name)); static int register_name PARAMS ((expressionS *expressionP)); @@ -70,15 +86,19 @@ static unsigned long build_insn PARAMS ((struct d10v_opcode *opcode, expressionS static void write_long PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx)); static void write_1_short PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx)); static int write_2_short PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1, - struct d10v_opcode *opcode2, unsigned long insn2, int exec_type, Fixups *fx)); + struct d10v_opcode *opcode2, unsigned long insn2, packing_type exec_type, Fixups *fx)); static unsigned long do_assemble PARAMS ((char *str, struct d10v_opcode **opcode)); static unsigned long d10v_insert_operand PARAMS (( unsigned long insn, int op_type, offsetT value, int left, fixS *fix)); static int parallel_ok PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1, - struct d10v_opcode *opcode2, unsigned long insn2)); + struct d10v_opcode *opcode2, unsigned long insn2, + packing_type exec_type)); +static symbolS * find_symbol_matching_register PARAMS ((expressionS *)); - -struct option md_longopts[] = { +struct option md_longopts[] = +{ +#define OPTION_NOWARNSWAP (OPTION_MD_BASE) + {"nowarnswap", no_argument, NULL, OPTION_NOWARNSWAP}, {NULL, no_argument, NULL, 0} }; size_t md_longopts_size = sizeof(md_longopts); @@ -95,7 +115,7 @@ const pseudo_typeS md_pseudo_table[] = /* Opcode hash table. */ static struct hash_control *d10v_hash; -/* reg_name_search does a binary search of the pre_defined_registers +/* reg_name_search does a binary search of the d10v_predefined_registers array to see if "name" is a valid regiter name. Returns the register number from the array on success, or -1 on failure. */ @@ -107,18 +127,18 @@ reg_name_search (name) int cmp; low = 0; - high = reg_name_cnt() - 1; + high = d10v_reg_name_cnt() - 1; do { middle = (low + high) / 2; - cmp = strcasecmp (name, pre_defined_registers[middle].name); + cmp = strcasecmp (name, d10v_predefined_registers[middle].name); if (cmp < 0) high = middle - 1; else if (cmp > 0) low = middle + 1; else - return pre_defined_registers[middle].value; + return d10v_predefined_registers[middle].value; } while (low <= high); return -1; @@ -147,7 +167,7 @@ register_name (expressionP) { expressionP->X_op = O_register; /* temporarily store a pointer to the string here */ - expressionP->X_op_symbol = (struct symbol *)input_line_pointer; + expressionP->X_op_symbol = (symbolS *)input_line_pointer; expressionP->X_add_number = reg_number; input_line_pointer = p; return 1; @@ -183,10 +203,19 @@ check_range (num, bits, flags) if (flags & OPERAND_SIGNED) { - max = (1 << (bits - 1))-1; - min = - (1 << (bits - 1)); - if (((long)num > max) || ((long)num < min)) - retval = 1; + /* Signed 3-bit integers are restricted to the (-2, 3) range */ + if (flags & RESTRICTED_NUM3) + { + if ((long) num < -2 || (long) num > 3) + retval = 1; + } + else + { + max = (1 << (bits - 1)) - 1; + min = - (1 << (bits - 1)); + if (((long) num > max) || ((long) num < min)) + retval = 1; + } } else { @@ -203,8 +232,8 @@ void md_show_usage (stream) FILE *stream; { - fprintf(stream, "D10V options:\n\ --O optimize. Will do some operations in parallel.\n"); + fprintf(stream, _("D10V options:\n\ +-O optimize. Will do some operations in parallel.\n")); } int @@ -218,6 +247,9 @@ md_parse_option (c, arg) /* Optimize. Will attempt to parallelize operations */ Optimizing = 1; break; + case OPTION_NOWARNSWAP: + flag_warn_suppress_instructionswap = 1; + break; default: return 0; } @@ -256,7 +288,7 @@ md_atof (type, litP, sizeP) break; default: *sizeP = 0; - return "bad call to md_atof"; + return _("bad call to md_atof"); } t = atof_ieee (input_line_pointer, type, words); @@ -279,7 +311,6 @@ md_convert_frag (abfd, sec, fragP) asection *sec; fragS *fragP; { - printf ("call to md_convert_frag \n"); abort (); } @@ -354,7 +385,6 @@ get_reloc (op) { int bits = op->bits; - /* printf("get_reloc: bits=%d address=%d\n",bits,op->flags & OPERAND_ADDR); */ if (bits <= 4) return (0); @@ -380,7 +410,8 @@ get_operands (exp) char *p = input_line_pointer; int numops = 0; int post = 0; - + int uses_at = 0; + while (*p) { while (*p == ' ' || *p == '\t' || *p == ',') @@ -390,6 +421,8 @@ get_operands (exp) if (*p == '@') { + uses_at = 1; + p++; exp[numops].X_op = O_absent; if (*p == '(') @@ -424,27 +457,61 @@ get_operands (exp) if (!register_name (&exp[numops])) { /* parse as an expression */ - expression (&exp[numops]); + if (uses_at) + { + /* Any expression that involves the indirect addressing + cannot also involve immediate addressing. Therefore + the use of the hash character is illegal. */ + int save = do_not_ignore_hash; + do_not_ignore_hash = 1; + + expression (&exp[numops]); + + do_not_ignore_hash = save; + } + else + expression (&exp[numops]); } - if (!strncasecmp (input_line_pointer, "@word", 5)) + if (strncasecmp (input_line_pointer, "@word", 5) == 0) { + input_line_pointer += 5; if (exp[numops].X_op == O_register) { - /* if it looked like a register name but was followed by "@word" */ - /* then it was really a symbol, so change it to one */ + /* if it looked like a register name but was followed by + "@word" then it was really a symbol, so change it to + one */ exp[numops].X_op = O_symbol; exp[numops].X_add_symbol = symbol_find_or_make ((char *)exp[numops].X_op_symbol); - exp[numops].X_op_symbol = NULL; } - exp[numops].X_add_number = AT_WORD; - input_line_pointer += 5; + + /* check for identifier@word+constant */ + if (*input_line_pointer == '-' || *input_line_pointer == '+') + { + char *orig_line = input_line_pointer; + expressionS new_exp; + expression (&new_exp); + exp[numops].X_add_number = new_exp.X_add_number; + } + + /* convert expr into a right shift by AT_WORD_RIGHT_SHIFT */ + { + expressionS new_exp; + memset (&new_exp, 0, sizeof new_exp); + new_exp.X_add_number = AT_WORD_RIGHT_SHIFT; + new_exp.X_op = O_constant; + new_exp.X_unsigned = 1; + exp[numops].X_op_symbol = make_expr_symbol (&new_exp); + exp[numops].X_op = O_right_shift; + } + + know (AT_WORD_P (&exp[numops])); } if (exp[numops].X_op == O_illegal) - as_bad ("illegal operand"); + as_bad (_("illegal operand")); else if (exp[numops].X_op == O_absent) - as_bad ("missing operand"); + as_bad (_("missing operand")); numops++; p = input_line_pointer; @@ -484,7 +551,7 @@ d10v_insert_operand (insn, op_type, value, left, fix) /* truncate to the proper number of bits */ if (check_range (value, bits, d10v_operands[op_type].flags)) - as_bad_where (fix->fx_file, fix->fx_line, "operand out of range: %d", value); + as_bad_where (fix->fx_file, fix->fx_line, _("operand out of range: %d"), value); value &= 0x7FFFFFFF >> (31 - bits); insn |= (value << shift); @@ -503,7 +570,7 @@ build_insn (opcode, opers, insn) unsigned long insn; { int i, bits, shift, flags, format; - unsigned int number; + unsigned long number; /* the insn argument is only used for the DIVS kludge */ if (insn) @@ -532,22 +599,25 @@ build_insn (opcode, opers, insn) { /* now create a fixup */ - /* - printf("need a fixup: "); - print_expr_1(stdout,&opers[i]); - printf("\n"); - */ - if (fixups->fc >= MAX_INSN_FIXUPS) - as_fatal ("too many fixups"); + as_fatal (_("too many fixups")); - if (opers[i].X_op == O_symbol && number == AT_WORD) + if (AT_WORD_P (&opers[i])) { - number = opers[i].X_add_number = 0; + /* Reconize XXX>>1+N aka XXX@word+N as special (AT_WORD) */ fixups->fix[fixups->fc].reloc = BFD_RELOC_D10V_18; - } else - fixups->fix[fixups->fc].reloc = - get_reloc((struct d10v_operand *)&d10v_operands[opcode->operands[i]]); + opers[i].X_op = O_symbol; + opers[i].X_op_symbol = NULL; /* Should free it */ + /* number is left shifted by AT_WORD_RIGHT_SHIFT so + that, it is aligned with the symbol's value. Later, + BFD_RELOC_D10V_18 will right shift (symbol_value + + X_add_number). */ + number <<= AT_WORD_RIGHT_SHIFT; + opers[i].X_add_number = number; + } + else + fixups->fix[fixups->fc].reloc = + get_reloc((struct d10v_operand *)&d10v_operands[opcode->operands[i]]); if (fixups->fix[fixups->fc].reloc == BFD_RELOC_16 || fixups->fix[fixups->fc].reloc == BFD_RELOC_D10V_18) @@ -563,7 +633,7 @@ build_insn (opcode, opers, insn) /* truncate to the proper number of bits */ if ((opers[i].X_op == O_constant) && check_range (number, bits, flags)) - as_bad("operand out of range: %d",number); + as_bad (_("operand out of range: %d"),number); number &= 0x7FFFFFFF >> (31 - bits); insn = insn | (number << shift); } @@ -588,7 +658,6 @@ write_long (opcode, insn, fx) char *f = frag_more(4); insn |= FM11; - /* printf("INSN: %08x\n",insn); */ number_to_chars_bigendian (f, insn, 4); for (i=0; i < fx->fc; i++) @@ -598,11 +667,6 @@ write_long (opcode, insn, fx) where = f - frag_now->fr_literal; if (fx->fix[i].size == 2) where += 2; - /* - printf("fix_new_exp: where:%x size:%d\n ",where,fx->fix[i].size); - print_expr_1(stdout,&(fx->fix[i].exp)); - printf("\n"); - */ if (fx->fix[i].reloc == BFD_RELOC_D10V_18) fx->fix[i].operand |= 4096; @@ -630,7 +694,7 @@ write_1_short (opcode, insn, fx) int i, where; if (opcode->exec_type & PARONLY) - as_fatal ("Instruction must be executed in parallel with another instruction."); + as_fatal (_("Instruction must be executed in parallel with another instruction.")); /* the other container needs to be NOP */ /* according to 4.3.1: for FM=00, sub-instructions performed only @@ -640,7 +704,6 @@ write_1_short (opcode, insn, fx) else insn = FM00 | (insn << 15) | NOP; /* left container */ - /* printf("INSN: %08x\n",insn); */ number_to_chars_bigendian (f, insn, 4); for (i=0; i < fx->fc; i++) { @@ -650,12 +713,6 @@ write_1_short (opcode, insn, fx) if (fx->fix[i].size == 2) where += 2; - /* - printf("fix_new_exp: where:%x size:%d\n ",where, fx->fix[i].size); - print_expr_1(stdout,&(fx->fix[i].exp)); - printf("\n"); - */ - if (fx->fix[i].reloc == BFD_RELOC_D10V_18) fx->fix[i].operand |= 4096; @@ -674,38 +731,40 @@ write_1_short (opcode, insn, fx) fx->fc = 0; } -/* write out a short form instruction if possible */ -/* return number of instructions not written out */ +/* Expects two short instructions. + If possible, writes out both as a single packed instruction. + Otherwise, writes out the first one, packed with a NOP. + Returns number of instructions not written out. */ + static int write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx) struct d10v_opcode *opcode1, *opcode2; unsigned long insn1, insn2; - int exec_type; + packing_type exec_type; Fixups *fx; { unsigned long insn; char *f; int i,j, where; - if ( (exec_type != 1) && ((opcode1->exec_type & PARONLY) + if ( (exec_type != PACK_PARALLEL) && ((opcode1->exec_type & PARONLY) || (opcode2->exec_type & PARONLY))) - as_fatal("Instruction must be executed in parallel"); + as_fatal (_("Instruction must be executed in parallel")); if ( (opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE)) - as_fatal ("Long instructions may not be combined."); + as_fatal (_("Long instructions may not be combined.")); - if(opcode1->exec_type & BRANCH_LINK && opcode2->exec_type != PARONLY) - { - /* subroutines must be called from 32-bit boundaries */ - /* so the return address will be correct */ - write_1_short (opcode1, insn1, fx->next); - return (1); - } switch (exec_type) { - case 0: /* order not specified */ - if ( Optimizing && parallel_ok (opcode1, insn1, opcode2, insn2)) + case PACK_UNSPEC: /* order not specified */ + if (opcode1->exec_type & ALONE) + { + /* Case of a short branch on a separate GAS line. Pack with NOP. */ + write_1_short (opcode1, insn1, fx->next); + return 1; + } + if (Optimizing && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type)) { /* parallel */ if (opcode1->unit == IU) @@ -715,65 +774,104 @@ write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx) else { insn = FM00 | (insn1 << 15) | insn2; + /* Advance over dummy fixup since packed insn1 in L */ fx = fx->next; } } else if (opcode1->unit == IU) - { - /* reverse sequential */ - insn = FM10 | (insn2 << 15) | insn1; - } + /* reverse sequential with IU opcode1 on right and done first */ + insn = FM10 | (insn2 << 15) | insn1; else { - /* sequential */ + /* sequential with non-IU opcode1 on left and done first */ insn = FM01 | (insn1 << 15) | insn2; - fx = fx->next; + /* Advance over dummy fixup since packed insn1 in L */ + fx = fx->next; } break; - case 1: /* parallel */ - if (opcode1->exec_type & SEQ || opcode2->exec_type & SEQ) - as_fatal ("One of these instructions may not be executed in parallel."); + + case PACK_PARALLEL: + if (opcode1->exec_type & SEQ || opcode2->exec_type & SEQ) + as_fatal + (_("One of these instructions may not be executed in parallel.")); if (opcode1->unit == IU) { if (opcode2->unit == IU) - as_fatal ("Two IU instructions may not be executed in parallel"); - as_warn ("Swapping instruction order"); + as_fatal (_("Two IU instructions may not be executed in parallel")); + if (!flag_warn_suppress_instructionswap) + as_warn (_("Swapping instruction order")); insn = FM00 | (insn2 << 15) | insn1; } else if (opcode2->unit == MU) { if (opcode1->unit == MU) - as_fatal ("Two MU instructions may not be executed in parallel"); - as_warn ("Swapping instruction order"); + as_fatal (_("Two MU instructions may not be executed in parallel")); + if (!flag_warn_suppress_instructionswap) + as_warn (_("Swapping instruction order")); insn = FM00 | (insn2 << 15) | insn1; } else { insn = FM00 | (insn1 << 15) | insn2; + /* Advance over dummy fixup since packed insn1 in L */ fx = fx->next; } break; - case 2: /* sequential */ - if (opcode1->unit == IU) - as_fatal ("IU instruction may not be in the left container"); - insn = FM01 | (insn1 << 15) | insn2; + + + case PACK_LEFT_RIGHT: + if (opcode1->unit != IU) + insn = FM01 | (insn1 << 15) | insn2; + else if (opcode2->unit == MU || opcode2->unit == EITHER) + { + if (!flag_warn_suppress_instructionswap) + as_warn (_("Swapping instruction order")); + insn = FM10 | (insn2 << 15) | insn1; + } + else + as_fatal (_("IU instruction may not be in the left container")); + if (opcode1->exec_type & ALONE) + as_warn (_("Instruction in R container is squashed by flow control instruction in L container.")); + /* Advance over dummy fixup */ fx = fx->next; break; - case 3: /* reverse sequential */ - if (opcode2->unit == MU) - as_fatal ("MU instruction may not be in the right container"); - insn = FM10 | (insn1 << 15) | insn2; + + + case PACK_RIGHT_LEFT: + if (opcode2->unit != MU) + insn = FM10 | (insn1 << 15) | insn2; + else if (opcode1->unit == IU || opcode1->unit == EITHER) + { + if (!flag_warn_suppress_instructionswap) + as_warn (_("Swapping instruction order")); + insn = FM01 | (insn2 << 15) | insn1; + } + else + as_fatal (_("MU instruction may not be in the right container")); + if (opcode2->exec_type & ALONE) + as_warn (_("Instruction in R container is squashed by flow control instruction in L container.")); + /* Advance over dummy fixup */ fx = fx->next; break; + + default: - as_fatal("unknown execution type passed to write_2_short()"); + as_fatal (_("unknown execution type passed to write_2_short()")); } - /* printf("INSN: %08x\n",insn); */ + f = frag_more(4); number_to_chars_bigendian (f, insn, 4); + /* Process fixup chains. + Note that the packing code above advanced fx conditionally. + dlindsay@cygnus.com: There's something subtle going on here involving + _dummy_first_bfd_reloc_code_real. This is related to the + difference between BFD_RELOC_D10V_10_PCREL_R and _L, ie whether + a fixup is done in the L or R container. A bug in this code + can pass Plum Hall fine, yet still affect hand-written assembler. */ + for (j=0; j<2; j++) { for (i=0; i < fx->fc; i++) @@ -790,12 +888,6 @@ write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx) if (fx->fix[i].reloc == BFD_RELOC_D10V_18) fx->fix[i].operand |= 4096; - /* - printf("fix_new_exp: where:%x reloc:%d\n ",where,fx->fix[i].operand); - print_expr_1(stdout,&(fx->fix[i].exp)); - printf("\n"); - */ - fix_new_exp (frag_now, where, fx->fix[i].size, @@ -814,9 +906,10 @@ write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx) /* Check 2 instructions and determine if they can be safely */ /* executed in parallel. Returns 1 if they can be. */ static int -parallel_ok (op1, insn1, op2, insn2) +parallel_ok (op1, insn1, op2, insn2, exec_type) struct d10v_opcode *op1, *op2; unsigned long insn1, insn2; + packing_type exec_type; { int i, j, flags, mask, shift, regno; unsigned long ins, mod[2], used[2]; @@ -829,15 +922,26 @@ parallel_ok (op1, insn1, op2, insn2) || (op1->unit == MU && op2->unit == MU)) return 0; - /* The idea here is to create two sets of bitmasks (mod and used) */ - /* which indicate which registers are modified or used by each instruction. */ - /* The operation can only be done in parallel if instruction 1 and instruction 2 */ - /* modify different registers, and neither instruction modifies any registers */ - /* the other is using. Accesses to control registers, PSW, and memory are treated */ - /* as accesses to a single register. So if both instructions write memory or one */ - /* instruction writes memory and the other reads, then they cannot be done in parallel. */ - /* Likewise, if one instruction mucks with the psw and the other reads the PSW */ - /* (which includes C, F0, and F1), then they cannot operate safely in parallel. */ + /* If this is auto parallization, and either instruction is a branch, + don't parallel. */ + if (exec_type == PACK_UNSPEC + && (op1->exec_type & ALONE || op2->exec_type & ALONE)) + return 0; + + /* The idea here is to create two sets of bitmasks (mod and used) + which indicate which registers are modified or used by each + instruction. The operation can only be done in parallel if + instruction 1 and instruction 2 modify different registers, and + the first instruction does not modify registers that the second + is using (The second instruction can modify registers that the + first is using as they are only written back after the first + instruction has completed). Accesses to control registers, PSW, + and memory are treated as accesses to a single register. So if + both instructions write memory or if the first instruction writes + memory and the second reads, then they cannot be done in + parallel. Likewise, if the first instruction mucks with the psw + and the second reads the PSW (which includes C, F0, and F1), then + they cannot operate safely in parallel. */ /* the bitmasks (mod and used) look like this (bit 31 = MSB) */ /* r0-r15 0-15 */ @@ -859,6 +963,9 @@ parallel_ok (op1, insn1, op2, insn2) ins = insn2; } mod[j] = used[j] = 0; + if (op->exec_type & BRANCH_LINK) + mod[j] |= 1 << 13; + for (i = 0; op->operands[i]; i++) { flags = d10v_operands[op->operands[i]].flags; @@ -867,7 +974,7 @@ parallel_ok (op1, insn1, op2, insn2) if (flags & OPERAND_REG) { regno = (ins >> shift) & mask; - if (flags & OPERAND_ACC) + if (flags & (OPERAND_ACC0|OPERAND_ACC1)) regno += 16; else if (flags & OPERAND_CONTROL) /* mvtc or mvfc */ { @@ -876,7 +983,7 @@ parallel_ok (op1, insn1, op2, insn2) else regno = 18; } - else if (flags & OPERAND_FLAG) + else if (flags & (OPERAND_FFLAG|OPERAND_CFLAG)) regno = 19; if ( flags & OPERAND_DEST ) @@ -890,8 +997,20 @@ parallel_ok (op1, insn1, op2, insn2) used[j] |= 1 << regno ; if (flags & OPERAND_EVEN) used[j] |= 1 << (regno + 1); + + /* Auto inc/dec also modifies the register. */ + if (op->operands[i+1] != 0 + && (d10v_operands[op->operands[i+1]].flags + & (OPERAND_PLUS | OPERAND_MINUS)) != 0) + mod[j] |= 1 << regno; } } + else if (flags & OPERAND_ATMINUS) + { + /* SP implicitly used/modified */ + mod[j] |= 1 << 15; + used[j] |= 1 << 15; + } } if (op->exec_type & RMEM) used[j] |= 1 << 20; @@ -904,7 +1023,7 @@ parallel_ok (op1, insn1, op2, insn2) else if (op->exec_type & WCAR) mod[j] |= 1 << 19; } - if ((mod[0] & mod[1]) == 0 && (mod[0] & used[1]) == 0 && (mod[1] & used[0]) == 0) + if ((mod[0] & mod[1]) == 0 && (mod[0] & used[1]) == 0) return 1; return 0; } @@ -919,36 +1038,36 @@ parallel_ok (op1, insn1, op2, insn2) static unsigned long prev_insn; static struct d10v_opcode *prev_opcode = 0; static subsegT prev_subseg; -static segT prev_seg; +static segT prev_seg = 0;; void md_assemble (str) char *str; { - struct d10v_opcode *opcode; - unsigned long insn; - int extype=0; /* execution type; parallel, etc */ - static int etype=0; /* saved extype. used for multiline instructions */ - char *str2; + /* etype is saved extype. for multiline instructions */ + + packing_type extype = PACK_UNSPEC; /* parallel, etc */ - /* printf("md_assemble: str=%s\n",str); */ + struct d10v_opcode * opcode; + unsigned long insn; + char * str2; - if (etype == 0) + if (etype == PACK_UNSPEC) { /* look for the special multiple instruction separators */ str2 = strstr (str, "||"); if (str2) - extype = 1; + extype = PACK_PARALLEL; else { str2 = strstr (str, "->"); if (str2) - extype = 2; + extype = PACK_LEFT_RIGHT; else { str2 = strstr (str, "<-"); if (str2) - extype = 3; + extype = PACK_RIGHT_LEFT; } } /* str2 points to the separator, if one */ @@ -957,14 +1076,13 @@ md_assemble (str) *str2 = 0; /* if two instructions are present and we already have one saved - then first write it out */ - if (prev_opcode) - write_1_short (prev_opcode, prev_insn, fixups->next); + then first write out the save one */ + d10v_cleanup (); /* assemble first instruction and save it */ prev_insn = do_assemble (str, &prev_opcode); if (prev_insn == -1) - as_fatal ("can't find opcode "); + as_fatal (_("can't find opcode ")); fixups = fixups->next; str = str2 + 2; } @@ -973,35 +1091,34 @@ md_assemble (str) insn = do_assemble (str, &opcode); if (insn == -1) { - if (extype) + if (extype != PACK_UNSPEC) { etype = extype; return; } - as_fatal ("can't find opcode "); + as_fatal (_("can't find opcode ")); } - if (etype) + if (etype != PACK_UNSPEC) { extype = etype; - etype = 0; + etype = PACK_UNSPEC; } /* if this is a long instruction, write it and any previous short instruction */ if (opcode->format & LONG_OPCODE) { - if (extype) - as_fatal("Unable to mix instructions as specified"); - if (prev_opcode) - { - write_1_short (prev_opcode, prev_insn, fixups->next); - prev_opcode = NULL; - } + if (extype != PACK_UNSPEC) + as_fatal (_("Unable to mix instructions as specified")); + d10v_cleanup (); write_long (opcode, insn, fixups); prev_opcode = NULL; return; } + if (prev_opcode && prev_seg && ((prev_seg != now_seg) || (prev_subseg != now_subseg))) + d10v_cleanup (); + if (prev_opcode && (write_2_short (prev_opcode, prev_insn, opcode, insn, extype, fixups) == 0)) { /* no instructions saved */ @@ -1009,8 +1126,8 @@ md_assemble (str) } else { - if (extype) - as_fatal("Unable to mix instructions as specified"); + if (extype != PACK_UNSPEC) + as_fatal (_("Unable to mix instructions as specified")); /* save off last instruction so it may be packed on next pass */ prev_opcode = opcode; prev_insn = insn; @@ -1036,31 +1153,29 @@ do_assemble (str, opcode) expressionS myops[6]; unsigned long insn; - /* printf("do_assemble: str=%s\n",str); */ - - /* Drop leading whitespace */ + /* Drop leading whitespace. */ while (*str == ' ') str++; - /* find the opcode end */ + /* Find the opcode end. */ for (op_start = op_end = (unsigned char *) (str); *op_end && nlen < 20 && !is_end_of_line[*op_end] && *op_end != ' '; op_end++) { - name[nlen] = op_start[nlen]; + name[nlen] = tolower (op_start[nlen]); nlen++; } name[nlen] = 0; if (nlen == 0) - return (-1); + return -1; - /* find the first opcode with the proper name */ + /* Find the first opcode with the proper name. */ *opcode = (struct d10v_opcode *)hash_find (d10v_hash, name); if (*opcode == NULL) - as_fatal ("unknown opcode: %s",name); + as_fatal (_("unknown opcode: %s"),name); save = input_line_pointer; input_line_pointer = op_end; @@ -1070,10 +1185,32 @@ do_assemble (str, opcode) input_line_pointer = save; insn = build_insn ((*opcode), myops, 0); - /* printf("sub-insn = %lx\n",insn); */ return (insn); } +/* Find the symbol which has the same name as the register in the given expression. */ +static symbolS * +find_symbol_matching_register (exp) + expressionS * exp; +{ + int i; + + if (exp->X_op != O_register) + return NULL; + + /* Find the name of the register. */ + for (i = d10v_reg_name_cnt (); i--;) + if (d10v_predefined_registers [i].value == exp->X_add_number) + break; + + if (i < 0) + abort (); + + /* Now see if a symbol has been defined with the same name. */ + return symbol_find (d10v_predefined_registers [i].name); +} + + /* find_opcode() gets a pointer to an entry in the opcode table. */ /* It must look at all opcodes with the same name and use the operands */ /* to choose the correct opcode. */ @@ -1083,17 +1220,18 @@ find_opcode (opcode, myops) struct d10v_opcode *opcode; expressionS myops[]; { - int i, match, done, numops; + int i, match, done; struct d10v_opcode *next_opcode; /* get all the operands and save them as expressions */ - numops = get_operands (myops); + get_operands (myops); /* now see if the operand is a fake. If so, find the correct size */ /* instruction, if possible */ if (opcode->format == OPCODE_FAKE) { int opnum = opcode->operands[0]; + int flags; if (myops[opnum].X_op == O_register) { @@ -1103,56 +1241,96 @@ find_opcode (opcode, myops) myops[opnum].X_op_symbol = NULL; } + next_opcode=opcode+1; + + /* If the first operand is supposed to be a register, make sure + we got a valid one. */ + flags = d10v_operands[next_opcode->operands[0]].flags; + if (flags & OPERAND_REG) + { + int X_op = myops[0].X_op; + int num = myops[0].X_add_number; + + if (X_op != O_register + || (num & ~flags + & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1 + | OPERAND_FFLAG | OPERAND_CFLAG | OPERAND_CONTROL))) + { + as_bad (_("bad opcode or operands")); + return 0; + } + } + if (myops[opnum].X_op == O_constant || (myops[opnum].X_op == O_symbol && S_IS_DEFINED(myops[opnum].X_add_symbol) && (S_GET_SEGMENT(myops[opnum].X_add_symbol) == now_seg))) { - next_opcode=opcode+1; for (i=0; opcode->operands[i+1]; i++) { int bits = d10v_operands[next_opcode->operands[opnum]].bits; int flags = d10v_operands[next_opcode->operands[opnum]].flags; if (flags & OPERAND_ADDR) bits += 2; - if (myops[opnum].X_op == O_constant) + + if (myops[opnum].X_op == O_constant) { if (!check_range (myops[opnum].X_add_number, bits, flags)) return next_opcode; } else { - fragS *f; - long value; - /* calculate the current address by running through the previous frags */ - /* and adding our current offset */ - for (value = 0, f = frchain_now->frch_root; f; f = f->fr_next) - value += f->fr_fix; + fragS * sym_frag; + fragS * f; + unsigned long current_position; + unsigned long symbol_position; + unsigned long value; + boolean found_symbol; + + /* Calculate the address of the current instruction + and the address of the symbol. Do this by summing + the offsets of previous frags until we reach the + frag containing the symbol, and the current frag. */ + sym_frag = symbol_get_frag (myops[opnum].X_add_symbol); + found_symbol = false; + + current_position = obstack_next_free (&frchain_now->frch_obstack) - frag_now->fr_literal; + symbol_position = S_GET_VALUE (myops[opnum].X_add_symbol); + + for (f = frchain_now->frch_root; f; f = f->fr_next) + { + current_position += f->fr_fix + f->fr_offset; + + if (f == sym_frag) + found_symbol = true; + + if (! found_symbol) + symbol_position += f->fr_fix + f->fr_offset; + } + value = symbol_position; + if (flags & OPERAND_ADDR) - value = S_GET_VALUE(myops[opnum].X_add_symbol) - value - - (obstack_next_free(&frchain_now->frch_obstack) - frag_now->fr_literal); - else - value = S_GET_VALUE(myops[opnum].X_add_symbol); - - if (myops[opnum].X_add_number == AT_WORD) + value -= current_position; + + if (AT_WORD_P (&myops[opnum])) { if (bits > 4) { bits += 2; - if (!check_range (value, bits, flags)) + if (!check_range (value, bits, flags)) return next_opcode; } } - else if (!check_range (value, bits, flags)) + else if (!check_range (value, bits, flags)) return next_opcode; } next_opcode++; } - as_fatal ("value out of range"); + as_fatal (_("value out of range")); } else { - /* not a constant, so use a long instruction */ + /* not a constant, so use a long instruction */ return opcode+2; } } @@ -1170,53 +1348,82 @@ find_opcode (opcode, myops) int X_op = myops[i].X_op; int num = myops[i].X_add_number; - if (X_op==0) + if (X_op == 0) { - match=0; + match = 0; break; } - if (flags & OPERAND_REG) + if (flags & OPERAND_REG) { - if ((X_op != O_register) || - ((flags & OPERAND_ACC) != (num & OPERAND_ACC)) || - ((flags & OPERAND_FLAG) != (num & OPERAND_FLAG)) || - ((flags & OPERAND_CONTROL) != (num & OPERAND_CONTROL))) + if ((X_op != O_register) + || (num & ~flags + & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1 + | OPERAND_FFLAG | OPERAND_CFLAG + | OPERAND_CONTROL))) { - match=0; + match = 0; break; - } + } } - if (((flags & OPERAND_MINUS) && ((X_op != O_absent) || (num != OPERAND_MINUS))) || - ((flags & OPERAND_PLUS) && ((X_op != O_absent) || (num != OPERAND_PLUS))) || + if (((flags & OPERAND_MINUS) && ((X_op != O_absent) || (num != OPERAND_MINUS))) || + ((flags & OPERAND_PLUS) && ((X_op != O_absent) || (num != OPERAND_PLUS))) || ((flags & OPERAND_ATMINUS) && ((X_op != O_absent) || (num != OPERAND_ATMINUS))) || - ((flags & OPERAND_ATPAR) && ((X_op != O_absent) || (num != OPERAND_ATPAR))) || - ((flags & OPERAND_ATSIGN) && ((X_op != O_absent) || (num != OPERAND_ATSIGN)))) + ((flags & OPERAND_ATPAR) && ((X_op != O_absent) || (num != OPERAND_ATPAR))) || + ((flags & OPERAND_ATSIGN) && ((X_op != O_absent) || ((num != OPERAND_ATSIGN) && (num != OPERAND_ATPAR))))) { - match=0; + match = 0; break; - } + } + + /* Unfortunatly, for the indirect operand in instructions such as + ``ldb r1, @(c,r14)'' this function can be passed X_op == O_register + (because 'c' is a valid register name). However we cannot just + ignore the case when X_op == O_register but flags & OPERAND_REG is + null, so we check to see if a symbol of the same name as the register + exists. If the symbol does exist, then the parser was unable to + distinguish the two cases and we fix things here. (Ref: PR14826) */ + + if (!(flags & OPERAND_REG) && (X_op == O_register)) + { + symbolS * sym; + + sym = find_symbol_matching_register (& myops[i]); + + if (sym != NULL) + { + myops [i].X_op == X_op == O_symbol; + myops [i].X_add_symbol = sym; + } + else + as_bad + (_("illegal operand - register name found where none expected")); + } } - /* we're only done if the operands matched so far AND there - are no more to check */ - if (match && myops[i].X_op==0) + + /* We're only done if the operands matched so far AND there + are no more to check. */ + if (match && myops[i].X_op == 0) break; else match = 0; - next_opcode = opcode+1; + next_opcode = opcode + 1; + if (next_opcode->opcode == 0) break; - if (strcmp(next_opcode->name, opcode->name)) + + if (strcmp (next_opcode->name, opcode->name)) break; + opcode = next_opcode; } } if (!match) { - as_bad ("bad opcode or operands"); + as_bad (_("bad opcode or operands")); return (0); } @@ -1227,7 +1434,7 @@ find_opcode (opcode, myops) { if ((d10v_operands[opcode->operands[i]].flags & OPERAND_EVEN) && (myops[i].X_add_number & 1)) - as_fatal("Register number must be EVEN"); + as_fatal (_("Register number must be EVEN")); if (myops[i].X_op == O_register) { if (!(d10v_operands[opcode->operands[i]].flags & OPERAND_REG)) @@ -1251,18 +1458,24 @@ tc_gen_reloc (seg, fixp) fixS *fixp; { arelent *reloc; - reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent)); - reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym; + reloc = (arelent *) xmalloc (sizeof (arelent)); + reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); + *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); if (reloc->howto == (reloc_howto_type *) NULL) { as_bad_where (fixp->fx_file, fixp->fx_line, - "reloc %d not supported by object file format", (int)fixp->fx_r_type); + _("reloc %d not supported by object file format"), (int)fixp->fx_r_type); return NULL; } + + if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT + || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) + reloc->address = fixp->fx_offset; + reloc->addend = fixp->fx_addnumber; - /* printf("tc_gen_reloc: addr=%x addend=%x\n", reloc->address, reloc->addend); */ + return reloc; } @@ -1280,9 +1493,9 @@ md_pcrel_from_section (fixp, sec) fixS *fixp; segT sec; { - if (fixp->fx_addsy != (symbolS *)NULL && !S_IS_DEFINED (fixp->fx_addsy)) + if (fixp->fx_addsy != (symbolS *)NULL && (!S_IS_DEFINED (fixp->fx_addsy) || + (S_GET_SEGMENT (fixp->fx_addsy) != sec))) return 0; - /* printf("pcrel_from_section: %x\n", fixp->fx_frag->fr_address + fixp->fx_where); */ return fixp->fx_frag->fr_address + fixp->fx_where; } @@ -1316,13 +1529,11 @@ md_apply_fix3 (fixp, valuep, seg) { /* We don't actually support subtracting a symbol. */ as_bad_where (fixp->fx_file, fixp->fx_line, - "expression too complex"); + _("expression too complex")); } } } - - /* printf("md_apply_fix: value=0x%x type=0x%x where=0x%x size=%d line=%d\n", value, fixp->fx_r_type,fixp->fx_where,fixp->fx_size, fixp->fx_line); */ - + op_type = fixp->fx_r_type; if (op_type & 2048) { @@ -1354,14 +1565,23 @@ md_apply_fix3 (fixp, valuep, seg) case BFD_RELOC_D10V_18_PCREL: case BFD_RELOC_D10V_18: /* instruction addresses are always right-shifted by 2 */ - value >>= 2; + value >>= AT_WORD_RIGHT_SHIFT; if (fixp->fx_size == 2) bfd_putb16 ((bfd_vma) value, (unsigned char *) where); else { - /* printf(" insn=%x value=%x where=%x pcrel=%x\n",insn,value,fixp->fx_where,fixp->fx_pcrel); */ + struct d10v_opcode *rep, *repi; + + rep = (struct d10v_opcode *) hash_find (d10v_hash, "rep"); + repi = (struct d10v_opcode *) hash_find (d10v_hash, "repi"); + if ((insn & FM11) == FM11 + && ((repi != NULL && (insn & repi->mask) == repi->opcode) + || (rep != NULL && (insn & rep->mask) == rep->opcode)) + && value < 4) + as_fatal + (_("line %d: rep or repi must include at least 4 instructions"), + fixp->fx_line); insn = d10v_insert_operand (insn, op_type, (offsetT)value, left, fixp); - /* printf(" new insn=%x\n",insn); */ bfd_putb32 ((bfd_vma) insn, (unsigned char *) where); } break; @@ -1371,29 +1591,36 @@ md_apply_fix3 (fixp, valuep, seg) case BFD_RELOC_16: bfd_putb16 ((bfd_vma) value, (unsigned char *) where); break; + + case BFD_RELOC_VTABLE_INHERIT: + case BFD_RELOC_VTABLE_ENTRY: + fixp->fx_done = 0; + return 1; + default: - as_fatal ("line %d: unknown relocation type: 0x%x",fixp->fx_line,fixp->fx_r_type); + as_fatal (_("line %d: unknown relocation type: 0x%x"),fixp->fx_line,fixp->fx_r_type); } return 0; } - /* d10v_cleanup() is called after the assembler has finished parsing the input file or after a label is defined. Because the D10V assembler sometimes saves short instructions to see if it can package them with the next instruction, there may - be a short instruction that still needs written. */ + be a short instruction that still needs written. + NOTE: accesses a global, etype. + NOTE: invoked by various macros such as md_cleanup: see. */ int -d10v_cleanup (done) - int done; +d10v_cleanup () { segT seg; subsegT subseg; - if ( prev_opcode && (done || (now_seg == prev_seg) && (now_subseg == prev_subseg))) + if (prev_opcode && etype == PACK_UNSPEC) { seg = now_seg; subseg = now_subseg; - subseg_set (prev_seg, prev_subseg); + if (prev_seg) + subseg_set (prev_seg, prev_subseg); write_1_short (prev_opcode, prev_insn, fixups->next); subseg_set (seg, subseg); prev_opcode = NULL; @@ -1454,10 +1681,42 @@ void md_operand (expressionP) expressionS *expressionP; { - if (*input_line_pointer == '#') + if (*input_line_pointer == '#' && ! do_not_ignore_hash) { input_line_pointer++; expression (expressionP); } } +boolean +d10v_fix_adjustable (fixP) + fixS *fixP; +{ + + if (fixP->fx_addsy == NULL) + return 1; + + /* Prevent all adjustments to global symbols. */ + if (S_IS_EXTERN (fixP->fx_addsy)) + return 0; + if (S_IS_WEAK (fixP->fx_addsy)) + return 0; + + /* We need the symbol name for the VTABLE entries */ + if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT + || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) + return 0; + + return 1; +} + +int +d10v_force_relocation (fixp) + fixS *fixp; +{ + if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT + || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) + return 1; + + return 0; +}