X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=gas%2Fdoc%2Fc-i386.texi;h=c4a39670146b6e9882d080333c2038ade21f4d00;hb=408520bcaa874edb0e37506e8559b2e4194dca05;hp=1dd99f91bb0e97f220c17cacedbe5c4f71cfe8d1;hpb=ae531041c7c5956672342f89c486a011c84f027f;p=binutils-gdb.git

diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 1dd99f91bb0..c4a39670146 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -1,4 +1,4 @@
-@c Copyright (C) 1991-2020 Free Software Foundation, Inc.
+@c Copyright (C) 1991-2022 Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 @c man end
@@ -110,8 +110,6 @@ processor names are recognized:
 @code{core},
 @code{core2},
 @code{corei7},
-@code{l1om},
-@code{k1om},
 @code{iamcu},
 @code{k6},
 @code{k6_2},
@@ -125,6 +123,7 @@ processor names are recognized:
 @code{bdver4},
 @code{znver1},
 @code{znver2},
+@code{znver3},
 @code{btver1},
 @code{btver2},
 @code{generic32} and
@@ -187,6 +186,13 @@ accept various extension mnemonics.  For example,
 @code{movdiri},
 @code{movdir64b},
 @code{enqcmd},
+@code{serialize},
+@code{tsxldtrk},
+@code{kl},
+@code{nokl},
+@code{widekl},
+@code{nowidekl},
+@code{hreset},
 @code{avx512f},
 @code{avx512cd},
 @code{avx512er},
@@ -202,7 +208,11 @@ accept various extension mnemonics.  For example,
 @code{avx512_vbmi2},
 @code{avx512_vnni},
 @code{avx512_bitalg},
+@code{avx512_vp2intersect},
+@code{tdx},
 @code{avx512_bf16},
+@code{avx_vnni},
+@code{avx512_fp16},
 @code{noavx512f},
 @code{noavx512cd},
 @code{noavx512er},
@@ -219,8 +229,21 @@ accept various extension mnemonics.  For example,
 @code{noavx512_vnni},
 @code{noavx512_bitalg},
 @code{noavx512_vp2intersect},
+@code{notdx},
 @code{noavx512_bf16},
+@code{noavx_vnni},
+@code{noavx512_fp16},
 @code{noenqcmd},
+@code{noserialize},
+@code{notsxldtrk},
+@code{amx_int8},
+@code{noamx_int8},
+@code{amx_bf16},
+@code{noamx_bf16},
+@code{amx_tile},
+@code{noamx_tile},
+@code{nouintr},
+@code{nohreset},
 @code{vmx},
 @code{vmfunc},
 @code{smx},
@@ -248,6 +271,7 @@ accept various extension mnemonics.  For example,
 @code{wbnoinvd},
 @code{pconfig},
 @code{waitpkg},
+@code{uintr},
 @code{cldemote},
 @code{rdpru},
 @code{mcommit},
@@ -262,6 +286,9 @@ accept various extension mnemonics.  For example,
 @code{3dnowa},
 @code{sse4a},
 @code{sse5},
+@code{snp},
+@code{invlpgb},
+@code{tlbsync},
 @code{svme} and
 @code{padlock}.
 Note that rather than extending a basic instruction set, the extension
@@ -287,6 +314,12 @@ Valid @var{CPU} values are identical to the processor list of
 This option specifies that the assembler should encode SSE instructions
 with VEX prefix.
 
+@cindex @samp{-muse-unaligned-vector-move} option, i386
+@cindex @samp{-muse-unaligned-vector-move} option, x86-64
+@item -muse-unaligned-vector-move
+This option specifies that the assembler should encode aligned vector
+move as unaligned vector move.
+
 @cindex @samp{-msse-check=} option, i386
 @cindex @samp{-msse-check=} option, x86-64
 @item -msse-check=@var{none}
@@ -386,9 +419,10 @@ with default visibility can be preempted.  The resulting code is
 slightly bigger.  This option only affects the handling of branch
 instructions.
 
+@cindex @samp{-mbig-obj} option, i386
 @cindex @samp{-mbig-obj} option, x86-64
 @item -mbig-obj
-On x86-64 PE/COFF target this option forces the use of big object file
+On PE/COFF target this option forces the use of big object file
 format, which allows more than 32768 sections.
 
 @cindex @samp{-momit-lock-prefix=} option, i386
@@ -480,12 +514,14 @@ lfence, which is the default.
 @item -mlfence-before-indirect-branch=@var{register}
 @itemx -mlfence-before-indirect-branch=@var{memory}
 These options control whether the assembler should generate lfence
-after indirect near branch instructions.
+before indirect near branch instructions.
 @option{-mlfence-before-indirect-branch=@var{all}} will generate lfence
-after indirect near branch via register and issue a warning before
+before indirect near branch via register and issue a warning before
 indirect near branch via memory.
+It also implicitly sets @option{-mlfence-before-ret=@var{shl}} when
+there's no explicit @option{-mlfence-before-ret=}.
 @option{-mlfence-before-indirect-branch=@var{register}} will generate
-lfence after indirect near branch via register.
+lfence before indirect near branch via register.
 @option{-mlfence-before-indirect-branch=@var{memory}} will issue a
 warning before indirect near branch via memory.
 @option{-mlfence-before-indirect-branch=@var{none}} will not generate
@@ -497,15 +533,17 @@ after loading branch target register.
 @cindex @samp{-mlfence-before-ret=} option, i386
 @cindex @samp{-mlfence-before-ret=} option, x86-64
 @item -mlfence-before-ret=@var{none}
+@item -mlfence-before-ret=@var{shl}
 @item -mlfence-before-ret=@var{or}
+@item -mlfence-before-ret=@var{yes}
 @itemx -mlfence-before-ret=@var{not}
 These options control whether the assembler should generate lfence
 before ret.  @option{-mlfence-before-ret=@var{or}} will generate
 generate or instruction with lfence.
-@option{-mlfence-before-ret=@var{not}} will generate not instruction
-with lfence.
-@option{-mlfence-before-ret=@var{none}} will not generate lfence,
-which is the default.
+@option{-mlfence-before-ret=@var{shl/yes}} will generate shl instruction
+with lfence. @option{-mlfence-before-ret=@var{not}} will generate not
+instruction with lfence. @option{-mlfence-before-ret=@var{none}} will not
+generate lfence, which is the default.
 
 @cindex @samp{-mx86-used-note=} option, i386
 @cindex @samp{-mx86-used-note=} option, x86-64
@@ -808,6 +846,9 @@ Different encoding options can be specified via pseudo prefixes:
 @item
 @samp{@{disp32@}} -- prefer 32-bit displacement.
 
+@item
+@samp{@{disp16@}} -- prefer 16-bit displacement.
+
 @item
 @samp{@{load@}} -- prefer load-form instruction.
 
@@ -832,6 +873,10 @@ prefix which generates REX prefix unconditionally.
 @samp{@{nooptimize@}} -- disable instruction size optimization.
 @end itemize
 
+Mnemonics of Intel VNNI instructions are encoded with the EVEX prefix
+by default.  The pseudo @samp{@{vex@}} prefix can be used to encode
+mnemonics of Intel VNNI instructions with the VEX prefix.
+
 @cindex conversion instructions, i386
 @cindex i386 conversion instructions
 @cindex conversion instructions, x86-64
@@ -913,7 +958,7 @@ The Intel-syntax extension instructions
 
 @noindent
 are called @samp{movsbw/movsxb/movsx}, @samp{movsbl/movsxb/movsx},
-@samp{movsbq/movsb/movsx}, @samp{movswl/movsxw}, @samp{movswq/movsxw},
+@samp{movsbq/movsxb/movsx}, @samp{movswl/movsxw}, @samp{movswq/movsxw},
 @samp{movslq/movsxl}, @samp{movzbw/movzxb/movzx},
 @samp{movzbl/movzxb/movzx}, @samp{movzbq/movzxb/movzx},
 @samp{movzwl/movzxw} and @samp{movzwq/movzxw} in AT&T syntax.
@@ -1044,16 +1089,6 @@ available in 32-bit mode).  The bottom 128 bits are overlaid with the
 
 @end itemize
 
-The AVX2 extensions made in 64-bit mode more registers available:
-
-@itemize @bullet
-
-@item
-the 16 128-bit registers @samp{%xmm16}--@samp{%xmm31} and the 16 256-bit
-registers @samp{%ymm16}--@samp{%ymm31}.
-
-@end itemize
-
 The AVX512 extensions added the following registers:
 
 @itemize @bullet
@@ -1282,18 +1317,23 @@ data type.  Constructors build these data types into memory.
 @cindex @code{single} directive, i386
 @cindex @code{double} directive, i386
 @cindex @code{tfloat} directive, i386
+@cindex @code{hfloat} directive, i386
+@cindex @code{bfloat16} directive, i386
 @cindex @code{float} directive, x86-64
 @cindex @code{single} directive, x86-64
 @cindex @code{double} directive, x86-64
 @cindex @code{tfloat} directive, x86-64
+@cindex @code{hfloat} directive, x86-64
+@cindex @code{bfloat16} directive, x86-64
 @itemize @bullet
 @item
 Floating point constructors are @samp{.float} or @samp{.single},
-@samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats.
-These correspond to instruction mnemonic suffixes @samp{s}, @samp{l},
-and @samp{t}. @samp{t} stands for 80-bit (ten byte) real.  The 80387
-only supports this format via the @samp{fldt} (load 80-bit real to stack
-top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
+@samp{.double}, @samp{.tfloat}, @samp{.hfloat}, and @samp{.bfloat16} for 32-,
+64-, 80-, and 16-bit (two flavors) formats respectively.  The former three
+correspond to instruction mnemonic suffixes @samp{s}, @samp{l}, and @samp{t}.
+@samp{t} stands for 80-bit (ten byte) real.  The 80387 only supports this
+format via the @samp{fldt} (load 80-bit real to stack top) and @samp{fstpt}
+(store 80-bit real and pop stack) instructions.
 
 @cindex @code{word} directive, i386
 @cindex @code{long} directive, i386
@@ -1306,7 +1346,7 @@ top) and @samp{fstpt} (store 80-bit real and pop stack) instructions.
 @item
 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
 @samp{.quad} for the 16-, 32-, and 64-bit integer formats.  The
-corresponding instruction mnemonic suffixes are @samp{s} (single),
+corresponding instruction mnemonic suffixes are @samp{s} (short),
 @samp{l} (long), and @samp{q} (quad).  As with the 80-bit real format,
 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
@@ -1464,15 +1504,16 @@ directive enables a warning when gas detects an instruction that is not
 supported on the CPU specified.  The choices for @var{cpu_type} are:
 
 @multitable @columnfractions .20 .20 .20 .20
+@item @samp{default} @tab @samp{push} @tab @samp{pop}
 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
-@item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @tab @samp{iamcu}
+@item @samp{corei7} @tab @samp{iamcu}
 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
-@item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{btver1}
-@item @samp{btver2} @tab @samp{generic32} @tab @samp{generic64}
+@item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{znver3}
+@item @samp{btver1} @tab @samp{btver2} @tab @samp{generic32} @tab @samp{generic64}
 @item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx}
 @item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} @tab @samp{.sse4a}
 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
@@ -1490,15 +1531,19 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
 @item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
 @item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect}
-@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt}
+@item @samp{.tdx} @tab @samp{.avx_vnni}  @tab @samp{.avx512_fp16}
+@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
 @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
 @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
-@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd}
+@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
+@item @samp{.amx_int8} @tab @samp{.amx_bf16} @tab @samp{.amx_tile}
+@item @samp{.kl} @tab @samp{.widekl} @tab @samp{.uintr} @tab @samp{.hreset}
 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme}
 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru}
-@item @samp{.mcommit} @tab @samp{.sev_es}
+@item @samp{.mcommit} @tab @samp{.sev_es} @tab @samp{.snp} @tab @samp{.invlpgb}
+@item @samp{.tlbsync}
 @end multitable
 
 Apart from the warning, there are only two other effects on