X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=gcc%2Fconfig%2Fi386%2Fi386.md;h=0db0222af793e022f81954c63498b645aa813d08;hb=18ae1560d19ed5e9e87e3dc4712ee917755374b2;hp=91a830104a4d1eec8c39b0c8625bc17ff91fda75;hpb=c4ab64c640c78b4800b9b1917835c9b58ce16027;p=gcc.git diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 91a830104a4..0db0222af79 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -1,6 +1,6 @@ ;; GCC machine description for IA-32 and x86-64. ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000, -;; 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 +;; 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 ;; Free Software Foundation, Inc. ;; Mostly by William Schelter. ;; x86_64 support added by Jan Hubicka @@ -38,6 +38,7 @@ ;; Z -- likewise, with special suffixes for x87 instructions. ;; * -- print a star (in certain assembler syntax) ;; A -- print an absolute memory reference. +;; E -- print address with DImode register names if TARGET_64BIT. ;; w -- print the operand as if it's a "word" (HImode) even if it isn't. ;; s -- print a shift double count, followed by the assemblers argument ;; delimiter. @@ -60,9 +61,9 @@ ;; Y -- print condition for XOP pcom* instruction. ;; + -- print a branch hint as 'cs' or 'ds' prefix ;; ; -- print a semicolon (after prefixes due to bug in older gas). +;; ~ -- print "i" if TARGET_AVX2, "f" otherwise. ;; @ -- print a segment register of thread base pointer load - -;; UNSPEC usage: +;; ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode (define_c_enum "unspec" [ ;; Relocation specifiers @@ -108,28 +109,19 @@ UNSPEC_LD_MPIC ; load_macho_picbase UNSPEC_TRUNC_NOOP UNSPEC_DIV_ALREADY_SPLIT + UNSPEC_MS_TO_SYSV_CALL UNSPEC_CALL_NEEDS_VZEROUPPER UNSPEC_PAUSE + UNSPEC_LEA_ADDR + UNSPEC_XBEGIN_ABORT ;; For SSE/MMX support: UNSPEC_FIX_NOTRUNC UNSPEC_MASKMOV UNSPEC_MOVMSK - UNSPEC_MOVNT - UNSPEC_MOVU UNSPEC_RCP UNSPEC_RSQRT - UNSPEC_SFENCE - UNSPEC_PFRCP - UNSPEC_PFRCPIT1 - UNSPEC_PFRCPIT2 - UNSPEC_PFRSQRT - UNSPEC_PFRSQIT1 - UNSPEC_MFENCE - UNSPEC_LFENCE UNSPEC_PSADBW - UNSPEC_LDDQU - UNSPEC_MS_TO_SYSV_CALL ;; Generic math support UNSPEC_COPYSIGN @@ -177,74 +169,18 @@ UNSPEC_SP_TLS_SET UNSPEC_SP_TLS_TEST - ;; SSSE3 - UNSPEC_PSHUFB - UNSPEC_PSIGN - UNSPEC_PALIGNR - - ;; For SSE4A support - UNSPEC_EXTRQI - UNSPEC_EXTRQ - UNSPEC_INSERTQI - UNSPEC_INSERTQ - - ;; For SSE4.1 support - UNSPEC_BLENDV - UNSPEC_INSERTPS - UNSPEC_DP - UNSPEC_MOVNTDQA - UNSPEC_MPSADBW - UNSPEC_PHMINPOSUW - UNSPEC_PTEST + ;; For ROUND support UNSPEC_ROUND - ;; For SSE4.2 support + ;; For CRC32 support UNSPEC_CRC32 - UNSPEC_PCMPESTR - UNSPEC_PCMPISTR - - ;; For FMA4 support - UNSPEC_FMADDSUB - UNSPEC_XOP_UNSIGNED_CMP - UNSPEC_XOP_TRUEFALSE - UNSPEC_XOP_PERMUTE - UNSPEC_FRCZ - - ;; For AES support - UNSPEC_AESENC - UNSPEC_AESENCLAST - UNSPEC_AESDEC - UNSPEC_AESDECLAST - UNSPEC_AESIMC - UNSPEC_AESKEYGENASSIST - - ;; For PCLMUL support - UNSPEC_PCLMUL - - ;; For AVX support - UNSPEC_PCMP - UNSPEC_VPERMIL - UNSPEC_VPERMIL2 - UNSPEC_VPERMIL2F128 - UNSPEC_CAST - UNSPEC_VTESTP - UNSPEC_VCVTPH2PS - UNSPEC_VCVTPS2PH - - ;; For AVX2 support - UNSPEC_VPERMSI - UNSPEC_VPERMDF - UNSPEC_VPERMSF - UNSPEC_VPERMTI - UNSPEC_GATHER - UNSPEC_VSIBADDR - - ;; For BMI support - UNSPEC_BEXTR ;; For RDRAND support UNSPEC_RDRAND + ;; For BMI support + UNSPEC_BEXTR + ;; For BMI2 support UNSPEC_PDEP UNSPEC_PEXT @@ -254,22 +190,11 @@ UNSPECV_BLOCKAGE UNSPECV_STACK_PROBE UNSPECV_PROBE_STACK_RANGE - UNSPECV_EMMS - UNSPECV_LDMXCSR - UNSPECV_STMXCSR - UNSPECV_FEMMS - UNSPECV_CLFLUSH UNSPECV_ALIGN - UNSPECV_MONITOR - UNSPECV_MWAIT - UNSPECV_CMPXCHG - UNSPECV_XCHG - UNSPECV_LOCK UNSPECV_PROLOGUE_USE + UNSPECV_SPLIT_STACK_RETURN UNSPECV_CLD UNSPECV_NOPS - UNSPECV_VZEROALL - UNSPECV_VZEROUPPER UNSPECV_RDTSC UNSPECV_RDTSCP UNSPECV_RDPMC @@ -281,7 +206,12 @@ UNSPECV_RDGSBASE UNSPECV_WRFSBASE UNSPECV_WRGSBASE - UNSPECV_SPLIT_STACK_RETURN + + ;; For RTM support + UNSPECV_XBEGIN + UNSPECV_XEND + UNSPECV_XABORT + UNSPECV_XTEST ]) ;; Constants to represent rounding modes in the ROUND instruction @@ -432,11 +362,11 @@ (eq_attr "type" "imov,test") (symbol_ref "ix86_attr_length_immediate_default (insn, false)") (eq_attr "type" "call") - (if_then_else (match_operand 0 "constant_call_address_operand" "") + (if_then_else (match_operand 0 "constant_call_address_operand") (const_int 4) (const_int 0)) (eq_attr "type" "callv") - (if_then_else (match_operand 1 "constant_call_address_operand" "") + (if_then_else (match_operand 1 "constant_call_address_operand") (const_int 4) (const_int 0)) ;; We don't know the size before shorten_branches. Expect @@ -452,10 +382,10 @@ (cond [(eq_attr "type" "str,other,multi,fxch") (const_int 0) (and (eq_attr "type" "call") - (match_operand 0 "constant_call_address_operand" "")) + (match_operand 0 "constant_call_address_operand")) (const_int 0) (and (eq_attr "type" "callv") - (match_operand 1 "constant_call_address_operand" "")) + (match_operand 1 "constant_call_address_operand")) (const_int 0) ] (symbol_ref "ix86_attr_length_address_default (insn)"))) @@ -502,7 +432,7 @@ (match_test "x86_extended_reg_mentioned_p (insn)") (const_int 1) (and (eq_attr "type" "imovx") - (match_operand:QI 1 "ext_QIreg_operand" "")) + (match_operand:QI 1 "ext_QIreg_operand")) (const_int 1) ] (const_int 0))) @@ -550,32 +480,32 @@ (const_int 0) (and (eq_attr "type" "incdec") (and (not (match_test "TARGET_64BIT")) - (ior (match_operand:SI 1 "register_operand" "") - (match_operand:HI 1 "register_operand" "")))) + (ior (match_operand:SI 1 "register_operand") + (match_operand:HI 1 "register_operand")))) (const_int 0) (and (eq_attr "type" "push") - (not (match_operand 1 "memory_operand" ""))) + (not (match_operand 1 "memory_operand"))) (const_int 0) (and (eq_attr "type" "pop") - (not (match_operand 0 "memory_operand" ""))) + (not (match_operand 0 "memory_operand"))) (const_int 0) (and (eq_attr "type" "imov") (and (not (eq_attr "mode" "DI")) - (ior (and (match_operand 0 "register_operand" "") - (match_operand 1 "immediate_operand" "")) - (ior (and (match_operand 0 "ax_reg_operand" "") - (match_operand 1 "memory_displacement_only_operand" "")) - (and (match_operand 0 "memory_displacement_only_operand" "") - (match_operand 1 "ax_reg_operand" "")))))) + (ior (and (match_operand 0 "register_operand") + (match_operand 1 "immediate_operand")) + (ior (and (match_operand 0 "ax_reg_operand") + (match_operand 1 "memory_displacement_only_operand")) + (and (match_operand 0 "memory_displacement_only_operand") + (match_operand 1 "ax_reg_operand")))))) (const_int 0) (and (eq_attr "type" "call") - (match_operand 0 "constant_call_address_operand" "")) + (match_operand 0 "constant_call_address_operand")) (const_int 0) (and (eq_attr "type" "callv") - (match_operand 1 "constant_call_address_operand" "")) + (match_operand 1 "constant_call_address_operand")) (const_int 0) (and (eq_attr "type" "alu,alu1,icmp,test") - (match_operand 0 "ax_reg_operand" "")) + (match_operand 0 "ax_reg_operand")) (symbol_ref "(get_attr_length_immediate (insn) <= (get_attr_mode (insn) != MODE_QI))") ] (const_int 1))) @@ -624,43 +554,43 @@ (eq_attr "type" "frndint") (const_string "load") (eq_attr "type" "push") - (if_then_else (match_operand 1 "memory_operand" "") + (if_then_else (match_operand 1 "memory_operand") (const_string "both") (const_string "store")) (eq_attr "type" "pop") - (if_then_else (match_operand 0 "memory_operand" "") + (if_then_else (match_operand 0 "memory_operand") (const_string "both") (const_string "load")) (eq_attr "type" "setcc") - (if_then_else (match_operand 0 "memory_operand" "") + (if_then_else (match_operand 0 "memory_operand") (const_string "store") (const_string "none")) (eq_attr "type" "icmp,test,ssecmp,ssecomi,mmxcmp,fcmp") - (if_then_else (ior (match_operand 0 "memory_operand" "") - (match_operand 1 "memory_operand" "")) + (if_then_else (ior (match_operand 0 "memory_operand") + (match_operand 1 "memory_operand")) (const_string "load") (const_string "none")) (eq_attr "type" "ibr") - (if_then_else (match_operand 0 "memory_operand" "") + (if_then_else (match_operand 0 "memory_operand") (const_string "load") (const_string "none")) (eq_attr "type" "call") - (if_then_else (match_operand 0 "constant_call_address_operand" "") + (if_then_else (match_operand 0 "constant_call_address_operand") (const_string "none") (const_string "load")) (eq_attr "type" "callv") - (if_then_else (match_operand 1 "constant_call_address_operand" "") + (if_then_else (match_operand 1 "constant_call_address_operand") (const_string "none") (const_string "load")) (and (eq_attr "type" "alu1,negnot,ishift1,sselog1") - (match_operand 1 "memory_operand" "")) + (match_operand 1 "memory_operand")) (const_string "both") - (and (match_operand 0 "memory_operand" "") - (match_operand 1 "memory_operand" "")) + (and (match_operand 0 "memory_operand") + (match_operand 1 "memory_operand")) (const_string "both") - (match_operand 0 "memory_operand" "") + (match_operand 0 "memory_operand") (const_string "store") - (match_operand 1 "memory_operand" "") + (match_operand 1 "memory_operand") (const_string "load") (and (eq_attr "type" "!alu1,negnot,ishift1, @@ -668,10 +598,10 @@ fmov,fcmp,fsgn, sse,ssemov,ssecmp,ssecomi,ssecvt,ssecvt1,sseicvt,sselog1, sseiadd1,mmx,mmxmov,mmxcmp,mmxcvt") - (match_operand 2 "memory_operand" "")) + (match_operand 2 "memory_operand")) (const_string "load") (and (eq_attr "type" "icmov,ssemuladd,sse4arg") - (match_operand 3 "memory_operand" "")) + (match_operand 3 "memory_operand")) (const_string "load") ] (const_string "none"))) @@ -682,12 +612,12 @@ (cond [(eq_attr "type" "other,multi") (const_string "unknown") (and (eq_attr "type" "icmp,test,imov,alu1,ishift1,rotate1") - (and (match_operand 0 "memory_displacement_operand" "") - (match_operand 1 "immediate_operand" ""))) + (and (match_operand 0 "memory_displacement_operand") + (match_operand 1 "immediate_operand"))) (const_string "true") (and (eq_attr "type" "alu,ishift,ishiftx,rotate,rotatex,imul,idiv") - (and (match_operand 0 "memory_displacement_operand" "") - (match_operand 2 "immediate_operand" ""))) + (and (match_operand 0 "memory_displacement_operand") + (match_operand 2 "immediate_operand"))) (const_string "true") ] (const_string "false"))) @@ -772,6 +702,9 @@ ;; Base name for insn mnemonic. (define_code_attr logic [(and "and") (ior "or") (xor "xor")]) +;; Mapping of logic-shift operators +(define_code_iterator any_lshift [ashift lshiftrt]) + ;; Mapping of shift-right operators (define_code_iterator any_shiftrt [lshiftrt ashiftrt]) @@ -781,6 +714,7 @@ ;; Base name for insn mnemonic. (define_code_attr shift [(ashift "sll") (lshiftrt "shr") (ashiftrt "sar")]) +(define_code_attr vshift [(ashift "sll") (lshiftrt "srl") (ashiftrt "sra")]) ;; Mapping of rotate operators (define_code_iterator any_rotate [rotate rotatert]) @@ -969,6 +903,11 @@ ;; pointer-sized quantities. Exactly one of the two alternatives will match. (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) +;; This mode iterator allows :W to be used for patterns that operate on +;; word_mode sized quantities. +(define_mode_iterator W + [(SI "word_mode == SImode") (DI "word_mode == DImode")]) + ;; This mode iterator allows :PTR to be used for patterns that operate on ;; ptr_mode sized quantities. (define_mode_iterator PTR @@ -996,12 +935,12 @@ (define_expand "cbranch4" [(set (reg:CC FLAGS_REG) - (compare:CC (match_operand:SDWIM 1 "nonimmediate_operand" "") - (match_operand:SDWIM 2 "" ""))) + (compare:CC (match_operand:SDWIM 1 "nonimmediate_operand") + (match_operand:SDWIM 2 ""))) (set (pc) (if_then_else (match_operator 0 "ordered_comparison_operator" [(reg:CC FLAGS_REG) (const_int 0)]) - (label_ref (match_operand 3 "" "")) + (label_ref (match_operand 3)) (pc)))] "" { @@ -1014,9 +953,9 @@ (define_expand "cstore4" [(set (reg:CC FLAGS_REG) - (compare:CC (match_operand:SWIM 2 "nonimmediate_operand" "") - (match_operand:SWIM 3 "" ""))) - (set (match_operand:QI 0 "register_operand" "") + (compare:CC (match_operand:SWIM 2 "nonimmediate_operand") + (match_operand:SWIM 3 ""))) + (set (match_operand:QI 0 "register_operand") (match_operator 1 "ordered_comparison_operator" [(reg:CC FLAGS_REG) (const_int 0)]))] "" @@ -1030,13 +969,13 @@ (define_expand "cmp_1" [(set (reg:CC FLAGS_REG) - (compare:CC (match_operand:SWI48 0 "nonimmediate_operand" "") - (match_operand:SWI48 1 "" "")))]) + (compare:CC (match_operand:SWI48 0 "nonimmediate_operand") + (match_operand:SWI48 1 "")))]) (define_insn "*cmp_ccno_1" [(set (reg FLAGS_REG) (compare (match_operand:SWI 0 "nonimmediate_operand" ",?m") - (match_operand:SWI 1 "const0_operand" "")))] + (match_operand:SWI 1 "const0_operand")))] "ix86_match_ccmode (insn, CCNOmode)" "@ test{}\t%0, %0 @@ -1101,7 +1040,7 @@ (match_operand 0 "ext_register_operand" "Q") (const_int 8) (const_int 8)) 0) - (match_operand:QI 1 "const0_operand" "")))] + (match_operand:QI 1 "const0_operand")))] "ix86_match_ccmode (insn, CCNOmode)" "test{b}\t%h0, %h0" [(set_attr "type" "test") @@ -1113,10 +1052,10 @@ (compare:CC (subreg:QI (zero_extract:SI - (match_operand 0 "ext_register_operand" "") + (match_operand 0 "ext_register_operand") (const_int 8) (const_int 8)) 0) - (match_operand:QI 1 "immediate_operand" "")))]) + (match_operand:QI 1 "immediate_operand")))]) (define_insn "*cmpqi_ext_3_insn" [(set (reg FLAGS_REG) @@ -1173,13 +1112,13 @@ (define_expand "cbranchxf4" [(set (reg:CC FLAGS_REG) - (compare:CC (match_operand:XF 1 "nonmemory_operand" "") - (match_operand:XF 2 "nonmemory_operand" ""))) + (compare:CC (match_operand:XF 1 "nonmemory_operand") + (match_operand:XF 2 "nonmemory_operand"))) (set (pc) (if_then_else (match_operator 0 "ix86_fp_comparison_operator" [(reg:CC FLAGS_REG) (const_int 0)]) - (label_ref (match_operand 3 "" "")) + (label_ref (match_operand 3)) (pc)))] "TARGET_80387" { @@ -1190,9 +1129,9 @@ (define_expand "cstorexf4" [(set (reg:CC FLAGS_REG) - (compare:CC (match_operand:XF 2 "nonmemory_operand" "") - (match_operand:XF 3 "nonmemory_operand" ""))) - (set (match_operand:QI 0 "register_operand" "") + (compare:CC (match_operand:XF 2 "nonmemory_operand") + (match_operand:XF 3 "nonmemory_operand"))) + (set (match_operand:QI 0 "register_operand") (match_operator 1 "ix86_fp_comparison_operator" [(reg:CC FLAGS_REG) (const_int 0)]))] @@ -1205,13 +1144,13 @@ (define_expand "cbranch4" [(set (reg:CC FLAGS_REG) - (compare:CC (match_operand:MODEF 1 "cmp_fp_expander_operand" "") - (match_operand:MODEF 2 "cmp_fp_expander_operand" ""))) + (compare:CC (match_operand:MODEF 1 "cmp_fp_expander_operand") + (match_operand:MODEF 2 "cmp_fp_expander_operand"))) (set (pc) (if_then_else (match_operator 0 "ix86_fp_comparison_operator" [(reg:CC FLAGS_REG) (const_int 0)]) - (label_ref (match_operand 3 "" "")) + (label_ref (match_operand 3)) (pc)))] "TARGET_80387 || (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)" { @@ -1222,9 +1161,9 @@ (define_expand "cstore4" [(set (reg:CC FLAGS_REG) - (compare:CC (match_operand:MODEF 2 "cmp_fp_expander_operand" "") - (match_operand:MODEF 3 "cmp_fp_expander_operand" ""))) - (set (match_operand:QI 0 "register_operand" "") + (compare:CC (match_operand:MODEF 2 "cmp_fp_expander_operand") + (match_operand:MODEF 3 "cmp_fp_expander_operand"))) + (set (match_operand:QI 0 "register_operand") (match_operator 1 "ix86_fp_comparison_operator" [(reg:CC FLAGS_REG) (const_int 0)]))] @@ -1238,9 +1177,9 @@ (define_expand "cbranchcc4" [(set (pc) (if_then_else (match_operator 0 "comparison_operator" - [(match_operand 1 "flags_reg_operand" "") - (match_operand 2 "const0_operand" "")]) - (label_ref (match_operand 3 "" "")) + [(match_operand 1 "flags_reg_operand") + (match_operand 2 "const0_operand")]) + (label_ref (match_operand 3)) (pc)))] "" { @@ -1250,10 +1189,10 @@ }) (define_expand "cstorecc4" - [(set (match_operand:QI 0 "register_operand" "") + [(set (match_operand:QI 0 "register_operand") (match_operator 1 "comparison_operator" - [(match_operand 2 "flags_reg_operand" "") - (match_operand 3 "const0_operand" "")]))] + [(match_operand 2 "flags_reg_operand") + (match_operand 3 "const0_operand")]))] "" { ix86_expand_setcc (operands[0], GET_CODE (operands[1]), @@ -1276,7 +1215,7 @@ (unspec:HI [(compare:CCFP (match_operand 1 "register_operand" "f") - (match_operand 2 "const0_operand" ""))] + (match_operand 2 "const0_operand"))] UNSPEC_FNSTSW))] "X87_FLOAT_MODE_P (GET_MODE (operands[1])) && GET_MODE (operands[1]) == GET_MODE (operands[2])" @@ -1284,9 +1223,9 @@ [(set_attr "type" "multi") (set_attr "unit" "i387") (set (attr "mode") - (cond [(match_operand:SF 1 "" "") + (cond [(match_operand:SF 1) (const_string "SF") - (match_operand:DF 1 "" "") + (match_operand:DF 1) (const_string "DF") ] (const_string "XF")))]) @@ -1295,7 +1234,7 @@ [(set (reg:CCFP FLAGS_REG) (compare:CCFP (match_operand 1 "register_operand" "f") - (match_operand 2 "const0_operand" ""))) + (match_operand 2 "const0_operand"))) (clobber (match_operand:HI 0 "register_operand" "=a"))] "X87_FLOAT_MODE_P (GET_MODE (operands[1])) && TARGET_SAHF && !TARGET_CMOVE @@ -1312,9 +1251,9 @@ [(set_attr "type" "multi") (set_attr "unit" "i387") (set (attr "mode") - (cond [(match_operand:SF 1 "" "") + (cond [(match_operand:SF 1) (const_string "SF") - (match_operand:DF 1 "" "") + (match_operand:DF 1) (const_string "DF") ] (const_string "XF")))]) @@ -1400,9 +1339,9 @@ [(set_attr "type" "multi") (set_attr "unit" "i387") (set (attr "mode") - (cond [(match_operand:SF 1 "" "") + (cond [(match_operand:SF 1) (const_string "SF") - (match_operand:DF 1 "" "") + (match_operand:DF 1) (const_string "DF") ] (const_string "XF")))]) @@ -1428,9 +1367,9 @@ [(set_attr "type" "multi") (set_attr "unit" "i387") (set (attr "mode") - (cond [(match_operand:SF 1 "" "") + (cond [(match_operand:SF 1) (const_string "SF") - (match_operand:DF 1 "" "") + (match_operand:DF 1) (const_string "DF") ] (const_string "XF")))]) @@ -1528,7 +1467,7 @@ [(set_attr "type" "fcmp,ssecomi") (set_attr "prefix" "orig,maybe_vex") (set (attr "mode") - (if_then_else (match_operand:SF 1 "" "") + (if_then_else (match_operand:SF 1) (const_string "SF") (const_string "DF"))) (set (attr "prefix_rep") @@ -1557,7 +1496,7 @@ [(set_attr "type" "ssecomi") (set_attr "prefix" "maybe_vex") (set (attr "mode") - (if_then_else (match_operand:SF 1 "" "") + (if_then_else (match_operand:SF 1) (const_string "SF") (const_string "DF"))) (set_attr "prefix_rep" "0") @@ -1580,9 +1519,9 @@ "* return output_fp_compare (insn, operands, true, false);" [(set_attr "type" "fcmp") (set (attr "mode") - (cond [(match_operand:SF 1 "" "") + (cond [(match_operand:SF 1) (const_string "SF") - (match_operand:DF 1 "" "") + (match_operand:DF 1) (const_string "DF") ] (const_string "XF"))) @@ -1601,7 +1540,7 @@ [(set_attr "type" "fcmp,ssecomi") (set_attr "prefix" "orig,maybe_vex") (set (attr "mode") - (if_then_else (match_operand:SF 1 "" "") + (if_then_else (match_operand:SF 1) (const_string "SF") (const_string "DF"))) (set (attr "prefix_rep") @@ -1630,7 +1569,7 @@ [(set_attr "type" "ssecomi") (set_attr "prefix" "maybe_vex") (set (attr "mode") - (if_then_else (match_operand:SF 1 "" "") + (if_then_else (match_operand:SF 1) (const_string "SF") (const_string "DF"))) (set_attr "prefix_rep" "0") @@ -1653,9 +1592,9 @@ "* return output_fp_compare (insn, operands, true, true);" [(set_attr "type" "fcmp") (set (attr "mode") - (cond [(match_operand:SF 1 "" "") + (cond [(match_operand:SF 1) (const_string "SF") - (match_operand:DF 1 "" "") + (match_operand:DF 1) (const_string "DF") ] (const_string "XF"))) @@ -1674,8 +1613,8 @@ (set_attr "mode" "")]) (define_split - [(set (match_operand:TI 0 "push_operand" "") - (match_operand:TI 1 "general_operand" ""))] + [(set (match_operand:TI 0 "push_operand") + (match_operand:TI 1 "general_operand"))] "TARGET_64BIT && reload_completed && !SSE_REG_P (operands[1])" [(const_int 0)] @@ -1697,8 +1636,8 @@ ;; upper part by 32bit move. (define_peephole2 [(match_scratch:DI 2 "r") - (set (match_operand:DI 0 "push_operand" "") - (match_operand:DI 1 "immediate_operand" ""))] + (set (match_operand:DI 0 "push_operand") + (match_operand:DI 1 "immediate_operand"))] "TARGET_64BIT && !symbolic_operand (operands[1], DImode) && !x86_64_immediate_operand (operands[1], DImode)" [(set (match_dup 2) (match_dup 1)) @@ -1708,8 +1647,8 @@ ;; peephole2 pass is not run. ;; "&& 1" is needed to keep it from matching the previous pattern. (define_peephole2 - [(set (match_operand:DI 0 "push_operand" "") - (match_operand:DI 1 "immediate_operand" ""))] + [(set (match_operand:DI 0 "push_operand") + (match_operand:DI 1 "immediate_operand"))] "TARGET_64BIT && !symbolic_operand (operands[1], DImode) && !x86_64_immediate_operand (operands[1], DImode) && 1" [(set (match_dup 0) (match_dup 1)) @@ -1723,8 +1662,8 @@ }) (define_split - [(set (match_operand:DI 0 "push_operand" "") - (match_operand:DI 1 "immediate_operand" ""))] + [(set (match_operand:DI 0 "push_operand") + (match_operand:DI 1 "immediate_operand"))] "TARGET_64BIT && ((optimize > 0 && flag_peephole2) ? epilogue_completed : reload_completed) && !symbolic_operand (operands[1], DImode) @@ -1740,8 +1679,8 @@ }) (define_split - [(set (match_operand:DI 0 "push_operand" "") - (match_operand:DI 1 "general_operand" ""))] + [(set (match_operand:DI 0 "push_operand") + (match_operand:DI 1 "general_operand"))] "!TARGET_64BIT && reload_completed && !(MMX_REG_P (operands[1]) || SSE_REG_P (operands[1]))" [(const_int 0)] @@ -1777,8 +1716,8 @@ (set_attr "mode" "SI")]) (define_insn "*push2_prologue" - [(set (match_operand:P 0 "push_operand" "=<") - (match_operand:P 1 "general_no_elim_operand" "r*m")) + [(set (match_operand:W 0 "push_operand" "=<") + (match_operand:W 1 "general_no_elim_operand" "r*m")) (clobber (mem:BLK (scratch)))] "" "push{}\t%1" @@ -1786,16 +1725,16 @@ (set_attr "mode" "")]) (define_insn "*pop1" - [(set (match_operand:P 0 "nonimmediate_operand" "=r*m") - (match_operand:P 1 "pop_operand" ">"))] + [(set (match_operand:W 0 "nonimmediate_operand" "=r*m") + (match_operand:W 1 "pop_operand" ">"))] "" "pop{}\t%0" [(set_attr "type" "pop") (set_attr "mode" "")]) (define_insn "*pop1_epilogue" - [(set (match_operand:P 0 "nonimmediate_operand" "=r*m") - (match_operand:P 1 "pop_operand" ">")) + [(set (match_operand:W 0 "nonimmediate_operand" "=r*m") + (match_operand:W 1 "pop_operand" ">")) (clobber (mem:BLK (scratch)))] "" "pop{}\t%0" @@ -1805,14 +1744,14 @@ ;; Move instructions. (define_expand "movoi" - [(set (match_operand:OI 0 "nonimmediate_operand" "") - (match_operand:OI 1 "general_operand" ""))] + [(set (match_operand:OI 0 "nonimmediate_operand") + (match_operand:OI 1 "general_operand"))] "TARGET_AVX" "ix86_expand_move (OImode, operands); DONE;") (define_expand "movti" - [(set (match_operand:TI 0 "nonimmediate_operand" "") - (match_operand:TI 1 "nonimmediate_operand" ""))] + [(set (match_operand:TI 0 "nonimmediate_operand") + (match_operand:TI 1 "nonimmediate_operand"))] "TARGET_64BIT || TARGET_SSE" { if (TARGET_64BIT) @@ -1829,8 +1768,8 @@ ;; 32-bit targets when SSE is present, but doesn't seem to be harmful ;; to have around all the time. (define_expand "movcdi" - [(set (match_operand:CDI 0 "nonimmediate_operand" "") - (match_operand:CDI 1 "general_operand" ""))] + [(set (match_operand:CDI 0 "nonimmediate_operand") + (match_operand:CDI 1 "general_operand"))] "" { if (push_operand (operands[0], CDImode)) @@ -1841,14 +1780,14 @@ }) (define_expand "mov" - [(set (match_operand:SWI1248x 0 "nonimmediate_operand" "") - (match_operand:SWI1248x 1 "general_operand" ""))] + [(set (match_operand:SWI1248x 0 "nonimmediate_operand") + (match_operand:SWI1248x 1 "general_operand"))] "" "ix86_expand_move (mode, operands); DONE;") (define_insn "*mov_xor" [(set (match_operand:SWI48 0 "register_operand" "=r") - (match_operand:SWI48 1 "const0_operand" "")) + (match_operand:SWI48 1 "const0_operand")) (clobber (reg:CC FLAGS_REG))] "reload_completed" "xor{l}\t%k0, %k0" @@ -1858,7 +1797,7 @@ (define_insn "*mov_or" [(set (match_operand:SWI48 0 "register_operand" "=r") - (match_operand:SWI48 1 "const_int_operand" "")) + (match_operand:SWI48 1 "const_int_operand")) (clobber (reg:CC FLAGS_REG))] "reload_completed && operands[1] == constm1_rtx" @@ -1943,8 +1882,8 @@ (const_string "DI")))]) (define_split - [(set (match_operand:TI 0 "nonimmediate_operand" "") - (match_operand:TI 1 "general_operand" ""))] + [(set (match_operand:TI 0 "nonimmediate_operand") + (match_operand:TI 1 "general_operand"))] "reload_completed && !SSE_REG_P (operands[0]) && !SSE_REG_P (operands[1])" [(const_int 0)] @@ -2035,7 +1974,7 @@ return "#"; case TYPE_LEA: - return "lea{q}\t{%a1, %0|%0, %a1}"; + return "lea{q}\t{%E1, %0|%0, %E1}"; default: gcc_assert (!flag_pic || LEGITIMATE_PIC_OPERAND_P (operands[1])); @@ -2043,6 +1982,8 @@ return "mov{l}\t{%k1, %k0|%k0, %k1}"; else if (which_alternative == 2) return "movabs{q}\t{%1, %0|%0, %1}"; + else if (ix86_use_lea_for_mov (insn, operands)) + return "lea{q}\t{%E1, %0|%0, %E1}"; else return "mov{q}\t{%1, %0|%0, %1}"; } @@ -2060,7 +2001,7 @@ (const_string "ssemov") (eq_attr "alternative" "16,17") (const_string "ssecvt") - (match_operand 1 "pic_32bit_operand" "") + (match_operand 1 "pic_32bit_operand") (const_string "lea") ] (const_string "imov"))) @@ -2127,8 +2068,8 @@ ;; fails, move by 32bit parts. (define_peephole2 [(match_scratch:DI 2 "r") - (set (match_operand:DI 0 "memory_operand" "") - (match_operand:DI 1 "immediate_operand" ""))] + (set (match_operand:DI 0 "memory_operand") + (match_operand:DI 1 "immediate_operand"))] "TARGET_64BIT && !symbolic_operand (operands[1], DImode) && !x86_64_immediate_operand (operands[1], DImode)" [(set (match_dup 2) (match_dup 1)) @@ -2138,8 +2079,8 @@ ;; peephole2 pass is not run. ;; "&& 1" is needed to keep it from matching the previous pattern. (define_peephole2 - [(set (match_operand:DI 0 "memory_operand" "") - (match_operand:DI 1 "immediate_operand" ""))] + [(set (match_operand:DI 0 "memory_operand") + (match_operand:DI 1 "immediate_operand"))] "TARGET_64BIT && !symbolic_operand (operands[1], DImode) && !x86_64_immediate_operand (operands[1], DImode) && 1" [(set (match_dup 2) (match_dup 3)) @@ -2147,8 +2088,8 @@ "split_double_mode (DImode, &operands[0], 2, &operands[2], &operands[4]);") (define_split - [(set (match_operand:DI 0 "memory_operand" "") - (match_operand:DI 1 "immediate_operand" ""))] + [(set (match_operand:DI 0 "memory_operand") + (match_operand:DI 1 "immediate_operand"))] "TARGET_64BIT && ((optimize > 0 && flag_peephole2) ? epilogue_completed : reload_completed) && !symbolic_operand (operands[1], DImode) @@ -2230,8 +2171,8 @@ (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI,TI,DI,V4SF,V2SF,V4SF,V2SF,DI,DI")]) (define_split - [(set (match_operand:DI 0 "nonimmediate_operand" "") - (match_operand:DI 1 "general_operand" ""))] + [(set (match_operand:DI 0 "nonimmediate_operand") + (match_operand:DI 1 "general_operand"))] "!TARGET_64BIT && reload_completed && !(MMX_REG_P (operands[0]) || SSE_REG_P (operands[0])) && !(MMX_REG_P (operands[1]) || SSE_REG_P (operands[1]))" @@ -2274,11 +2215,14 @@ return "movd\t{%1, %0|%0, %1}"; case TYPE_LEA: - return "lea{l}\t{%a1, %0|%0, %a1}"; + return "lea{l}\t{%E1, %0|%0, %E1}"; default: gcc_assert (!flag_pic || LEGITIMATE_PIC_OPERAND_P (operands[1])); - return "mov{l}\t{%1, %0|%0, %1}"; + if (ix86_use_lea_for_mov (insn, operands)) + return "lea{l}\t{%E1, %0|%0, %E1}"; + else + return "mov{l}\t{%1, %0|%0, %1}"; } } [(set (attr "type") @@ -2290,7 +2234,7 @@ (const_string "sselog1") (eq_attr "alternative" "7,8,9,10,11") (const_string "ssemov") - (match_operand 1 "pic_32bit_operand" "") + (match_operand 1 "pic_32bit_operand") (const_string "lea") ] (const_string "imov"))) @@ -2342,7 +2286,7 @@ (not (match_test "TARGET_HIMODE_MATH")))) (const_string "imov") (and (eq_attr "alternative" "1,2") - (match_operand:HI 1 "aligned_operand" "")) + (match_operand:HI 1 "aligned_operand")) (const_string "imov") (and (match_test "TARGET_MOVX") (eq_attr "alternative" "0,2")) @@ -2353,7 +2297,7 @@ (cond [(eq_attr "type" "imovx") (const_string "SI") (and (eq_attr "alternative" "1,2") - (match_operand:HI 1 "aligned_operand" "")) + (match_operand:HI 1 "aligned_operand")) (const_string "SI") (and (eq_attr "alternative" "0") (ior (not (match_test "TARGET_PARTIAL_REG_STALL")) @@ -2391,7 +2335,7 @@ } [(set (attr "type") (cond [(and (eq_attr "alternative" "5") - (not (match_operand:QI 1 "aligned_operand" ""))) + (not (match_operand:QI 1 "aligned_operand"))) (const_string "imovx") (match_test "optimize_function_for_size_p (cfun)") (const_string "imov") @@ -2433,8 +2377,8 @@ ;; into register when rax is not available (define_insn "*movabs_1" [(set (mem:SWI1248x (match_operand:DI 0 "x86_64_movabs_operand" "i,r")) - (match_operand:SWI1248x 1 "nonmemory_operand" "a,er"))] - "TARGET_64BIT && ix86_check_movabs (insn, 0)" + (match_operand:SWI1248x 1 "nonmemory_operand" "a,r"))] + "TARGET_LP64 && ix86_check_movabs (insn, 0)" "@ movabs{}\t{%1, %P0|%P0, %1} mov{}\t{%1, %a0|%a0, %1}" @@ -2448,7 +2392,7 @@ (define_insn "*movabs_2" [(set (match_operand:SWI1248x 0 "register_operand" "=a,r") (mem:SWI1248x (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))] - "TARGET_64BIT && ix86_check_movabs (insn, 1)" + "TARGET_LP64 && ix86_check_movabs (insn, 1)" "@ movabs{}\t{%P1, %0|%0, %P1} mov{}\t{%a1, %0|%0, %a1}" @@ -2502,8 +2446,8 @@ (set_attr "athlon_decode" "vector")]) (define_expand "movstrict" - [(set (strict_low_part (match_operand:SWI12 0 "nonimmediate_operand" "")) - (match_operand:SWI12 1 "general_operand" ""))] + [(set (strict_low_part (match_operand:SWI12 0 "nonimmediate_operand")) + (match_operand:SWI12 1 "general_operand"))] "" { if (TARGET_PARTIAL_REG_STALL && optimize_function_for_speed_p (cfun)) @@ -2528,7 +2472,7 @@ (define_insn "*movstrict_xor" [(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+")) - (match_operand:SWI12 1 "const0_operand" "")) + (match_operand:SWI12 1 "const0_operand")) (clobber (reg:CC FLAGS_REG))] "reload_completed" "xor{}\t%0, %0" @@ -2562,7 +2506,7 @@ } } [(set (attr "type") - (if_then_else (ior (not (match_operand:QI 0 "QIreg_operand" "")) + (if_then_else (ior (not (match_operand:QI 0 "QIreg_operand")) (match_test "TARGET_MOVX")) (const_string "imovx") (const_string "imov"))) @@ -2587,8 +2531,8 @@ } } [(set (attr "type") - (if_then_else (and (match_operand:QI 0 "register_operand" "") - (ior (not (match_operand:QI 0 "QIreg_operand" "")) + (if_then_else (and (match_operand:QI 0 "register_operand") + (ior (not (match_operand:QI 0 "QIreg_operand")) (match_test "TARGET_MOVX"))) (const_string "imovx") (const_string "imov"))) @@ -2624,7 +2568,7 @@ } } [(set (attr "type") - (if_then_else (ior (not (match_operand:QI 0 "QIreg_operand" "")) + (if_then_else (ior (not (match_operand:QI 0 "QIreg_operand")) (match_test "TARGET_MOVX")) (const_string "imovx") (const_string "imov"))) @@ -2650,8 +2594,8 @@ } } [(set (attr "type") - (if_then_else (and (match_operand:QI 0 "register_operand" "") - (ior (not (match_operand:QI 0 "QIreg_operand" "")) + (if_then_else (and (match_operand:QI 0 "register_operand") + (ior (not (match_operand:QI 0 "QIreg_operand")) (match_test "TARGET_MOVX"))) (const_string "imovx") (const_string "imov"))) @@ -2661,10 +2605,10 @@ (const_string "QI")))]) (define_expand "mov_insv_1" - [(set (zero_extract:SWI48 (match_operand 0 "ext_register_operand" "") + [(set (zero_extract:SWI48 (match_operand 0 "ext_register_operand") (const_int 8) (const_int 8)) - (match_operand:SWI48 1 "nonmemory_operand" ""))]) + (match_operand:SWI48 1 "nonmemory_operand"))]) (define_insn "*mov_insv_1_rex64" [(set (zero_extract:SWI48x (match_operand 0 "ext_register_operand" "+Q") @@ -2713,8 +2657,8 @@ ;; %%% Kill this when call knows how to work this out. (define_split - [(set (match_operand:TF 0 "push_operand" "") - (match_operand:TF 1 "sse_reg_operand" ""))] + [(set (match_operand:TF 0 "push_operand") + (match_operand:TF 1 "sse_reg_operand"))] "TARGET_SSE2 && reload_completed" [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (const_int -16))) (set (mem:TF (reg:P SP_REG)) (match_dup 1))]) @@ -2751,8 +2695,8 @@ ;; %%% Kill this when call knows how to work this out. (define_split - [(set (match_operand:XF 0 "push_operand" "") - (match_operand:XF 1 "fp_register_operand" ""))] + [(set (match_operand:XF 0 "push_operand") + (match_operand:XF 1 "fp_register_operand"))] "reload_completed" [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2))) (set (mem:XF (reg:P SP_REG)) (match_dup 1))] @@ -2789,8 +2733,8 @@ ;; %%% Kill this when call knows how to work this out. (define_split - [(set (match_operand:DF 0 "push_operand" "") - (match_operand:DF 1 "any_fp_register_operand" ""))] + [(set (match_operand:DF 0 "push_operand") + (match_operand:DF 1 "any_fp_register_operand"))] "reload_completed" [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (const_int -8))) (set (mem:DF (reg:P SP_REG)) (match_dup 1))]) @@ -2823,23 +2767,23 @@ ;; %%% Kill this when call knows how to work this out. (define_split - [(set (match_operand:SF 0 "push_operand" "") - (match_operand:SF 1 "any_fp_register_operand" ""))] + [(set (match_operand:SF 0 "push_operand") + (match_operand:SF 1 "any_fp_register_operand"))] "reload_completed" [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2))) (set (mem:SF (reg:P SP_REG)) (match_dup 1))] "operands[2] = GEN_INT (-GET_MODE_SIZE (mode));") (define_split - [(set (match_operand:SF 0 "push_operand" "") - (match_operand:SF 1 "memory_operand" ""))] + [(set (match_operand:SF 0 "push_operand") + (match_operand:SF 1 "memory_operand"))] "reload_completed && (operands[2] = find_constant_src (insn))" [(set (match_dup 0) (match_dup 2))]) (define_split - [(set (match_operand 0 "push_operand" "") - (match_operand 1 "general_operand" ""))] + [(set (match_operand 0 "push_operand") + (match_operand 1 "general_operand"))] "reload_completed && (GET_MODE (operands[0]) == TFmode || GET_MODE (operands[0]) == XFmode @@ -2851,8 +2795,8 @@ ;; Floating point move instructions. (define_expand "movtf" - [(set (match_operand:TF 0 "nonimmediate_operand" "") - (match_operand:TF 1 "nonimmediate_operand" ""))] + [(set (match_operand:TF 0 "nonimmediate_operand") + (match_operand:TF 1 "nonimmediate_operand"))] "TARGET_SSE2" { ix86_expand_move (TFmode, operands); @@ -2860,8 +2804,8 @@ }) (define_expand "mov" - [(set (match_operand:X87MODEF 0 "nonimmediate_operand" "") - (match_operand:X87MODEF 1 "general_operand" ""))] + [(set (match_operand:X87MODEF 0 "nonimmediate_operand") + (match_operand:X87MODEF 1 "general_operand"))] "" "ix86_expand_move (mode, operands); DONE;") @@ -3342,8 +3286,8 @@ (const_string "SF")))]) (define_split - [(set (match_operand 0 "any_fp_register_operand" "") - (match_operand 1 "memory_operand" ""))] + [(set (match_operand 0 "any_fp_register_operand") + (match_operand 1 "memory_operand"))] "reload_completed && (GET_MODE (operands[0]) == TFmode || GET_MODE (operands[0]) == XFmode @@ -3361,8 +3305,8 @@ }) (define_split - [(set (match_operand 0 "any_fp_register_operand" "") - (float_extend (match_operand 1 "memory_operand" "")))] + [(set (match_operand 0 "any_fp_register_operand") + (float_extend (match_operand 1 "memory_operand")))] "reload_completed && (GET_MODE (operands[0]) == TFmode || GET_MODE (operands[0]) == XFmode @@ -3380,8 +3324,8 @@ ;; Split the load of -0.0 or -1.0 into fldz;fchs or fld1;fchs sequence (define_split - [(set (match_operand:X87MODEF 0 "fp_register_operand" "") - (match_operand:X87MODEF 1 "immediate_operand" ""))] + [(set (match_operand:X87MODEF 0 "fp_register_operand") + (match_operand:X87MODEF 1 "immediate_operand"))] "reload_completed && (standard_80387_constant_p (operands[1]) == 8 || standard_80387_constant_p (operands[1]) == 9)" @@ -3399,8 +3343,8 @@ }) (define_split - [(set (match_operand 0 "nonimmediate_operand" "") - (match_operand 1 "general_operand" ""))] + [(set (match_operand 0 "nonimmediate_operand") + (match_operand 1 "general_operand"))] "reload_completed && (GET_MODE (operands[0]) == TFmode || GET_MODE (operands[0]) == XFmode @@ -3442,47 +3386,34 @@ ;; Zero extension instructions (define_expand "zero_extendsidi2" - [(set (match_operand:DI 0 "nonimmediate_operand" "") - (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] - "" -{ - if (!TARGET_64BIT) - { - emit_insn (gen_zero_extendsidi2_1 (operands[0], operands[1])); - DONE; - } -}) + [(set (match_operand:DI 0 "nonimmediate_operand") + (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]) (define_insn "*zero_extendsidi2_rex64" - [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,?*Ym,?*y,?*Yi,*x") + [(set (match_operand:DI 0 "nonimmediate_operand" + "=r ,o,?*Ym,?*y,?*Yi,!*x") (zero_extend:DI - (match_operand:SI 1 "nonimmediate_operand" "rm,0,r ,m ,r ,m")))] + (match_operand:SI 1 "x86_64_zext_general_operand" + "rmZ,0,r ,m ,r ,m*x")))] "TARGET_64BIT" "@ - mov\t{%k1, %k0|%k0, %k1} + mov{l}\t{%1, %k0|%k0, %1} # movd\t{%1, %0|%0, %1} movd\t{%1, %0|%0, %1} %vmovd\t{%1, %0|%0, %1} %vmovd\t{%1, %0|%0, %1}" - [(set_attr "type" "imovx,imov,mmxmov,mmxmov,ssemov,ssemov") + [(set_attr "isa" "*,*,*,*,*,sse2") + (set_attr "type" "imovx,multi,mmxmov,mmxmov,ssemov,ssemov") (set_attr "prefix" "orig,*,orig,orig,maybe_vex,maybe_vex") (set_attr "prefix_0f" "0,*,*,*,*,*") - (set_attr "mode" "SI,DI,DI,DI,TI,TI")]) - -(define_split - [(set (match_operand:DI 0 "memory_operand" "") - (zero_extend:DI (match_dup 0)))] - "TARGET_64BIT" - [(set (match_dup 4) (const_int 0))] - "split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);") + (set_attr "mode" "SI,SI,DI,DI,TI,TI")]) -;; %%% Kill me once multi-word ops are sane. -(define_insn "zero_extendsidi2_1" - [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?o,?*Ym,?*y,?*Yi,*x") - (zero_extend:DI - (match_operand:SI 1 "nonimmediate_operand" "0,rm,r ,r ,m ,r ,m"))) - (clobber (reg:CC FLAGS_REG))] +(define_insn "*zero_extendsidi2" + [(set (match_operand:DI 0 "nonimmediate_operand" + "=ro,?r,?o,?*Ym,?*y,?*Yi,!*x") + (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" + "0 ,rm,r ,r ,m ,r ,m*x")))] "!TARGET_64BIT" "@ # @@ -3498,19 +3429,26 @@ (set_attr "mode" "SI,SI,SI,DI,DI,TI,TI")]) (define_split - [(set (match_operand:DI 0 "register_operand" "") - (zero_extend:DI (match_operand:SI 1 "register_operand" ""))) - (clobber (reg:CC FLAGS_REG))] + [(set (match_operand:DI 0 "memory_operand") + (zero_extend:DI (match_operand:SI 1 "memory_operand")))] + "reload_completed" + [(set (match_dup 4) (const_int 0))] + "split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);") + +(define_split + [(set (match_operand:DI 0 "register_operand") + (zero_extend:DI (match_operand:SI 1 "register_operand")))] "!TARGET_64BIT && reload_completed + && !(MMX_REG_P (operands[0]) || SSE_REG_P (operands[0])) && true_regnum (operands[0]) == true_regnum (operands[1])" [(set (match_dup 4) (const_int 0))] "split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);") (define_split - [(set (match_operand:DI 0 "nonimmediate_operand" "") - (zero_extend:DI (match_operand:SI 1 "general_operand" ""))) - (clobber (reg:CC FLAGS_REG))] + [(set (match_operand:DI 0 "nonimmediate_operand") + (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))] "!TARGET_64BIT && reload_completed + && !(MEM_P (operands[0]) && MEM_P (operands[1])) && !(MMX_REG_P (operands[0]) || SSE_REG_P (operands[0]))" [(set (match_dup 3) (match_dup 1)) (set (match_dup 4) (const_int 0))] @@ -3525,118 +3463,106 @@ [(set_attr "type" "imovx") (set_attr "mode" "SI")]) -(define_expand "zero_extendhisi2" - [(set (match_operand:SI 0 "register_operand" "") - (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] +(define_expand "zero_extendsi2" + [(set (match_operand:SI 0 "register_operand") + (zero_extend:SI (match_operand:SWI12 1 "nonimmediate_operand")))] "" { if (TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)) { - operands[1] = force_reg (HImode, operands[1]); - emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1])); + operands[1] = force_reg (mode, operands[1]); + emit_insn (gen_zero_extendsi2_and (operands[0], operands[1])); DONE; } }) -(define_insn_and_split "zero_extendhisi2_and" - [(set (match_operand:SI 0 "register_operand" "=r") - (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))) +(define_insn_and_split "zero_extendsi2_and" + [(set (match_operand:SI 0 "register_operand" "=r,?&") + (zero_extend:SI + (match_operand:SWI12 1 "nonimmediate_operand" "0,m"))) (clobber (reg:CC FLAGS_REG))] "TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)" "#" "&& reload_completed" - [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535))) + [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] - "" +{ + if (true_regnum (operands[0]) != true_regnum (operands[1])) + { + ix86_expand_clear (operands[0]); + + gcc_assert (!TARGET_PARTIAL_REG_STALL); + emit_insn (gen_movstrict + (gen_lowpart (mode, operands[0]), operands[1])); + DONE; + } + + operands[2] = GEN_INT (GET_MODE_MASK (mode)); +} [(set_attr "type" "alu1") (set_attr "mode" "SI")]) -(define_insn "*zero_extendhisi2_movzwl" +(define_insn "*zero_extendsi2" [(set (match_operand:SI 0 "register_operand" "=r") - (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))] - "!TARGET_ZERO_EXTEND_WITH_AND - || optimize_function_for_size_p (cfun)" - "movz{wl|x}\t{%1, %0|%0, %1}" + (zero_extend:SI + (match_operand:SWI12 1 "nonimmediate_operand" "m")))] + "!(TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun))" + "movz{l|x}\t{%1, %0|%0, %1}" [(set_attr "type" "imovx") (set_attr "mode" "SI")]) -(define_expand "zero_extendqi2" - [(parallel - [(set (match_operand:SWI24 0 "register_operand" "") - (zero_extend:SWI24 (match_operand:QI 1 "nonimmediate_operand" ""))) - (clobber (reg:CC FLAGS_REG))])]) +(define_expand "zero_extendqihi2" + [(set (match_operand:HI 0 "register_operand") + (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))] + "" +{ + if (TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)) + { + operands[1] = force_reg (QImode, operands[1]); + emit_insn (gen_zero_extendqihi2_and (operands[0], operands[1])); + DONE; + } +}) -(define_insn "*zero_extendqi2_and" - [(set (match_operand:SWI24 0 "register_operand" "=r,?&q") - (zero_extend:SWI24 (match_operand:QI 1 "nonimmediate_operand" "0,qm"))) +(define_insn_and_split "zero_extendqihi2_and" + [(set (match_operand:HI 0 "register_operand" "=r,?&q") + (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm"))) (clobber (reg:CC FLAGS_REG))] "TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)" "#" - [(set_attr "type" "alu1") - (set_attr "mode" "")]) - -;; When source and destination does not overlap, clear destination -;; first and then do the movb -(define_split - [(set (match_operand:SWI24 0 "register_operand" "") - (zero_extend:SWI24 (match_operand:QI 1 "nonimmediate_operand" ""))) - (clobber (reg:CC FLAGS_REG))] - "reload_completed - && (TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)) - && ANY_QI_REG_P (operands[0]) - && (ANY_QI_REG_P (operands[1]) || MEM_P (operands[1])) - && !reg_overlap_mentioned_p (operands[0], operands[1])" - [(set (strict_low_part (match_dup 2)) (match_dup 1))] + "&& reload_completed" + [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255))) + (clobber (reg:CC FLAGS_REG))])] { - operands[2] = gen_lowpart (QImode, operands[0]); - ix86_expand_clear (operands[0]); -}) + if (true_regnum (operands[0]) != true_regnum (operands[1])) + { + ix86_expand_clear (operands[0]); -(define_insn "*zero_extendqi2_movzbl_and" - [(set (match_operand:SWI24 0 "register_operand" "=r,r") - (zero_extend:SWI24 (match_operand:QI 1 "nonimmediate_operand" "qm,0"))) - (clobber (reg:CC FLAGS_REG))] - "!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_size_p (cfun)" - "#" - [(set_attr "type" "imovx,alu1") - (set_attr "mode" "")]) + gcc_assert (!TARGET_PARTIAL_REG_STALL); + emit_insn (gen_movstrictqi + (gen_lowpart (QImode, operands[0]), operands[1])); + DONE; + } -;; For the movzbl case strip only the clobber -(define_split - [(set (match_operand:SWI24 0 "register_operand" "") - (zero_extend:SWI24 (match_operand:QI 1 "nonimmediate_operand" ""))) - (clobber (reg:CC FLAGS_REG))] - "reload_completed - && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_size_p (cfun)) - && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))" - [(set (match_dup 0) - (zero_extend:SWI24 (match_dup 1)))]) + operands[0] = gen_lowpart (SImode, operands[0]); +} + [(set_attr "type" "alu1") + (set_attr "mode" "SI")]) ; zero extend to SImode to avoid partial register stalls -(define_insn "*zero_extendqi2_movzbl" - [(set (match_operand:SWI24 0 "register_operand" "=r") - (zero_extend:SWI24 (match_operand:QI 1 "nonimmediate_operand" "qm")))] - "reload_completed - && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_size_p (cfun))" +(define_insn "*zero_extendqihi2" + [(set (match_operand:HI 0 "register_operand" "=r") + (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))] + "!(TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun))" "movz{bl|x}\t{%1, %k0|%k0, %1}" [(set_attr "type" "imovx") (set_attr "mode" "SI")]) - -;; Rest is handled by single and. -(define_split - [(set (match_operand:SWI24 0 "register_operand" "") - (zero_extend:SWI24 (match_operand:QI 1 "register_operand" ""))) - (clobber (reg:CC FLAGS_REG))] - "reload_completed - && true_regnum (operands[0]) == true_regnum (operands[1])" - [(parallel [(set (match_dup 0) (and:SWI24 (match_dup 0) (const_int 255))) - (clobber (reg:CC FLAGS_REG))])]) ;; Sign extension instructions (define_expand "extendsidi2" - [(set (match_operand:DI 0 "register_operand" "") - (sign_extend:DI (match_operand:SI 1 "register_operand" "")))] + [(set (match_operand:DI 0 "register_operand") + (sign_extend:DI (match_operand:SI 1 "register_operand")))] "" { if (!TARGET_64BIT) @@ -3668,10 +3594,10 @@ ;; Extend to memory case when source register does die. (define_split - [(set (match_operand:DI 0 "memory_operand" "") - (sign_extend:DI (match_operand:SI 1 "register_operand" ""))) + [(set (match_operand:DI 0 "memory_operand") + (sign_extend:DI (match_operand:SI 1 "register_operand"))) (clobber (reg:CC FLAGS_REG)) - (clobber (match_operand:SI 2 "register_operand" ""))] + (clobber (match_operand:SI 2 "register_operand"))] "(reload_completed && dead_or_set_p (insn, operands[1]) && !reg_mentioned_p (operands[1], operands[0]))" @@ -3683,10 +3609,10 @@ ;; Extend to memory case when source register does not die. (define_split - [(set (match_operand:DI 0 "memory_operand" "") - (sign_extend:DI (match_operand:SI 1 "register_operand" ""))) + [(set (match_operand:DI 0 "memory_operand") + (sign_extend:DI (match_operand:SI 1 "register_operand"))) (clobber (reg:CC FLAGS_REG)) - (clobber (match_operand:SI 2 "register_operand" ""))] + (clobber (match_operand:SI 2 "register_operand"))] "reload_completed" [(const_int 0)] { @@ -3713,10 +3639,10 @@ ;; Extend to register case. Optimize case where source and destination ;; registers match and cases where we can use cltd. (define_split - [(set (match_operand:DI 0 "register_operand" "") - (sign_extend:DI (match_operand:SI 1 "register_operand" ""))) + [(set (match_operand:DI 0 "register_operand") + (sign_extend:DI (match_operand:SI 1 "register_operand"))) (clobber (reg:CC FLAGS_REG)) - (clobber (match_scratch:SI 2 ""))] + (clobber (match_scratch:SI 2))] "reload_completed" [(const_int 0)] { @@ -3854,23 +3780,23 @@ ;; %%% Kill these when call knows how to work out a DFmode push earlier. (define_split - [(set (match_operand:DF 0 "push_operand" "") - (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))] + [(set (match_operand:DF 0 "push_operand") + (float_extend:DF (match_operand:SF 1 "fp_register_operand")))] "reload_completed" [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (const_int -8))) (set (mem:DF (reg:P SP_REG)) (float_extend:DF (match_dup 1)))]) (define_split - [(set (match_operand:XF 0 "push_operand" "") - (float_extend:XF (match_operand:MODEF 1 "fp_register_operand" "")))] + [(set (match_operand:XF 0 "push_operand") + (float_extend:XF (match_operand:MODEF 1 "fp_register_operand")))] "reload_completed" [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2))) (set (mem:XF (reg:P SP_REG)) (float_extend:XF (match_dup 1)))] "operands[2] = GEN_INT (-GET_MODE_SIZE (XFmode));") (define_expand "extendsfdf2" - [(set (match_operand:DF 0 "nonimmediate_operand" "") - (float_extend:DF (match_operand:SF 1 "general_operand" "")))] + [(set (match_operand:DF 0 "nonimmediate_operand") + (float_extend:DF (match_operand:SF 1 "general_operand")))] "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)" { /* ??? Needed for compress_float_constant since all fp constants @@ -3897,9 +3823,9 @@ that might lead to ICE on 32bit target. The sequence unlikely combine anyway. */ (define_split - [(set (match_operand:DF 0 "register_operand" "") + [(set (match_operand:DF 0 "register_operand") (float_extend:DF - (match_operand:SF 1 "nonimmediate_operand" "")))] + (match_operand:SF 1 "nonimmediate_operand")))] "TARGET_USE_VECTOR_FP_CONVERTS && optimize_insn_for_speed_p () && reload_completed && SSE_REG_P (operands[0])" @@ -3975,8 +3901,8 @@ (set_attr "mode" "SF,XF")]) (define_expand "extendxf2" - [(set (match_operand:XF 0 "nonimmediate_operand" "") - (float_extend:XF (match_operand:MODEF 1 "general_operand" "")))] + [(set (match_operand:XF 0 "nonimmediate_operand") + (float_extend:XF (match_operand:MODEF 1 "general_operand")))] "TARGET_80387" { /* ??? Needed for compress_float_constant since all fp constants @@ -4012,9 +3938,9 @@ ;; Conversion from DFmode to SFmode. (define_expand "truncdfsf2" - [(set (match_operand:SF 0 "nonimmediate_operand" "") + [(set (match_operand:SF 0 "nonimmediate_operand") (float_truncate:SF - (match_operand:DF 1 "nonimmediate_operand" "")))] + (match_operand:DF 1 "nonimmediate_operand")))] "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)" { if (TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_MIX_SSE_I387) @@ -4040,9 +3966,9 @@ that might lead to ICE on 32bit target. The sequence unlikely combine anyway. */ (define_split - [(set (match_operand:SF 0 "register_operand" "") + [(set (match_operand:SF 0 "register_operand") (float_truncate:SF - (match_operand:DF 1 "nonimmediate_operand" "")))] + (match_operand:DF 1 "nonimmediate_operand")))] "TARGET_USE_VECTOR_FP_CONVERTS && optimize_insn_for_speed_p () && reload_completed && SSE_REG_P (operands[0])" @@ -4079,9 +4005,9 @@ }) (define_expand "truncdfsf2_with_temp" - [(parallel [(set (match_operand:SF 0 "" "") - (float_truncate:SF (match_operand:DF 1 "" ""))) - (clobber (match_operand:SF 2 "" ""))])]) + [(parallel [(set (match_operand:SF 0) + (float_truncate:SF (match_operand:DF 1))) + (clobber (match_operand:SF 2))])]) (define_insn "*truncdfsf_fast_mixed" [(set (match_operand:SF 0 "nonimmediate_operand" "=fm,x") @@ -4180,10 +4106,10 @@ (set_attr "mode" "SF")]) (define_split - [(set (match_operand:SF 0 "register_operand" "") + [(set (match_operand:SF 0 "register_operand") (float_truncate:SF - (match_operand:DF 1 "fp_register_operand" ""))) - (clobber (match_operand 2 "" ""))] + (match_operand:DF 1 "fp_register_operand"))) + (clobber (match_operand 2))] "reload_completed" [(set (match_dup 2) (match_dup 1)) (set (match_dup 0) (match_dup 2))] @@ -4192,9 +4118,9 @@ ;; Conversion from XFmode to {SF,DF}mode (define_expand "truncxf2" - [(parallel [(set (match_operand:MODEF 0 "nonimmediate_operand" "") + [(parallel [(set (match_operand:MODEF 0 "nonimmediate_operand") (float_truncate:MODEF - (match_operand:XF 1 "register_operand" ""))) + (match_operand:XF 1 "register_operand"))) (clobber (match_dup 2))])] "TARGET_80387" { @@ -4263,27 +4189,27 @@ (set_attr "mode" "")]) (define_split - [(set (match_operand:MODEF 0 "register_operand" "") + [(set (match_operand:MODEF 0 "register_operand") (float_truncate:MODEF - (match_operand:XF 1 "register_operand" ""))) - (clobber (match_operand:MODEF 2 "memory_operand" ""))] + (match_operand:XF 1 "register_operand"))) + (clobber (match_operand:MODEF 2 "memory_operand"))] "TARGET_80387 && reload_completed" [(set (match_dup 2) (float_truncate:MODEF (match_dup 1))) (set (match_dup 0) (match_dup 2))]) (define_split - [(set (match_operand:MODEF 0 "memory_operand" "") + [(set (match_operand:MODEF 0 "memory_operand") (float_truncate:MODEF - (match_operand:XF 1 "register_operand" ""))) - (clobber (match_operand:MODEF 2 "memory_operand" ""))] + (match_operand:XF 1 "register_operand"))) + (clobber (match_operand:MODEF 2 "memory_operand"))] "TARGET_80387" [(set (match_dup 0) (float_truncate:MODEF (match_dup 1)))]) ;; Signed conversion to DImode. (define_expand "fix_truncxfdi2" - [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "") - (fix:DI (match_operand:XF 1 "register_operand" ""))) + [(parallel [(set (match_operand:DI 0 "nonimmediate_operand") + (fix:DI (match_operand:XF 1 "register_operand"))) (clobber (reg:CC FLAGS_REG))])] "TARGET_80387" { @@ -4295,8 +4221,8 @@ }) (define_expand "fix_truncdi2" - [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "") - (fix:DI (match_operand:MODEF 1 "register_operand" ""))) + [(parallel [(set (match_operand:DI 0 "nonimmediate_operand") + (fix:DI (match_operand:MODEF 1 "register_operand"))) (clobber (reg:CC FLAGS_REG))])] "TARGET_80387 || (TARGET_64BIT && SSE_FLOAT_MODE_P (mode))" { @@ -4319,8 +4245,8 @@ ;; Signed conversion to SImode. (define_expand "fix_truncxfsi2" - [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "") - (fix:SI (match_operand:XF 1 "register_operand" ""))) + [(parallel [(set (match_operand:SI 0 "nonimmediate_operand") + (fix:SI (match_operand:XF 1 "register_operand"))) (clobber (reg:CC FLAGS_REG))])] "TARGET_80387" { @@ -4332,8 +4258,8 @@ }) (define_expand "fix_truncsi2" - [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "") - (fix:SI (match_operand:MODEF 1 "register_operand" ""))) + [(parallel [(set (match_operand:SI 0 "nonimmediate_operand") + (fix:SI (match_operand:MODEF 1 "register_operand"))) (clobber (reg:CC FLAGS_REG))])] "TARGET_80387 || SSE_FLOAT_MODE_P (mode)" { @@ -4356,8 +4282,8 @@ ;; Signed conversion to HImode. (define_expand "fix_trunchi2" - [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "") - (fix:HI (match_operand:X87MODEF 1 "register_operand" ""))) + [(parallel [(set (match_operand:HI 0 "nonimmediate_operand") + (fix:HI (match_operand:X87MODEF 1 "register_operand"))) (clobber (reg:CC FLAGS_REG))])] "TARGET_80387 && !(SSE_FLOAT_MODE_P (mode) && (!TARGET_FISTTP || TARGET_SSE_MATH))" @@ -4373,12 +4299,12 @@ (define_expand "fixuns_truncsi2" [(parallel - [(set (match_operand:SI 0 "register_operand" "") + [(set (match_operand:SI 0 "register_operand") (unsigned_fix:SI - (match_operand:MODEF 1 "nonimmediate_operand" ""))) + (match_operand:MODEF 1 "nonimmediate_operand"))) (use (match_dup 2)) - (clobber (match_scratch: 3 "")) - (clobber (match_scratch: 4 ""))])] + (clobber (match_scratch: 3)) + (clobber (match_scratch: 4))])] "!TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH" { enum machine_mode mode = mode; @@ -4418,8 +4344,8 @@ (define_expand "fixuns_trunchi2" [(set (match_dup 2) - (fix:SI (match_operand:MODEF 1 "nonimmediate_operand" ""))) - (set (match_operand:HI 0 "nonimmediate_operand" "") + (fix:SI (match_operand:MODEF 1 "nonimmediate_operand"))) + (set (match_operand:HI 0 "nonimmediate_operand") (subreg:HI (match_dup 2) 0))] "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH" "operands[2] = gen_reg_rtx (SImode);") @@ -4454,9 +4380,9 @@ ;; Shorten x87->SSE reload sequences of fix_trunc?f?i_sse patterns. (define_peephole2 - [(set (match_operand:MODEF 0 "register_operand" "") - (match_operand:MODEF 1 "memory_operand" "")) - (set (match_operand:SWI48x 2 "register_operand" "") + [(set (match_operand:MODEF 0 "register_operand") + (match_operand:MODEF 1 "memory_operand")) + (set (match_operand:SWI48x 2 "register_operand") (fix:SWI48x (match_dup 0)))] "TARGET_SHORTEN_X87_SSE && !(TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ()) @@ -4466,23 +4392,23 @@ ;; Avoid vector decoded forms of the instruction. (define_peephole2 [(match_scratch:DF 2 "x") - (set (match_operand:SWI48x 0 "register_operand" "") - (fix:SWI48x (match_operand:DF 1 "memory_operand" "")))] + (set (match_operand:SWI48x 0 "register_operand") + (fix:SWI48x (match_operand:DF 1 "memory_operand")))] "TARGET_SSE2 && TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ()" [(set (match_dup 2) (match_dup 1)) (set (match_dup 0) (fix:SWI48x (match_dup 2)))]) (define_peephole2 [(match_scratch:SF 2 "x") - (set (match_operand:SWI48x 0 "register_operand" "") - (fix:SWI48x (match_operand:SF 1 "memory_operand" "")))] + (set (match_operand:SWI48x 0 "register_operand") + (fix:SWI48x (match_operand:SF 1 "memory_operand")))] "TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ()" [(set (match_dup 2) (match_dup 1)) (set (match_dup 0) (fix:SWI48x (match_dup 2)))]) (define_insn_and_split "fix_trunc_fisttp_i387_1" - [(set (match_operand:SWI248x 0 "nonimmediate_operand" "") - (fix:SWI248x (match_operand 1 "register_operand" "")))] + [(set (match_operand:SWI248x 0 "nonimmediate_operand") + (fix:SWI248x (match_operand 1 "register_operand")))] "X87_FLOAT_MODE_P (GET_MODE (operands[1])) && TARGET_FISTTP && !((SSE_FLOAT_MODE_P (GET_MODE (operands[1])) @@ -4535,20 +4461,20 @@ (set_attr "mode" "")]) (define_split - [(set (match_operand:SWI248x 0 "register_operand" "") - (fix:SWI248x (match_operand 1 "register_operand" ""))) - (clobber (match_operand:SWI248x 2 "memory_operand" "")) - (clobber (match_scratch 3 ""))] + [(set (match_operand:SWI248x 0 "register_operand") + (fix:SWI248x (match_operand 1 "register_operand"))) + (clobber (match_operand:SWI248x 2 "memory_operand")) + (clobber (match_scratch 3))] "reload_completed" [(parallel [(set (match_dup 2) (fix:SWI248x (match_dup 1))) (clobber (match_dup 3))]) (set (match_dup 0) (match_dup 2))]) (define_split - [(set (match_operand:SWI248x 0 "memory_operand" "") - (fix:SWI248x (match_operand 1 "register_operand" ""))) - (clobber (match_operand:SWI248x 2 "memory_operand" "")) - (clobber (match_scratch 3 ""))] + [(set (match_operand:SWI248x 0 "memory_operand") + (fix:SWI248x (match_operand 1 "register_operand"))) + (clobber (match_operand:SWI248x 2 "memory_operand")) + (clobber (match_scratch 3))] "reload_completed" [(parallel [(set (match_dup 0) (fix:SWI248x (match_dup 1))) (clobber (match_dup 3))])]) @@ -4559,8 +4485,8 @@ ;; clobbering insns can be used. Look at emit_i387_cw_initialization () ;; function in i386.c. (define_insn_and_split "*fix_trunc_i387_1" - [(set (match_operand:SWI248x 0 "nonimmediate_operand" "") - (fix:SWI248x (match_operand 1 "register_operand" ""))) + [(set (match_operand:SWI248x 0 "nonimmediate_operand") + (fix:SWI248x (match_operand 1 "register_operand"))) (clobber (reg:CC FLAGS_REG))] "X87_FLOAT_MODE_P (GET_MODE (operands[1])) && !TARGET_FISTTP @@ -4621,12 +4547,12 @@ (set_attr "mode" "DI")]) (define_split - [(set (match_operand:DI 0 "register_operand" "") - (fix:DI (match_operand 1 "register_operand" ""))) - (use (match_operand:HI 2 "memory_operand" "")) - (use (match_operand:HI 3 "memory_operand" "")) - (clobber (match_operand:DI 4 "memory_operand" "")) - (clobber (match_scratch 5 ""))] + [(set (match_operand:DI 0 "register_operand") + (fix:DI (match_operand 1 "register_operand"))) + (use (match_operand:HI 2 "memory_operand")) + (use (match_operand:HI 3 "memory_operand")) + (clobber (match_operand:DI 4 "memory_operand")) + (clobber (match_scratch 5))] "reload_completed" [(parallel [(set (match_dup 4) (fix:DI (match_dup 1))) (use (match_dup 2)) @@ -4635,12 +4561,12 @@ (set (match_dup 0) (match_dup 4))]) (define_split - [(set (match_operand:DI 0 "memory_operand" "") - (fix:DI (match_operand 1 "register_operand" ""))) - (use (match_operand:HI 2 "memory_operand" "")) - (use (match_operand:HI 3 "memory_operand" "")) - (clobber (match_operand:DI 4 "memory_operand" "")) - (clobber (match_scratch 5 ""))] + [(set (match_operand:DI 0 "memory_operand") + (fix:DI (match_operand 1 "register_operand"))) + (use (match_operand:HI 2 "memory_operand")) + (use (match_operand:HI 3 "memory_operand")) + (clobber (match_operand:DI 4 "memory_operand")) + (clobber (match_scratch 5))] "reload_completed" [(parallel [(set (match_dup 0) (fix:DI (match_dup 1))) (use (match_dup 2)) @@ -4675,11 +4601,11 @@ (set_attr "mode" "")]) (define_split - [(set (match_operand:SWI24 0 "register_operand" "") - (fix:SWI24 (match_operand 1 "register_operand" ""))) - (use (match_operand:HI 2 "memory_operand" "")) - (use (match_operand:HI 3 "memory_operand" "")) - (clobber (match_operand:SWI24 4 "memory_operand" ""))] + [(set (match_operand:SWI24 0 "register_operand") + (fix:SWI24 (match_operand 1 "register_operand"))) + (use (match_operand:HI 2 "memory_operand")) + (use (match_operand:HI 3 "memory_operand")) + (clobber (match_operand:SWI24 4 "memory_operand"))] "reload_completed" [(parallel [(set (match_dup 4) (fix:SWI24 (match_dup 1))) (use (match_dup 2)) @@ -4687,11 +4613,11 @@ (set (match_dup 0) (match_dup 4))]) (define_split - [(set (match_operand:SWI24 0 "memory_operand" "") - (fix:SWI24 (match_operand 1 "register_operand" ""))) - (use (match_operand:HI 2 "memory_operand" "")) - (use (match_operand:HI 3 "memory_operand" "")) - (clobber (match_operand:SWI24 4 "memory_operand" ""))] + [(set (match_operand:SWI24 0 "memory_operand") + (fix:SWI24 (match_operand 1 "register_operand"))) + (use (match_operand:HI 2 "memory_operand")) + (use (match_operand:HI 3 "memory_operand")) + (clobber (match_operand:SWI24 4 "memory_operand"))] "reload_completed" [(parallel [(set (match_dup 0) (fix:SWI24 (match_dup 1))) (use (match_dup 2)) @@ -4727,16 +4653,16 @@ ;; wants to be able to do this between registers. (define_expand "floathi2" - [(set (match_operand:X87MODEF 0 "register_operand" "") - (float:X87MODEF (match_operand:HI 1 "nonimmediate_operand" "")))] + [(set (match_operand:X87MODEF 0 "register_operand") + (float:X87MODEF (match_operand:HI 1 "nonimmediate_operand")))] "TARGET_80387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)") ;; Pre-reload splitter to add memory clobber to the pattern. (define_insn_and_split "*floathi2_1" - [(set (match_operand:X87MODEF 0 "register_operand" "") - (float:X87MODEF (match_operand:HI 1 "register_operand" "")))] + [(set (match_operand:X87MODEF 0 "register_operand") + (float:X87MODEF (match_operand:HI 1 "register_operand")))] "TARGET_80387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -4751,7 +4677,7 @@ (define_insn "*floathi2_i387_with_temp" [(set (match_operand:X87MODEF 0 "register_operand" "=f,f") (float:X87MODEF (match_operand:HI 1 "nonimmediate_operand" "m,?r"))) - (clobber (match_operand:HI 2 "memory_operand" "=m,m"))] + (clobber (match_operand:HI 2 "memory_operand" "=X,m"))] "TARGET_80387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)" @@ -4773,9 +4699,9 @@ (set_attr "fp_int_src" "true")]) (define_split - [(set (match_operand:X87MODEF 0 "register_operand" "") - (float:X87MODEF (match_operand:HI 1 "register_operand" ""))) - (clobber (match_operand:HI 2 "memory_operand" ""))] + [(set (match_operand:X87MODEF 0 "register_operand") + (float:X87MODEF (match_operand:HI 1 "register_operand"))) + (clobber (match_operand:HI 2 "memory_operand"))] "TARGET_80387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -4784,9 +4710,9 @@ (set (match_dup 0) (float:X87MODEF (match_dup 2)))]) (define_split - [(set (match_operand:X87MODEF 0 "register_operand" "") - (float:X87MODEF (match_operand:HI 1 "memory_operand" ""))) - (clobber (match_operand:HI 2 "memory_operand" ""))] + [(set (match_operand:X87MODEF 0 "register_operand") + (float:X87MODEF (match_operand:HI 1 "memory_operand"))) + (clobber (match_operand:HI 2 "memory_operand"))] "TARGET_80387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -4794,9 +4720,9 @@ [(set (match_dup 0) (float:X87MODEF (match_dup 1)))]) (define_expand "float2" - [(set (match_operand:X87MODEF 0 "register_operand" "") + [(set (match_operand:X87MODEF 0 "register_operand") (float:X87MODEF - (match_operand:SWI48x 1 "nonimmediate_operand" "")))] + (match_operand:SWI48x 1 "nonimmediate_operand")))] "TARGET_80387 || ((mode != DImode || TARGET_64BIT) && SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)" @@ -4824,8 +4750,8 @@ ;; Pre-reload splitter to add memory clobber to the pattern. (define_insn_and_split "*float2_1" - [(set (match_operand:X87MODEF 0 "register_operand" "") - (float:X87MODEF (match_operand:SWI48x 1 "register_operand" "")))] + [(set (match_operand:X87MODEF 0 "register_operand") + (float:X87MODEF (match_operand:SWI48x 1 "register_operand")))] "((TARGET_80387 && X87_ENABLE_FLOAT (mode, mode) && (!((mode != DImode || TARGET_64BIT) @@ -4909,29 +4835,29 @@ (set_attr "fp_int_src" "true")]) (define_split - [(set (match_operand:MODEF 0 "register_operand" "") - (float:MODEF (match_operand:SWI48x 1 "register_operand" ""))) - (clobber (match_operand:SWI48x 2 "memory_operand" ""))] + [(set (match_operand:MODEF 0 "register_operand") + (float:MODEF (match_operand:SWI48x 1 "register_operand"))) + (clobber (match_operand:SWI48x 2 "memory_operand"))] "(mode != DImode || TARGET_64BIT) && SSE_FLOAT_MODE_P (mode) && TARGET_MIX_SSE_I387 && TARGET_INTER_UNIT_CONVERSIONS && reload_completed && (SSE_REG_P (operands[0]) || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(set (match_dup 0) (float:MODEF (match_dup 1)))]) (define_split - [(set (match_operand:MODEF 0 "register_operand" "") - (float:MODEF (match_operand:SWI48x 1 "register_operand" ""))) - (clobber (match_operand:SWI48x 2 "memory_operand" ""))] + [(set (match_operand:MODEF 0 "register_operand") + (float:MODEF (match_operand:SWI48x 1 "register_operand"))) + (clobber (match_operand:SWI48x 2 "memory_operand"))] "(mode != DImode || TARGET_64BIT) && SSE_FLOAT_MODE_P (mode) && TARGET_MIX_SSE_I387 && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun)) && reload_completed && (SSE_REG_P (operands[0]) || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(set (match_dup 2) (match_dup 1)) (set (match_dup 0) (float:MODEF (match_dup 2)))]) @@ -5014,15 +4940,15 @@ (set_attr "fp_int_src" "true")]) (define_split - [(set (match_operand:MODEF 0 "register_operand" "") - (float:MODEF (match_operand:SI 1 "register_operand" ""))) - (clobber (match_operand:SI 2 "memory_operand" ""))] + [(set (match_operand:MODEF 0 "register_operand") + (float:MODEF (match_operand:SI 1 "register_operand"))) + (clobber (match_operand:SI 2 "memory_operand"))] "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun) && reload_completed && (SSE_REG_P (operands[0]) || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(const_int 0)] { rtx op1 = operands[1]; @@ -5049,21 +4975,23 @@ emit_insn (gen_sse2_loadld (operands[4], CONST0_RTX (V4SImode), operands[2])); } - emit_insn - (gen_sse2_cvtdq2 (operands[3], operands[4])); + if (mode == V4SFmode) + emit_insn (gen_floatv4siv4sf2 (operands[3], operands[4])); + else + emit_insn (gen_sse2_cvtdq2pd (operands[3], operands[4])); DONE; }) (define_split - [(set (match_operand:MODEF 0 "register_operand" "") - (float:MODEF (match_operand:SI 1 "memory_operand" ""))) - (clobber (match_operand:SI 2 "memory_operand" ""))] + [(set (match_operand:MODEF 0 "register_operand") + (float:MODEF (match_operand:SI 1 "memory_operand"))) + (clobber (match_operand:SI 2 "memory_operand"))] "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun) && reload_completed && (SSE_REG_P (operands[0]) || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(const_int 0)] { operands[3] = simplify_gen_subreg (mode, operands[0], @@ -5072,20 +5000,22 @@ emit_insn (gen_sse2_loadld (operands[4], CONST0_RTX (V4SImode), operands[1])); - emit_insn - (gen_sse2_cvtdq2 (operands[3], operands[4])); + if (mode == V4SFmode) + emit_insn (gen_floatv4siv4sf2 (operands[3], operands[4])); + else + emit_insn (gen_sse2_cvtdq2pd (operands[3], operands[4])); DONE; }) (define_split - [(set (match_operand:MODEF 0 "register_operand" "") - (float:MODEF (match_operand:SI 1 "register_operand" "")))] + [(set (match_operand:MODEF 0 "register_operand") + (float:MODEF (match_operand:SI 1 "register_operand")))] "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun) && reload_completed && (SSE_REG_P (operands[0]) || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(const_int 0)] { rtx op1 = operands[1]; @@ -5116,20 +5046,22 @@ operands[4] = simplify_gen_subreg (V4SImode, operands[1], SImode, 0); else gcc_unreachable (); - emit_insn - (gen_sse2_cvtdq2 (operands[3], operands[4])); + if (mode == V4SFmode) + emit_insn (gen_floatv4siv4sf2 (operands[3], operands[4])); + else + emit_insn (gen_sse2_cvtdq2pd (operands[3], operands[4])); DONE; }) (define_split - [(set (match_operand:MODEF 0 "register_operand" "") - (float:MODEF (match_operand:SI 1 "memory_operand" "")))] + [(set (match_operand:MODEF 0 "register_operand") + (float:MODEF (match_operand:SI 1 "memory_operand")))] "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun) && reload_completed && (SSE_REG_P (operands[0]) || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(const_int 0)] { operands[3] = simplify_gen_subreg (mode, operands[0], @@ -5138,8 +5070,10 @@ emit_insn (gen_sse2_loadld (operands[4], CONST0_RTX (V4SImode), operands[1])); - emit_insn - (gen_sse2_cvtdq2 (operands[3], operands[4])); + if (mode == V4SFmode) + emit_insn (gen_floatv4siv4sf2 (operands[3], operands[4])); + else + emit_insn (gen_sse2_cvtdq2pd (operands[3], operands[4])); DONE; }) @@ -5181,16 +5115,16 @@ (set_attr "fp_int_src" "true")]) (define_split - [(set (match_operand:MODEF 0 "register_operand" "") - (float:MODEF (match_operand:SWI48x 1 "nonimmediate_operand" ""))) - (clobber (match_operand:SWI48x 2 "memory_operand" ""))] + [(set (match_operand:MODEF 0 "register_operand") + (float:MODEF (match_operand:SWI48x 1 "nonimmediate_operand"))) + (clobber (match_operand:SWI48x 2 "memory_operand"))] "(mode != DImode || TARGET_64BIT) && SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH && (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun)) && reload_completed && (SSE_REG_P (operands[0]) || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(set (match_dup 0) (float:MODEF (match_dup 1)))]) (define_insn "*float2_sse_nointerunit" @@ -5216,29 +5150,29 @@ (set_attr "fp_int_src" "true")]) (define_split - [(set (match_operand:MODEF 0 "register_operand" "") - (float:MODEF (match_operand:SWI48x 1 "register_operand" ""))) - (clobber (match_operand:SWI48x 2 "memory_operand" ""))] + [(set (match_operand:MODEF 0 "register_operand") + (float:MODEF (match_operand:SWI48x 1 "register_operand"))) + (clobber (match_operand:SWI48x 2 "memory_operand"))] "(mode != DImode || TARGET_64BIT) && SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun)) && reload_completed && (SSE_REG_P (operands[0]) || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(set (match_dup 2) (match_dup 1)) (set (match_dup 0) (float:MODEF (match_dup 2)))]) (define_split - [(set (match_operand:MODEF 0 "register_operand" "") - (float:MODEF (match_operand:SWI48x 1 "memory_operand" ""))) - (clobber (match_operand:SWI48x 2 "memory_operand" ""))] + [(set (match_operand:MODEF 0 "register_operand") + (float:MODEF (match_operand:SWI48x 1 "memory_operand"))) + (clobber (match_operand:SWI48x 2 "memory_operand"))] "(mode != DImode || TARGET_64BIT) && SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH && reload_completed && (SSE_REG_P (operands[0]) || (GET_CODE (operands[0]) == SUBREG - && SSE_REG_P (operands[0])))" + && SSE_REG_P (SUBREG_REG (operands[0]))))" [(set (match_dup 0) (float:MODEF (match_dup 1)))]) (define_insn "*float2_i387_with_temp" @@ -5268,9 +5202,9 @@ (set_attr "fp_int_src" "true")]) (define_split - [(set (match_operand:X87MODEF 0 "fp_register_operand" "") - (float:X87MODEF (match_operand:SWI48x 1 "register_operand" ""))) - (clobber (match_operand:SWI48x 2 "memory_operand" ""))] + [(set (match_operand:X87MODEF 0 "fp_register_operand") + (float:X87MODEF (match_operand:SWI48x 1 "register_operand"))) + (clobber (match_operand:SWI48x 2 "memory_operand"))] "TARGET_80387 && X87_ENABLE_FLOAT (mode, mode) && reload_completed" @@ -5278,9 +5212,9 @@ (set (match_dup 0) (float:X87MODEF (match_dup 2)))]) (define_split - [(set (match_operand:X87MODEF 0 "fp_register_operand" "") - (float:X87MODEF (match_operand:SWI48x 1 "memory_operand" ""))) - (clobber (match_operand:SWI48x 2 "memory_operand" ""))] + [(set (match_operand:X87MODEF 0 "fp_register_operand") + (float:X87MODEF (match_operand:SWI48x 1 "memory_operand"))) + (clobber (match_operand:SWI48x 2 "memory_operand"))] "TARGET_80387 && X87_ENABLE_FLOAT (mode, mode) && reload_completed" @@ -5306,11 +5240,11 @@ (set_attr "fp_int_src" "true")]) (define_split - [(set (match_operand:X87MODEF 0 "fp_register_operand" "") - (float:X87MODEF (match_operand:DI 1 "register_operand" ""))) - (clobber (match_scratch:V4SI 3 "")) - (clobber (match_scratch:V4SI 4 "")) - (clobber (match_operand:DI 2 "memory_operand" ""))] + [(set (match_operand:X87MODEF 0 "fp_register_operand") + (float:X87MODEF (match_operand:DI 1 "register_operand"))) + (clobber (match_scratch:V4SI 3)) + (clobber (match_scratch:V4SI 4)) + (clobber (match_operand:DI 2 "memory_operand"))] "TARGET_80387 && X87_ENABLE_FLOAT (mode, DImode) && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES && !TARGET_64BIT && optimize_function_for_speed_p (cfun) @@ -5331,11 +5265,11 @@ }) (define_split - [(set (match_operand:X87MODEF 0 "fp_register_operand" "") - (float:X87MODEF (match_operand:DI 1 "memory_operand" ""))) - (clobber (match_scratch:V4SI 3 "")) - (clobber (match_scratch:V4SI 4 "")) - (clobber (match_operand:DI 2 "memory_operand" ""))] + [(set (match_operand:X87MODEF 0 "fp_register_operand") + (float:X87MODEF (match_operand:DI 1 "memory_operand"))) + (clobber (match_scratch:V4SI 3)) + (clobber (match_scratch:V4SI 4)) + (clobber (match_operand:DI 2 "memory_operand"))] "TARGET_80387 && X87_ENABLE_FLOAT (mode, DImode) && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES && !TARGET_64BIT && optimize_function_for_speed_p (cfun) @@ -5362,11 +5296,11 @@ (set_attr "mode" "")]) (define_split - [(set (match_operand:X87MODEF 0 "register_operand" "") + [(set (match_operand:X87MODEF 0 "register_operand") (unsigned_float:X87MODEF - (match_operand:SI 1 "register_operand" ""))) - (clobber (match_operand:DI 2 "memory_operand" "")) - (clobber (match_scratch:SI 3 ""))] + (match_operand:SI 1 "register_operand"))) + (clobber (match_operand:DI 2 "memory_operand")) + (clobber (match_scratch:SI 3))] "!TARGET_64BIT && TARGET_80387 && X87_ENABLE_FLOAT (mode, DImode) && TARGET_SSE @@ -5377,11 +5311,11 @@ "operands[1] = simplify_gen_subreg (DImode, operands[1], SImode, 0);") (define_split - [(set (match_operand:X87MODEF 0 "register_operand" "") + [(set (match_operand:X87MODEF 0 "register_operand") (unsigned_float:X87MODEF - (match_operand:SI 1 "memory_operand" ""))) - (clobber (match_operand:DI 2 "memory_operand" "")) - (clobber (match_scratch:SI 3 ""))] + (match_operand:SI 1 "memory_operand"))) + (clobber (match_operand:DI 2 "memory_operand")) + (clobber (match_scratch:SI 3))] "!TARGET_64BIT && TARGET_80387 && X87_ENABLE_FLOAT (mode, DImode) && TARGET_SSE @@ -5396,11 +5330,11 @@ (define_expand "floatunssi2" [(parallel - [(set (match_operand:X87MODEF 0 "register_operand" "") + [(set (match_operand:X87MODEF 0 "register_operand") (unsigned_float:X87MODEF - (match_operand:SI 1 "nonimmediate_operand" ""))) + (match_operand:SI 1 "nonimmediate_operand"))) (clobber (match_dup 2)) - (clobber (match_scratch:SI 3 ""))])] + (clobber (match_scratch:SI 3))])] "!TARGET_64BIT && ((TARGET_80387 && X87_ENABLE_FLOAT (mode, DImode) && TARGET_SSE) @@ -5421,14 +5355,14 @@ }) (define_expand "floatunsdisf2" - [(use (match_operand:SF 0 "register_operand" "")) - (use (match_operand:DI 1 "nonimmediate_operand" ""))] + [(use (match_operand:SF 0 "register_operand")) + (use (match_operand:DI 1 "nonimmediate_operand"))] "TARGET_64BIT && TARGET_SSE_MATH" "x86_emit_floatuns (operands); DONE;") (define_expand "floatunsdidf2" - [(use (match_operand:DF 0 "register_operand" "")) - (use (match_operand:DI 1 "nonimmediate_operand" ""))] + [(use (match_operand:DF 0 "register_operand")) + (use (match_operand:DI 1 "nonimmediate_operand"))] "(TARGET_64BIT || TARGET_KEEPS_VECTOR_ALIGNED_STACK) && TARGET_SSE2 && TARGET_SSE_MATH" { @@ -5442,9 +5376,9 @@ ;; Add instructions (define_expand "add3" - [(set (match_operand:SDWIM 0 "nonimmediate_operand" "") - (plus:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand" "") - (match_operand:SDWIM 2 "" "")))] + [(set (match_operand:SDWIM 0 "nonimmediate_operand") + (plus:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand") + (match_operand:SDWIM 2 "")))] "" "ix86_expand_binary_operator (PLUS, mode, operands); DONE;") @@ -5501,7 +5435,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (subreg:SI (match_operand:DI 1 "lea_address_operand" "p") 0))] "TARGET_64BIT" - "lea{l}\t{%a1, %0|%0, %a1}" + "lea{l}\t{%E1, %0|%0, %E1}" "&& reload_completed && ix86_avoid_lea_for_addr (insn, operands)" [(const_int 0)] { @@ -5515,7 +5449,7 @@ [(set (match_operand:SWI48 0 "register_operand" "=r") (match_operand:SWI48 1 "lea_address_operand" "p"))] "" - "lea{}\t{%a1, %0|%0, %a1}" + "lea{}\t{%E1, %0|%0, %E1}" "reload_completed && ix86_avoid_lea_for_addr (insn, operands)" [(const_int 0)] { @@ -5528,18 +5462,18 @@ (define_insn "*lea_3_zext" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI - (subreg:SI (match_operand:DI 1 "lea_address_operand" "p") 0)))] + (subreg:SI (match_operand:DI 1 "lea_address_operand" "j") 0)))] "TARGET_64BIT" - "lea{l}\t{%a1, %k0|%k0, %a1}" + "lea{l}\t{%E1, %k0|%k0, %E1}" [(set_attr "type" "lea") (set_attr "mode" "SI")]) (define_insn "*lea_4_zext" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI - (match_operand:SI 1 "lea_address_operand" "p")))] + (match_operand:SI 1 "lea_address_operand" "j")))] "TARGET_64BIT" - "lea{l}\t{%a1, %k0|%k0, %a1}" + "lea{l}\t{%E1, %k0|%k0, %E1}" [(set_attr "type" "lea") (set_attr "mode" "SI")]) @@ -5549,7 +5483,7 @@ (subreg:DI (match_operand:SI 1 "lea_address_operand" "p") 0) (match_operand:DI 2 "const_32bit_mask" "n")))] "TARGET_64BIT" - "lea{l}\t{%a1, %k0|%k0, %a1}" + "lea{l}\t{%E1, %k0|%k0, %E1}" [(set_attr "type" "lea") (set_attr "mode" "SI")]) @@ -5559,7 +5493,7 @@ (match_operand:DI 1 "lea_address_operand" "p") (match_operand:DI 2 "const_32bit_mask" "n")))] "TARGET_64BIT" - "lea{l}\t{%a1, %k0|%k0, %a1}" + "lea{l}\t{%E1, %k0|%k0, %E1}" [(set_attr "type" "lea") (set_attr "mode" "SI")]) @@ -5605,13 +5539,13 @@ [(set (attr "type") (cond [(eq_attr "alternative" "3") (const_string "lea") - (match_operand:SWI48 2 "incdec_operand" "") + (match_operand:SWI48 2 "incdec_operand") (const_string "incdec") ] (const_string "alu"))) (set (attr "length_immediate") (if_then_else - (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" "")) + (and (eq_attr "type" "alu") (match_operand 2 "const128_operand")) (const_string "1") (const_string "*"))) (set_attr "mode" "")]) @@ -5662,13 +5596,13 @@ [(set (attr "type") (cond [(eq_attr "alternative" "2") (const_string "lea") - (match_operand:SI 2 "incdec_operand" "") + (match_operand:SI 2 "incdec_operand") (const_string "incdec") ] (const_string "alu"))) (set (attr "length_immediate") (if_then_else - (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" "")) + (and (eq_attr "type" "alu") (match_operand 2 "const128_operand")) (const_string "1") (const_string "*"))) (set_attr "mode" "SI")]) @@ -5714,13 +5648,13 @@ [(set (attr "type") (cond [(eq_attr "alternative" "3") (const_string "lea") - (match_operand:HI 2 "incdec_operand" "") + (match_operand:HI 2 "incdec_operand") (const_string "incdec") ] (const_string "alu"))) (set (attr "length_immediate") (if_then_else - (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" "")) + (and (eq_attr "type" "alu") (match_operand 2 "const128_operand")) (const_string "1") (const_string "*"))) (set_attr "mode" "HI,HI,HI,SI")]) @@ -5776,13 +5710,13 @@ [(set (attr "type") (cond [(eq_attr "alternative" "5") (const_string "lea") - (match_operand:QI 2 "incdec_operand" "") + (match_operand:QI 2 "incdec_operand") (const_string "incdec") ] (const_string "alu"))) (set (attr "length_immediate") (if_then_else - (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" "")) + (and (eq_attr "type" "alu") (match_operand 2 "const128_operand")) (const_string "1") (const_string "*"))) (set_attr "mode" "QI,QI,QI,SI,SI,SI")]) @@ -5814,20 +5748,20 @@ } } [(set (attr "type") - (if_then_else (match_operand:QI 1 "incdec_operand" "") + (if_then_else (match_operand:QI 1 "incdec_operand") (const_string "incdec") (const_string "alu1"))) (set (attr "memory") - (if_then_else (match_operand 1 "memory_operand" "") + (if_then_else (match_operand 1 "memory_operand") (const_string "load") (const_string "none"))) (set_attr "mode" "QI")]) ;; Split non destructive adds if we cannot use lea. (define_split - [(set (match_operand:SWI48 0 "register_operand" "") - (plus:SWI48 (match_operand:SWI48 1 "register_operand" "") - (match_operand:SWI48 2 "nonmemory_operand" ""))) + [(set (match_operand:SWI48 0 "register_operand") + (plus:SWI48 (match_operand:SWI48 1 "register_operand") + (match_operand:SWI48 2 "nonmemory_operand"))) (clobber (reg:CC FLAGS_REG))] "reload_completed && ix86_avoid_lea_for_add (insn, operands)" [(set (match_dup 0) (match_dup 1)) @@ -5836,9 +5770,9 @@ ;; Convert add to the lea pattern to avoid flags dependency. (define_split - [(set (match_operand:SWI 0 "register_operand" "") - (plus:SWI (match_operand:SWI 1 "register_operand" "") - (match_operand:SWI 2 "" ""))) + [(set (match_operand:SWI 0 "register_operand") + (plus:SWI (match_operand:SWI 1 "register_operand") + (match_operand:SWI 2 ""))) (clobber (reg:CC FLAGS_REG))] "reload_completed && ix86_lea_for_add_ok (insn, operands)" [(const_int 0)] @@ -5862,10 +5796,10 @@ ;; Convert add to the lea pattern to avoid flags dependency. (define_split - [(set (match_operand:DI 0 "register_operand" "") + [(set (match_operand:DI 0 "register_operand") (zero_extend:DI - (plus:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "x86_64_nonmemory_operand" "")))) + (plus:SI (match_operand:SI 1 "register_operand") + (match_operand:SI 2 "x86_64_nonmemory_operand")))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && reload_completed && ix86_lea_for_add_ok (insn, operands)" [(set (match_dup 0) @@ -5902,12 +5836,12 @@ } } [(set (attr "type") - (if_then_else (match_operand:SWI 2 "incdec_operand" "") + (if_then_else (match_operand:SWI 2 "incdec_operand") (const_string "incdec") (const_string "alu"))) (set (attr "length_immediate") (if_then_else - (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" "")) + (and (eq_attr "type" "alu") (match_operand 2 "const128_operand")) (const_string "1") (const_string "*"))) (set_attr "mode" "")]) @@ -5943,12 +5877,12 @@ } } [(set (attr "type") - (if_then_else (match_operand:SI 2 "incdec_operand" "") + (if_then_else (match_operand:SI 2 "incdec_operand") (const_string "incdec") (const_string "alu"))) (set (attr "length_immediate") (if_then_else - (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" "")) + (and (eq_attr "type" "alu") (match_operand 2 "const128_operand")) (const_string "1") (const_string "*"))) (set_attr "mode" "SI")]) @@ -5981,12 +5915,12 @@ } } [(set (attr "type") - (if_then_else (match_operand:SWI 2 "incdec_operand" "") + (if_then_else (match_operand:SWI 2 "incdec_operand") (const_string "incdec") (const_string "alu"))) (set (attr "length_immediate") (if_then_else - (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" "")) + (and (eq_attr "type" "alu") (match_operand 2 "const128_operand")) (const_string "1") (const_string "*"))) (set_attr "mode" "")]) @@ -6021,12 +5955,12 @@ } } [(set (attr "type") - (if_then_else (match_operand:SI 2 "incdec_operand" "") + (if_then_else (match_operand:SI 2 "incdec_operand") (const_string "incdec") (const_string "alu"))) (set (attr "length_immediate") (if_then_else - (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" "")) + (and (eq_attr "type" "alu") (match_operand 2 "const128_operand")) (const_string "1") (const_string "*"))) (set_attr "mode" "SI")]) @@ -6066,12 +6000,12 @@ } } [(set (attr "type") - (if_then_else (match_operand:DI 2 "incdec_operand" "") + (if_then_else (match_operand:DI 2 "incdec_operand") (const_string "incdec") (const_string "alu"))) (set (attr "length_immediate") (if_then_else - (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" "")) + (and (eq_attr "type" "alu") (match_operand 2 "const128_operand")) (const_string "1") (const_string "*"))) (set_attr "mode" "DI")]) @@ -6110,12 +6044,12 @@ } } [(set (attr "type") - (if_then_else (match_operand: 2 "incdec_operand" "") + (if_then_else (match_operand: 2 "incdec_operand") (const_string "incdec") (const_string "alu"))) (set (attr "length_immediate") (if_then_else - (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" "")) + (and (eq_attr "type" "alu") (match_operand 2 "const128_operand")) (const_string "1") (const_string "*"))) (set_attr "mode" "")]) @@ -6150,12 +6084,12 @@ } } [(set (attr "type") - (if_then_else (match_operand:SWI 2 "incdec_operand" "") + (if_then_else (match_operand:SWI 2 "incdec_operand") (const_string "incdec") (const_string "alu"))) (set (attr "length_immediate") (if_then_else - (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" "")) + (and (eq_attr "type" "alu") (match_operand 2 "const128_operand")) (const_string "1") (const_string "*"))) (set_attr "mode" "")]) @@ -6189,7 +6123,7 @@ } } [(set (attr "type") - (if_then_else (match_operand:QI 2 "incdec_operand" "") + (if_then_else (match_operand:QI 2 "incdec_operand") (const_string "incdec") (const_string "alu"))) (set_attr "modrm" "1") @@ -6224,7 +6158,7 @@ } } [(set (attr "type") - (if_then_else (match_operand:QI 2 "incdec_operand" "") + (if_then_else (match_operand:QI 2 "incdec_operand") (const_string "incdec") (const_string "alu"))) (set_attr "modrm" "1") @@ -6387,16 +6321,16 @@ } [(set_attr "type" "lea") (set (attr "mode") - (if_then_else (match_operand:DI 0 "" "") + (if_then_else (match_operand:DI 0) (const_string "DI") (const_string "SI")))]) ;; Subtract instructions (define_expand "sub3" - [(set (match_operand:SDWIM 0 "nonimmediate_operand" "") - (minus:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand" "") - (match_operand:SDWIM 2 "" "")))] + [(set (match_operand:SDWIM 0 "nonimmediate_operand") + (minus:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand") + (match_operand:SDWIM 2 "")))] "" "ix86_expand_binary_operator (MINUS, mode, operands); DONE;") @@ -6516,13 +6450,13 @@ (define_expand "3_carry" [(parallel - [(set (match_operand:SWI 0 "nonimmediate_operand" "") + [(set (match_operand:SWI 0 "nonimmediate_operand") (plusminus:SWI - (match_operand:SWI 1 "nonimmediate_operand" "") + (match_operand:SWI 1 "nonimmediate_operand") (plus:SWI (match_operator:SWI 4 "ix86_carry_flag_operator" - [(match_operand 3 "flags_reg_operand" "") + [(match_operand 3 "flags_reg_operand") (const_int 0)]) - (match_operand:SWI 2 "" "")))) + (match_operand:SWI 2 "")))) (clobber (reg:CC FLAGS_REG))])] "ix86_binary_operator_ok (, mode, operands)") @@ -6629,34 +6563,34 @@ ;; The patterns that match these are at the end of this file. (define_expand "xf3" - [(set (match_operand:XF 0 "register_operand" "") + [(set (match_operand:XF 0 "register_operand") (plusminus:XF - (match_operand:XF 1 "register_operand" "") - (match_operand:XF 2 "register_operand" "")))] + (match_operand:XF 1 "register_operand") + (match_operand:XF 2 "register_operand")))] "TARGET_80387") (define_expand "3" - [(set (match_operand:MODEF 0 "register_operand" "") + [(set (match_operand:MODEF 0 "register_operand") (plusminus:MODEF - (match_operand:MODEF 1 "register_operand" "") - (match_operand:MODEF 2 "nonimmediate_operand" "")))] + (match_operand:MODEF 1 "register_operand") + (match_operand:MODEF 2 "nonimmediate_operand")))] "(TARGET_80387 && X87_ENABLE_ARITH (mode)) || (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)") ;; Multiply instructions (define_expand "mul3" - [(parallel [(set (match_operand:SWIM248 0 "register_operand" "") + [(parallel [(set (match_operand:SWIM248 0 "register_operand") (mult:SWIM248 - (match_operand:SWIM248 1 "register_operand" "") - (match_operand:SWIM248 2 "" ""))) + (match_operand:SWIM248 1 "register_operand") + (match_operand:SWIM248 2 ""))) (clobber (reg:CC FLAGS_REG))])]) (define_expand "mulqi3" - [(parallel [(set (match_operand:QI 0 "register_operand" "") + [(parallel [(set (match_operand:QI 0 "register_operand") (mult:QI - (match_operand:QI 1 "register_operand" "") - (match_operand:QI 2 "nonimmediate_operand" ""))) + (match_operand:QI 1 "register_operand") + (match_operand:QI 2 "nonimmediate_operand"))) (clobber (reg:CC FLAGS_REG))])] "TARGET_QIMODE_MATH") @@ -6689,12 +6623,12 @@ (eq_attr "alternative" "1") (const_string "vector") (and (eq_attr "alternative" "2") - (match_operand 1 "memory_operand" "")) + (match_operand 1 "memory_operand")) (const_string "vector")] (const_string "direct"))) (set (attr "amdfam10_decode") (cond [(and (eq_attr "alternative" "0,1") - (match_operand 1 "memory_operand" "")) + (match_operand 1 "memory_operand")) (const_string "vector")] (const_string "direct"))) (set_attr "bdver1_decode" "direct") @@ -6720,12 +6654,12 @@ (eq_attr "alternative" "1") (const_string "vector") (and (eq_attr "alternative" "2") - (match_operand 1 "memory_operand" "")) + (match_operand 1 "memory_operand")) (const_string "vector")] (const_string "direct"))) (set (attr "amdfam10_decode") (cond [(and (eq_attr "alternative" "0,1") - (match_operand 1 "memory_operand" "")) + (match_operand 1 "memory_operand")) (const_string "vector")] (const_string "direct"))) (set_attr "bdver1_decode" "direct") @@ -6790,21 +6724,21 @@ (set_attr "mode" "QI")]) (define_expand "mul3" - [(parallel [(set (match_operand: 0 "register_operand" "") + [(parallel [(set (match_operand: 0 "register_operand") (mult: (any_extend: - (match_operand:DWIH 1 "nonimmediate_operand" "")) + (match_operand:DWIH 1 "nonimmediate_operand")) (any_extend: - (match_operand:DWIH 2 "register_operand" "")))) + (match_operand:DWIH 2 "register_operand")))) (clobber (reg:CC FLAGS_REG))])]) (define_expand "mulqihi3" - [(parallel [(set (match_operand:HI 0 "register_operand" "") + [(parallel [(set (match_operand:HI 0 "register_operand") (mult:HI (any_extend:HI - (match_operand:QI 1 "nonimmediate_operand" "")) + (match_operand:QI 1 "nonimmediate_operand")) (any_extend:HI - (match_operand:QI 2 "register_operand" "")))) + (match_operand:QI 2 "register_operand")))) (clobber (reg:CC FLAGS_REG))])] "TARGET_QIMODE_MATH") @@ -6872,12 +6806,12 @@ ;; Convert mul to the mulx pattern to avoid flags dependency. (define_split - [(set (match_operand: 0 "register_operand" "") + [(set (match_operand: 0 "register_operand") (mult: (zero_extend: - (match_operand:DWIH 1 "register_operand" "")) + (match_operand:DWIH 1 "register_operand")) (zero_extend: - (match_operand:DWIH 2 "nonimmediate_operand" "")))) + (match_operand:DWIH 2 "nonimmediate_operand")))) (clobber (reg:CC FLAGS_REG))] "TARGET_BMI2 && reload_completed && true_regnum (operands[1]) == DX_REG" @@ -6937,16 +6871,16 @@ (set_attr "mode" "QI")]) (define_expand "mul3_highpart" - [(parallel [(set (match_operand:SWI48 0 "register_operand" "") + [(parallel [(set (match_operand:SWI48 0 "register_operand") (truncate:SWI48 (lshiftrt: (mult: (any_extend: - (match_operand:SWI48 1 "nonimmediate_operand" "")) + (match_operand:SWI48 1 "nonimmediate_operand")) (any_extend: - (match_operand:SWI48 2 "register_operand" ""))) + (match_operand:SWI48 2 "register_operand"))) (match_dup 4)))) - (clobber (match_scratch:SWI48 3 "")) + (clobber (match_scratch:SWI48 3)) (clobber (reg:CC FLAGS_REG))])] "" "operands[4] = GEN_INT (GET_MODE_BITSIZE (mode));") @@ -7027,15 +6961,15 @@ ;; The patterns that match these are at the end of this file. (define_expand "mulxf3" - [(set (match_operand:XF 0 "register_operand" "") - (mult:XF (match_operand:XF 1 "register_operand" "") - (match_operand:XF 2 "register_operand" "")))] + [(set (match_operand:XF 0 "register_operand") + (mult:XF (match_operand:XF 1 "register_operand") + (match_operand:XF 2 "register_operand")))] "TARGET_80387") (define_expand "mul3" - [(set (match_operand:MODEF 0 "register_operand" "") - (mult:MODEF (match_operand:MODEF 1 "register_operand" "") - (match_operand:MODEF 2 "nonimmediate_operand" "")))] + [(set (match_operand:MODEF 0 "register_operand") + (mult:MODEF (match_operand:MODEF 1 "register_operand") + (match_operand:MODEF 2 "nonimmediate_operand")))] "(TARGET_80387 && X87_ENABLE_ARITH (mode)) || (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)") @@ -7044,22 +6978,22 @@ ;; The patterns that match these are at the end of this file. (define_expand "divxf3" - [(set (match_operand:XF 0 "register_operand" "") - (div:XF (match_operand:XF 1 "register_operand" "") - (match_operand:XF 2 "register_operand" "")))] + [(set (match_operand:XF 0 "register_operand") + (div:XF (match_operand:XF 1 "register_operand") + (match_operand:XF 2 "register_operand")))] "TARGET_80387") (define_expand "divdf3" - [(set (match_operand:DF 0 "register_operand" "") - (div:DF (match_operand:DF 1 "register_operand" "") - (match_operand:DF 2 "nonimmediate_operand" "")))] + [(set (match_operand:DF 0 "register_operand") + (div:DF (match_operand:DF 1 "register_operand") + (match_operand:DF 2 "nonimmediate_operand")))] "(TARGET_80387 && X87_ENABLE_ARITH (DFmode)) || (TARGET_SSE2 && TARGET_SSE_MATH)") (define_expand "divsf3" - [(set (match_operand:SF 0 "register_operand" "") - (div:SF (match_operand:SF 1 "register_operand" "") - (match_operand:SF 2 "nonimmediate_operand" "")))] + [(set (match_operand:SF 0 "register_operand") + (div:SF (match_operand:SF 1 "register_operand") + (match_operand:SF 2 "nonimmediate_operand")))] "(TARGET_80387 && X87_ENABLE_ARITH (SFmode)) || TARGET_SSE_MATH" { @@ -7078,11 +7012,11 @@ ;; Divmod instructions. (define_expand "divmod4" - [(parallel [(set (match_operand:SWIM248 0 "register_operand" "") + [(parallel [(set (match_operand:SWIM248 0 "register_operand") (div:SWIM248 - (match_operand:SWIM248 1 "register_operand" "") - (match_operand:SWIM248 2 "nonimmediate_operand" ""))) - (set (match_operand:SWIM248 3 "register_operand" "") + (match_operand:SWIM248 1 "register_operand") + (match_operand:SWIM248 2 "nonimmediate_operand"))) + (set (match_operand:SWIM248 3 "register_operand") (mod:SWIM248 (match_dup 1) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])]) @@ -7092,10 +7026,10 @@ ;; else ;; use original integer divide (define_split - [(set (match_operand:SWI48 0 "register_operand" "") - (div:SWI48 (match_operand:SWI48 2 "register_operand" "") - (match_operand:SWI48 3 "nonimmediate_operand" ""))) - (set (match_operand:SWI48 1 "register_operand" "") + [(set (match_operand:SWI48 0 "register_operand") + (div:SWI48 (match_operand:SWI48 2 "register_operand") + (match_operand:SWI48 3 "nonimmediate_operand"))) + (set (match_operand:SWI48 1 "register_operand") (mod:SWI48 (match_dup 2) (match_dup 3))) (clobber (reg:CC FLAGS_REG))] "TARGET_USE_8BIT_IDIV @@ -7189,11 +7123,11 @@ (set_attr "mode" "")]) (define_expand "divmodqi4" - [(parallel [(set (match_operand:QI 0 "register_operand" "") + [(parallel [(set (match_operand:QI 0 "register_operand") (div:QI - (match_operand:QI 1 "register_operand" "") - (match_operand:QI 2 "nonimmediate_operand" ""))) - (set (match_operand:QI 3 "register_operand" "") + (match_operand:QI 1 "register_operand") + (match_operand:QI 2 "nonimmediate_operand"))) + (set (match_operand:QI 3 "register_operand") (mod:QI (match_dup 1) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] "TARGET_QIMODE_MATH" @@ -7251,11 +7185,11 @@ (set_attr "mode" "QI")]) (define_expand "udivmod4" - [(parallel [(set (match_operand:SWIM248 0 "register_operand" "") + [(parallel [(set (match_operand:SWIM248 0 "register_operand") (udiv:SWIM248 - (match_operand:SWIM248 1 "register_operand" "") - (match_operand:SWIM248 2 "nonimmediate_operand" ""))) - (set (match_operand:SWIM248 3 "register_operand" "") + (match_operand:SWIM248 1 "register_operand") + (match_operand:SWIM248 2 "nonimmediate_operand"))) + (set (match_operand:SWIM248 3 "register_operand") (umod:SWIM248 (match_dup 1) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])]) @@ -7265,10 +7199,10 @@ ;; else ;; use original integer divide (define_split - [(set (match_operand:SWI48 0 "register_operand" "") - (udiv:SWI48 (match_operand:SWI48 2 "register_operand" "") - (match_operand:SWI48 3 "nonimmediate_operand" ""))) - (set (match_operand:SWI48 1 "register_operand" "") + [(set (match_operand:SWI48 0 "register_operand") + (udiv:SWI48 (match_operand:SWI48 2 "register_operand") + (match_operand:SWI48 3 "nonimmediate_operand"))) + (set (match_operand:SWI48 1 "register_operand") (umod:SWI48 (match_dup 2) (match_dup 3))) (clobber (reg:CC FLAGS_REG))] "TARGET_USE_8BIT_IDIV @@ -7335,11 +7269,11 @@ (set_attr "mode" "")]) (define_expand "udivmodqi4" - [(parallel [(set (match_operand:QI 0 "register_operand" "") + [(parallel [(set (match_operand:QI 0 "register_operand") (udiv:QI - (match_operand:QI 1 "register_operand" "") - (match_operand:QI 2 "nonimmediate_operand" ""))) - (set (match_operand:QI 3 "register_operand" "") + (match_operand:QI 1 "register_operand") + (match_operand:QI 2 "nonimmediate_operand"))) + (set (match_operand:QI 3 "register_operand") (umod:QI (match_dup 1) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] "TARGET_QIMODE_MATH" @@ -7418,21 +7352,21 @@ (define_expand "testsi_ccno_1" [(set (reg:CCNO FLAGS_REG) (compare:CCNO - (and:SI (match_operand:SI 0 "nonimmediate_operand" "") - (match_operand:SI 1 "x86_64_nonmemory_operand" "")) + (and:SI (match_operand:SI 0 "nonimmediate_operand") + (match_operand:SI 1 "x86_64_nonmemory_operand")) (const_int 0)))]) (define_expand "testqi_ccz_1" [(set (reg:CCZ FLAGS_REG) - (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "") - (match_operand:QI 1 "nonmemory_operand" "")) + (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand") + (match_operand:QI 1 "nonmemory_operand")) (const_int 0)))]) (define_expand "testdi_ccno_1" [(set (reg:CCNO FLAGS_REG) (compare:CCNO - (and:DI (match_operand:DI 0 "nonimmediate_operand" "") - (match_operand:DI 1 "x86_64_szext_general_operand" "")) + (and:DI (match_operand:DI 0 "nonimmediate_operand") + (match_operand:DI 1 "x86_64_szext_general_operand")) (const_int 0)))] "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))") @@ -7500,10 +7434,10 @@ (compare:CCNO (and:SI (zero_extract:SI - (match_operand 0 "ext_register_operand" "") + (match_operand 0 "ext_register_operand") (const_int 8) (const_int 8)) - (match_operand 1 "const_int_operand" "")) + (match_operand 1 "const_int_operand")) (const_int 0)))]) (define_insn "*testqi_ext_0" @@ -7578,8 +7512,8 @@ [(set (reg FLAGS_REG) (compare (zero_extract:DI (match_operand 0 "nonimmediate_operand" "rm") - (match_operand:DI 1 "const_int_operand" "") - (match_operand:DI 2 "const_int_operand" "")) + (match_operand:DI 1 "const_int_operand") + (match_operand:DI 2 "const_int_operand")) (const_int 0)))] "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) @@ -7600,8 +7534,8 @@ [(set (reg FLAGS_REG) (compare (zero_extract:SI (match_operand 0 "nonimmediate_operand" "rm") - (match_operand:SI 1 "const_int_operand" "") - (match_operand:SI 2 "const_int_operand" "")) + (match_operand:SI 1 "const_int_operand") + (match_operand:SI 2 "const_int_operand")) (const_int 0)))] "ix86_match_ccmode (insn, CCNOmode) && INTVAL (operands[1]) > 0 @@ -7614,12 +7548,12 @@ "#") (define_split - [(set (match_operand 0 "flags_reg_operand" "") + [(set (match_operand 0 "flags_reg_operand") (match_operator 1 "compare_operator" [(zero_extract - (match_operand 2 "nonimmediate_operand" "") - (match_operand 3 "const_int_operand" "") - (match_operand 4 "const_int_operand" "")) + (match_operand 2 "nonimmediate_operand") + (match_operand 3 "const_int_operand") + (match_operand 4 "const_int_operand")) (const_int 0)]))] "ix86_match_ccmode (insn, CCNOmode)" [(set (match_dup 0) (match_op_dup 1 [(match_dup 2) (const_int 0)]))] @@ -7673,10 +7607,10 @@ ;; Do the conversion only post-reload to avoid limiting of the register class ;; to QI regs. (define_split - [(set (match_operand 0 "flags_reg_operand" "") + [(set (match_operand 0 "flags_reg_operand") (match_operator 1 "compare_operator" - [(and (match_operand 2 "register_operand" "") - (match_operand 3 "const_int_operand" "")) + [(and (match_operand 2 "register_operand") + (match_operand 3 "const_int_operand")) (const_int 0)]))] "reload_completed && QI_REG_P (operands[2]) @@ -7690,14 +7624,16 @@ [(and:SI (zero_extract:SI (match_dup 2) (const_int 8) (const_int 8)) (match_dup 3)) (const_int 0)]))] - "operands[2] = gen_lowpart (SImode, operands[2]); - operands[3] = gen_int_mode (INTVAL (operands[3]) >> 8, SImode);") +{ + operands[2] = gen_lowpart (SImode, operands[2]); + operands[3] = gen_int_mode (INTVAL (operands[3]) >> 8, SImode); +}) (define_split - [(set (match_operand 0 "flags_reg_operand" "") + [(set (match_operand 0 "flags_reg_operand") (match_operator 1 "compare_operator" - [(and (match_operand 2 "nonimmediate_operand" "") - (match_operand 3 "const_int_operand" "")) + [(and (match_operand 2 "nonimmediate_operand") + (match_operand 3 "const_int_operand")) (const_int 0)]))] "reload_completed && GET_MODE (operands[2]) != QImode @@ -7709,17 +7645,19 @@ [(set (match_dup 0) (match_op_dup 1 [(and:QI (match_dup 2) (match_dup 3)) (const_int 0)]))] - "operands[2] = gen_lowpart (QImode, operands[2]); - operands[3] = gen_lowpart (QImode, operands[3]);") +{ + operands[2] = gen_lowpart (QImode, operands[2]); + operands[3] = gen_lowpart (QImode, operands[3]); +}) ;; %%% This used to optimize known byte-wide and operations to memory, ;; and sometimes to QImode registers. If this is considered useful, ;; it should be done with splitters. (define_expand "and3" - [(set (match_operand:SWIM 0 "nonimmediate_operand" "") - (and:SWIM (match_operand:SWIM 1 "nonimmediate_operand" "") - (match_operand:SWIM 2 "" "")))] + [(set (match_operand:SWIM 0 "nonimmediate_operand") + (and:SWIM (match_operand:SWIM 1 "nonimmediate_operand") + (match_operand:SWIM 2 "")))] "" "ix86_expand_binary_operator (AND, mode, operands); DONE;") @@ -7734,24 +7672,7 @@ switch (get_attr_type (insn)) { case TYPE_IMOVX: - { - enum machine_mode mode; - - gcc_assert (CONST_INT_P (operands[2])); - if (INTVAL (operands[2]) == 0xff) - mode = QImode; - else - { - gcc_assert (INTVAL (operands[2]) == 0xffff); - mode = HImode; - } - - operands[1] = gen_lowpart (mode, operands[1]); - if (mode == QImode) - return "movz{bl|x}\t{%1, %k0|%k0, %1}"; - else - return "movz{wl|x}\t{%1, %k0|%k0, %1}"; - } + return "#"; default: gcc_assert (rtx_equal_p (operands[0], operands[1])); @@ -7767,13 +7688,13 @@ (if_then_else (and (eq_attr "type" "imovx") (and (match_test "INTVAL (operands[2]) == 0xff") - (match_operand 1 "ext_QIreg_operand" ""))) + (match_operand 1 "ext_QIreg_operand"))) (const_string "1") (const_string "*"))) (set_attr "mode" "SI,DI,DI,SI")]) (define_insn "*andsi_1" - [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r") + [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,Ya") (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm") (match_operand:SI 2 "x86_64_general_operand" "re,rm,L"))) (clobber (reg:CC FLAGS_REG))] @@ -7782,24 +7703,7 @@ switch (get_attr_type (insn)) { case TYPE_IMOVX: - { - enum machine_mode mode; - - gcc_assert (CONST_INT_P (operands[2])); - if (INTVAL (operands[2]) == 0xff) - mode = QImode; - else - { - gcc_assert (INTVAL (operands[2]) == 0xffff); - mode = HImode; - } - - operands[1] = gen_lowpart (mode, operands[1]); - if (mode == QImode) - return "movz{bl|x}\t{%1, %0|%0, %1}"; - else - return "movz{wl|x}\t{%1, %0|%0, %1}"; - } + return "#"; default: gcc_assert (rtx_equal_p (operands[0], operands[1])); @@ -7811,7 +7715,7 @@ (if_then_else (and (eq_attr "type" "imovx") (and (match_test "INTVAL (operands[2]) == 0xff") - (match_operand 1 "ext_QIreg_operand" ""))) + (match_operand 1 "ext_QIreg_operand"))) (const_string "1") (const_string "*"))) (set_attr "length_immediate" "*,*,0") @@ -7830,7 +7734,7 @@ (set_attr "mode" "SI")]) (define_insn "*andhi_1" - [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r") + [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,Ya") (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm") (match_operand:HI 2 "general_operand" "rn,rm,L"))) (clobber (reg:CC FLAGS_REG))] @@ -7839,13 +7743,10 @@ switch (get_attr_type (insn)) { case TYPE_IMOVX: - gcc_assert (CONST_INT_P (operands[2])); - gcc_assert (INTVAL (operands[2]) == 0xff); - return "movz{bl|x}\t{%b1, %k0|%k0, %b1}"; + return "#"; default: gcc_assert (rtx_equal_p (operands[0], operands[1])); - return "and{w}\t{%2, %0|%0, %2}"; } } @@ -7854,7 +7755,7 @@ (set (attr "prefix_rex") (if_then_else (and (eq_attr "type" "imovx") - (match_operand 1 "ext_QIreg_operand" "")) + (match_operand 1 "ext_QIreg_operand")) (const_string "1") (const_string "*"))) (set_attr "mode" "HI,HI,SI")]) @@ -7885,7 +7786,45 @@ (set_attr "mode" "QI")]) (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand:SWI248 0 "register_operand") + (and:SWI248 (match_operand:SWI248 1 "nonimmediate_operand") + (match_operand:SWI248 2 "const_int_operand"))) + (clobber (reg:CC FLAGS_REG))] + "reload_completed + && true_regnum (operands[0]) != true_regnum (operands[1])" + [(const_int 0)] +{ + enum machine_mode mode; + + if (INTVAL (operands[2]) == (HOST_WIDE_INT) 0xffffffff) + mode = SImode; + else if (INTVAL (operands[2]) == 0xffff) + mode = HImode; + else + { + gcc_assert (INTVAL (operands[2]) == 0xff); + mode = QImode; + } + + operands[1] = gen_lowpart (mode, operands[1]); + + if (mode == SImode) + emit_insn (gen_zero_extendsidi2 (operands[0], operands[1])); + else + { + rtx (*insn) (rtx, rtx); + + /* Zero extend to SImode to avoid partial register stalls. */ + operands[0] = gen_lowpart (SImode, operands[0]); + + insn = (mode == HImode) ? gen_zero_extendhisi2 : gen_zero_extendqisi2; + emit_insn (insn (operands[0], operands[1])); + } + DONE; +}) + +(define_split + [(set (match_operand 0 "register_operand") (and (match_dup 0) (const_int -65536))) (clobber (reg:CC FLAGS_REG))] @@ -7895,7 +7834,7 @@ "operands[1] = gen_lowpart (HImode, operands[0]);") (define_split - [(set (match_operand 0 "ext_register_operand" "") + [(set (match_operand 0 "ext_register_operand") (and (match_dup 0) (const_int -256))) (clobber (reg:CC FLAGS_REG))] @@ -7905,7 +7844,7 @@ "operands[1] = gen_lowpart (QImode, operands[0]);") (define_split - [(set (match_operand 0 "ext_register_operand" "") + [(set (match_operand 0 "ext_register_operand") (and (match_dup 0) (const_int -65281))) (clobber (reg:CC FLAGS_REG))] @@ -8121,9 +8060,9 @@ ;; of memory mismatch stalls. We may want to do the splitting for optimizing ;; for size, but that can (should?) be handled by generic code instead. (define_split - [(set (match_operand 0 "register_operand" "") - (and (match_operand 1 "register_operand" "") - (match_operand 2 "const_int_operand" ""))) + [(set (match_operand 0 "register_operand") + (and (match_operand 1 "register_operand") + (match_operand 2 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))] "reload_completed && QI_REG_P (operands[0]) @@ -8135,16 +8074,18 @@ (const_int 8) (const_int 8)) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] - "operands[0] = gen_lowpart (SImode, operands[0]); - operands[1] = gen_lowpart (SImode, operands[1]); - operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);") +{ + operands[0] = gen_lowpart (SImode, operands[0]); + operands[1] = gen_lowpart (SImode, operands[1]); + operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode); +}) ;; Since AND can be encoded with sign extended immediate, this is only ;; profitable when 7th bit is not set. (define_split - [(set (match_operand 0 "register_operand" "") - (and (match_operand 1 "general_operand" "") - (match_operand 2 "const_int_operand" ""))) + [(set (match_operand 0 "register_operand") + (and (match_operand 1 "general_operand") + (match_operand 2 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))] "reload_completed && ANY_QI_REG_P (operands[0]) @@ -8156,9 +8097,11 @@ (and:QI (match_dup 1) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] - "operands[0] = gen_lowpart (QImode, operands[0]); - operands[1] = gen_lowpart (QImode, operands[1]); - operands[2] = gen_lowpart (QImode, operands[2]);") +{ + operands[0] = gen_lowpart (QImode, operands[0]); + operands[1] = gen_lowpart (QImode, operands[1]); + operands[2] = gen_lowpart (QImode, operands[2]); +}) ;; Logical inclusive and exclusive OR instructions @@ -8166,9 +8109,9 @@ ;; If this is considered useful, it should be done with splitters. (define_expand "3" - [(set (match_operand:SWIM 0 "nonimmediate_operand" "") - (any_or:SWIM (match_operand:SWIM 1 "nonimmediate_operand" "") - (match_operand:SWIM 2 "" "")))] + [(set (match_operand:SWIM 0 "nonimmediate_operand") + (any_or:SWIM (match_operand:SWIM 1 "nonimmediate_operand") + (match_operand:SWIM 2 "")))] "" "ix86_expand_binary_operator (, mode, operands); DONE;") @@ -8376,9 +8319,9 @@ (set_attr "mode" "QI")]) (define_split - [(set (match_operand 0 "register_operand" "") - (any_or (match_operand 1 "register_operand" "") - (match_operand 2 "const_int_operand" ""))) + [(set (match_operand 0 "register_operand") + (any_or (match_operand 1 "register_operand") + (match_operand 2 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))] "reload_completed && QI_REG_P (operands[0]) @@ -8390,16 +8333,18 @@ (const_int 8) (const_int 8)) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] - "operands[0] = gen_lowpart (SImode, operands[0]); - operands[1] = gen_lowpart (SImode, operands[1]); - operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);") +{ + operands[0] = gen_lowpart (SImode, operands[0]); + operands[1] = gen_lowpart (SImode, operands[1]); + operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode); +}) ;; Since OR can be encoded with sign extended immediate, this is only ;; profitable when 7th bit is set. (define_split - [(set (match_operand 0 "register_operand" "") - (any_or (match_operand 1 "general_operand" "") - (match_operand 2 "const_int_operand" ""))) + [(set (match_operand 0 "register_operand") + (any_or (match_operand 1 "general_operand") + (match_operand 2 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))] "reload_completed && ANY_QI_REG_P (operands[0]) @@ -8411,9 +8356,11 @@ (any_or:QI (match_dup 1) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] - "operands[0] = gen_lowpart (QImode, operands[0]); - operands[1] = gen_lowpart (QImode, operands[1]); - operands[2] = gen_lowpart (QImode, operands[2]);") +{ + operands[0] = gen_lowpart (QImode, operands[0]); + operands[1] = gen_lowpart (QImode, operands[1]); + operands[2] = gen_lowpart (QImode, operands[2]); +}) (define_expand "xorqi_cc_ext_1" [(parallel [ @@ -8421,12 +8368,12 @@ (compare:CCNO (xor:SI (zero_extract:SI - (match_operand 1 "ext_register_operand" "") + (match_operand 1 "ext_register_operand") (const_int 8) (const_int 8)) - (match_operand:QI 2 "general_operand" "")) + (match_operand:QI 2 "general_operand")) (const_int 0))) - (set (zero_extract:SI (match_operand 0 "ext_register_operand" "") + (set (zero_extract:SI (match_operand 0 "ext_register_operand") (const_int 8) (const_int 8)) (xor:SI @@ -8489,8 +8436,8 @@ ;; Negation instructions (define_expand "neg2" - [(set (match_operand:SDWIM 0 "nonimmediate_operand" "") - (neg:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand" "")))] + [(set (match_operand:SDWIM 0 "nonimmediate_operand") + (neg:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand")))] "" "ix86_expand_unary_operator (NEG, mode, operands); DONE;") @@ -8576,8 +8523,8 @@ ;; Changing of sign for FP values is doable using integer unit too. (define_expand "2" - [(set (match_operand:X87MODEF 0 "register_operand" "") - (absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "")))] + [(set (match_operand:X87MODEF 0 "register_operand") + (absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand")))] "TARGET_80387 || (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)" "ix86_expand_fp_absneg_operator (, mode, operands); DONE;") @@ -8603,14 +8550,14 @@ [(set (match_operand:X87MODEF 0 "register_operand" "=f,!r") (match_operator:X87MODEF 3 "absneg_operator" [(match_operand:X87MODEF 1 "register_operand" "0,0")])) - (use (match_operand 2 "" "")) + (use (match_operand 2)) (clobber (reg:CC FLAGS_REG))] "TARGET_80387 && !(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)" "#") (define_expand "tf2" - [(set (match_operand:TF 0 "register_operand" "") - (absneg:TF (match_operand:TF 1 "register_operand" "")))] + [(set (match_operand:TF 0 "register_operand") + (absneg:TF (match_operand:TF 1 "register_operand")))] "TARGET_SSE2" "ix86_expand_fp_absneg_operator (, TFmode, operands); DONE;") @@ -8626,18 +8573,18 @@ ;; Splitters for fp abs and neg. (define_split - [(set (match_operand 0 "fp_register_operand" "") + [(set (match_operand 0 "fp_register_operand") (match_operator 1 "absneg_operator" [(match_dup 0)])) - (use (match_operand 2 "" "")) + (use (match_operand 2)) (clobber (reg:CC FLAGS_REG))] "reload_completed" [(set (match_dup 0) (match_op_dup 1 [(match_dup 0)]))]) (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "register_operand") (match_operator 3 "absneg_operator" - [(match_operand 1 "register_operand" "")])) - (use (match_operand 2 "nonimmediate_operand" "")) + [(match_operand 1 "register_operand")])) + (use (match_operand 2 "nonimmediate_operand")) (clobber (reg:CC FLAGS_REG))] "reload_completed && SSE_REG_P (operands[0])" [(set (match_dup 0) (match_dup 3))] @@ -8662,9 +8609,9 @@ }) (define_split - [(set (match_operand:SF 0 "register_operand" "") + [(set (match_operand:SF 0 "register_operand") (match_operator:SF 1 "absneg_operator" [(match_dup 0)])) - (use (match_operand:V4SF 2 "" "")) + (use (match_operand:V4SF 2)) (clobber (reg:CC FLAGS_REG))] "reload_completed" [(parallel [(set (match_dup 0) (match_dup 1)) @@ -8686,9 +8633,9 @@ }) (define_split - [(set (match_operand:DF 0 "register_operand" "") + [(set (match_operand:DF 0 "register_operand") (match_operator:DF 1 "absneg_operator" [(match_dup 0)])) - (use (match_operand 2 "" "")) + (use (match_operand 2)) (clobber (reg:CC FLAGS_REG))] "reload_completed" [(parallel [(set (match_dup 0) (match_dup 1)) @@ -8724,9 +8671,9 @@ }) (define_split - [(set (match_operand:XF 0 "register_operand" "") + [(set (match_operand:XF 0 "register_operand") (match_operator:XF 1 "absneg_operator" [(match_dup 0)])) - (use (match_operand 2 "" "")) + (use (match_operand 2)) (clobber (reg:CC FLAGS_REG))] "reload_completed" [(parallel [(set (match_dup 0) (match_dup 1)) @@ -8795,9 +8742,9 @@ (define_mode_attr CSGNVMODE [(SF "V4SF") (DF "V2DF") (TF "TF")]) (define_expand "copysign3" - [(match_operand:CSGNMODE 0 "register_operand" "") - (match_operand:CSGNMODE 1 "nonmemory_operand" "") - (match_operand:CSGNMODE 2 "register_operand" "")] + [(match_operand:CSGNMODE 0 "register_operand") + (match_operand:CSGNMODE 1 "nonmemory_operand") + (match_operand:CSGNMODE 2 "register_operand")] "(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || (TARGET_SSE2 && (mode == TFmode))" "ix86_expand_copysign (operands); DONE;") @@ -8830,14 +8777,14 @@ "#") (define_split - [(set (match_operand:CSGNMODE 0 "register_operand" "") + [(set (match_operand:CSGNMODE 0 "register_operand") (unspec:CSGNMODE - [(match_operand:CSGNMODE 2 "register_operand" "") - (match_operand:CSGNMODE 3 "register_operand" "") - (match_operand: 4 "" "") - (match_operand: 5 "" "")] + [(match_operand:CSGNMODE 2 "register_operand") + (match_operand:CSGNMODE 3 "register_operand") + (match_operand: 4) + (match_operand: 5)] UNSPEC_COPYSIGN)) - (clobber (match_scratch: 1 ""))] + (clobber (match_scratch: 1))] "((SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || (TARGET_SSE2 && (mode == TFmode))) && reload_completed" @@ -8847,8 +8794,8 @@ ;; One complement instructions (define_expand "one_cmpl2" - [(set (match_operand:SWIM 0 "nonimmediate_operand" "") - (not:SWIM (match_operand:SWIM 1 "nonimmediate_operand" "")))] + [(set (match_operand:SWIM 0 "nonimmediate_operand") + (not:SWIM (match_operand:SWIM 1 "nonimmediate_operand")))] "" "ix86_expand_unary_operator (NOT, mode, operands); DONE;") @@ -8894,11 +8841,11 @@ (set_attr "mode" "")]) (define_split - [(set (match_operand 0 "flags_reg_operand" "") + [(set (match_operand 0 "flags_reg_operand") (match_operator 2 "compare_operator" - [(not:SWI (match_operand:SWI 3 "nonimmediate_operand" "")) + [(not:SWI (match_operand:SWI 3 "nonimmediate_operand")) (const_int 0)])) - (set (match_operand:SWI 1 "nonimmediate_operand" "") + (set (match_operand:SWI 1 "nonimmediate_operand") (not:SWI (match_dup 3)))] "ix86_match_ccmode (insn, CCNOmode)" [(parallel [(set (match_dup 0) @@ -8921,11 +8868,11 @@ (set_attr "mode" "SI")]) (define_split - [(set (match_operand 0 "flags_reg_operand" "") + [(set (match_operand 0 "flags_reg_operand") (match_operator 2 "compare_operator" - [(not:SI (match_operand:SI 3 "register_operand" "")) + [(not:SI (match_operand:SI 3 "register_operand")) (const_int 0)])) - (set (match_operand:DI 1 "register_operand" "") + (set (match_operand:DI 1 "register_operand") (zero_extend:DI (not:SI (match_dup 3))))] "ix86_match_ccmode (insn, CCNOmode)" [(parallel [(set (match_dup 0) @@ -8959,9 +8906,9 @@ ;; than 31. (define_expand "ashl3" - [(set (match_operand:SDWIM 0 "" "") - (ashift:SDWIM (match_operand:SDWIM 1 "" "") - (match_operand:QI 2 "nonmemory_operand" "")))] + [(set (match_operand:SDWIM 0 "") + (ashift:SDWIM (match_operand:SDWIM 1 "") + (match_operand:QI 2 "nonmemory_operand")))] "" "ix86_expand_binary_operator (ASHIFT, mode, operands); DONE;") @@ -8975,9 +8922,9 @@ [(set_attr "type" "multi")]) (define_split - [(set (match_operand:DWI 0 "register_operand" "") - (ashift:DWI (match_operand:DWI 1 "nonmemory_operand" "") - (match_operand:QI 2 "nonmemory_operand" ""))) + [(set (match_operand:DWI 0 "register_operand") + (ashift:DWI (match_operand:DWI 1 "nonmemory_operand") + (match_operand:QI 2 "nonmemory_operand"))) (clobber (reg:CC FLAGS_REG))] "(optimize && flag_peephole2) ? epilogue_completed : reload_completed" [(const_int 0)] @@ -8989,10 +8936,10 @@ (define_peephole2 [(match_scratch:DWIH 3 "r") - (parallel [(set (match_operand: 0 "register_operand" "") + (parallel [(set (match_operand: 0 "register_operand") (ashift: - (match_operand: 1 "nonmemory_operand" "") - (match_operand:QI 2 "nonmemory_operand" ""))) + (match_operand: 1 "nonmemory_operand") + (match_operand:QI 2 "nonmemory_operand"))) (clobber (reg:CC FLAGS_REG))]) (match_dup 3)] "TARGET_CMOVE" @@ -9034,24 +8981,24 @@ (define_expand "x86_shift_adj_1" [(set (reg:CCZ FLAGS_REG) - (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "") + (compare:CCZ (and:QI (match_operand:QI 2 "register_operand") (match_dup 4)) (const_int 0))) - (set (match_operand:SWI48 0 "register_operand" "") + (set (match_operand:SWI48 0 "register_operand") (if_then_else:SWI48 (ne (reg:CCZ FLAGS_REG) (const_int 0)) - (match_operand:SWI48 1 "register_operand" "") + (match_operand:SWI48 1 "register_operand") (match_dup 0))) (set (match_dup 1) (if_then_else:SWI48 (ne (reg:CCZ FLAGS_REG) (const_int 0)) - (match_operand:SWI48 3 "register_operand" "r") + (match_operand:SWI48 3 "register_operand") (match_dup 1)))] "TARGET_CMOVE" "operands[4] = GEN_INT (GET_MODE_BITSIZE (mode));") (define_expand "x86_shift_adj_2" - [(use (match_operand:SWI48 0 "register_operand" "")) - (use (match_operand:SWI48 1 "register_operand" "")) - (use (match_operand:QI 2 "register_operand" ""))] + [(use (match_operand:SWI48 0 "register_operand")) + (use (match_operand:SWI48 1 "register_operand")) + (use (match_operand:QI 2 "register_operand"))] "" { rtx label = gen_label_rtx (); @@ -9146,8 +9093,8 @@ (eq_attr "alternative" "2") (const_string "ishiftx") (and (and (match_test "TARGET_DOUBLE_WITH_ADD") - (match_operand 0 "register_operand" "")) - (match_operand 2 "const1_operand" "")) + (match_operand 0 "register_operand")) + (match_operand 2 "const1_operand")) (const_string "alu") ] (const_string "ishift"))) @@ -9155,7 +9102,7 @@ (if_then_else (ior (eq_attr "type" "alu") (and (eq_attr "type" "ishift") - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))))) (const_string "0") @@ -9164,9 +9111,9 @@ ;; Convert shift to the shiftx pattern to avoid flags dependency. (define_split - [(set (match_operand:SWI48 0 "register_operand" "") - (ashift:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "") - (match_operand:QI 2 "register_operand" ""))) + [(set (match_operand:SWI48 0 "register_operand") + (ashift:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") + (match_operand:QI 2 "register_operand"))) (clobber (reg:CC FLAGS_REG))] "TARGET_BMI2 && reload_completed" [(set (match_dup 0) @@ -9216,7 +9163,7 @@ (eq_attr "alternative" "2") (const_string "ishiftx") (and (match_test "TARGET_DOUBLE_WITH_ADD") - (match_operand 2 "const1_operand" "")) + (match_operand 2 "const1_operand")) (const_string "alu") ] (const_string "ishift"))) @@ -9224,7 +9171,7 @@ (if_then_else (ior (eq_attr "type" "alu") (and (eq_attr "type" "ishift") - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))))) (const_string "0") @@ -9233,10 +9180,10 @@ ;; Convert shift to the shiftx pattern to avoid flags dependency. (define_split - [(set (match_operand:DI 0 "register_operand" "") + [(set (match_operand:DI 0 "register_operand") (zero_extend:DI - (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "") - (match_operand:QI 2 "register_operand" "")))) + (ashift:SI (match_operand:SI 1 "nonimmediate_operand") + (match_operand:QI 2 "register_operand")))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && TARGET_BMI2 && reload_completed" [(set (match_dup 0) @@ -9271,8 +9218,8 @@ (cond [(eq_attr "alternative" "1") (const_string "lea") (and (and (match_test "TARGET_DOUBLE_WITH_ADD") - (match_operand 0 "register_operand" "")) - (match_operand 2 "const1_operand" "")) + (match_operand 0 "register_operand")) + (match_operand 2 "const1_operand")) (const_string "alu") ] (const_string "ishift"))) @@ -9280,7 +9227,7 @@ (if_then_else (ior (eq_attr "type" "alu") (and (eq_attr "type" "ishift") - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))))) (const_string "0") @@ -9329,8 +9276,8 @@ (cond [(eq_attr "alternative" "2") (const_string "lea") (and (and (match_test "TARGET_DOUBLE_WITH_ADD") - (match_operand 0 "register_operand" "")) - (match_operand 2 "const1_operand" "")) + (match_operand 0 "register_operand")) + (match_operand 2 "const1_operand")) (const_string "alu") ] (const_string "ishift"))) @@ -9338,7 +9285,7 @@ (if_then_else (ior (eq_attr "type" "alu") (and (eq_attr "type" "ishift") - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))))) (const_string "0") @@ -9372,8 +9319,8 @@ } [(set (attr "type") (cond [(and (and (match_test "TARGET_DOUBLE_WITH_ADD") - (match_operand 0 "register_operand" "")) - (match_operand 1 "const1_operand" "")) + (match_operand 0 "register_operand")) + (match_operand 1 "const1_operand")) (const_string "alu") ] (const_string "ishift1"))) @@ -9381,7 +9328,7 @@ (if_then_else (ior (eq_attr "type" "alu") (and (eq_attr "type" "ishift1") - (and (match_operand 1 "const1_operand" "") + (and (match_operand 1 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))))) (const_string "0") @@ -9390,9 +9337,9 @@ ;; Convert ashift to the lea pattern to avoid flags dependency. (define_split - [(set (match_operand 0 "register_operand" "") - (ashift (match_operand 1 "index_register_operand" "") - (match_operand:QI 2 "const_int_operand" ""))) + [(set (match_operand 0 "register_operand") + (ashift (match_operand 1 "index_register_operand") + (match_operand:QI 2 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))] "GET_MODE (operands[0]) == GET_MODE (operands[1]) && reload_completed @@ -9419,10 +9366,10 @@ ;; Convert ashift to the lea pattern to avoid flags dependency. (define_split - [(set (match_operand:DI 0 "register_operand" "") + [(set (match_operand:DI 0 "register_operand") (zero_extend:DI - (ashift:SI (match_operand:SI 1 "index_register_operand" "") - (match_operand:QI 2 "const_int_operand" "")))) + (ashift:SI (match_operand:SI 1 "index_register_operand") + (match_operand:QI 2 "const_int_operand")))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && reload_completed && true_regnum (operands[0]) != true_regnum (operands[1])" @@ -9468,8 +9415,8 @@ } [(set (attr "type") (cond [(and (and (match_test "TARGET_DOUBLE_WITH_ADD") - (match_operand 0 "register_operand" "")) - (match_operand 2 "const1_operand" "")) + (match_operand 0 "register_operand")) + (match_operand 2 "const1_operand")) (const_string "alu") ] (const_string "ishift"))) @@ -9477,7 +9424,7 @@ (if_then_else (ior (eq_attr "type" "alu") (and (eq_attr "type" "ishift") - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))))) (const_string "0") @@ -9517,7 +9464,7 @@ } [(set (attr "type") (cond [(and (match_test "TARGET_DOUBLE_WITH_ADD") - (match_operand 2 "const1_operand" "")) + (match_operand 2 "const1_operand")) (const_string "alu") ] (const_string "ishift"))) @@ -9525,7 +9472,7 @@ (if_then_else (ior (eq_attr "type" "alu") (and (eq_attr "type" "ishift") - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))))) (const_string "0") @@ -9562,8 +9509,8 @@ } [(set (attr "type") (cond [(and (and (match_test "TARGET_DOUBLE_WITH_ADD") - (match_operand 0 "register_operand" "")) - (match_operand 2 "const1_operand" "")) + (match_operand 0 "register_operand")) + (match_operand 2 "const1_operand")) (const_string "alu") ] (const_string "ishift"))) @@ -9571,7 +9518,7 @@ (if_then_else (ior (eq_attr "type" "alu") (and (eq_attr "type" "ishift") - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))))) (const_string "0") @@ -9581,9 +9528,9 @@ ;; See comment above `ashl3' about how this works. (define_expand "3" - [(set (match_operand:SDWIM 0 "" "") - (any_shiftrt:SDWIM (match_operand:SDWIM 1 "" "") - (match_operand:QI 2 "nonmemory_operand" "")))] + [(set (match_operand:SDWIM 0 "") + (any_shiftrt:SDWIM (match_operand:SDWIM 1 "") + (match_operand:QI 2 "nonmemory_operand")))] "" "ix86_expand_binary_operator (, mode, operands); DONE;") @@ -9632,10 +9579,10 @@ (define_peephole2 [(match_scratch:DWIH 3 "r") - (parallel [(set (match_operand: 0 "register_operand" "") + (parallel [(set (match_operand: 0 "register_operand") (any_shiftrt: - (match_operand: 1 "register_operand" "") - (match_operand:QI 2 "nonmemory_operand" ""))) + (match_operand: 1 "register_operand") + (match_operand:QI 2 "nonmemory_operand"))) (clobber (reg:CC FLAGS_REG))]) (match_dup 3)] "TARGET_CMOVE" @@ -9678,7 +9625,7 @@ (define_insn "ashrdi3_cvt" [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm") (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0") - (match_operand:QI 2 "const_int_operand" ""))) + (match_operand:QI 2 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && INTVAL (operands[2]) == 63 && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun)) @@ -9695,7 +9642,7 @@ (define_insn "ashrsi3_cvt" [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm") (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0") - (match_operand:QI 2 "const_int_operand" ""))) + (match_operand:QI 2 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))] "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun)) @@ -9713,7 +9660,7 @@ [(set (match_operand:DI 0 "register_operand" "=*d,r") (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0") - (match_operand:QI 2 "const_int_operand" "")))) + (match_operand:QI 2 "const_int_operand")))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun)) @@ -9728,9 +9675,9 @@ (set_attr "mode" "SI")]) (define_expand "x86_shift_adj_3" - [(use (match_operand:SWI48 0 "register_operand" "")) - (use (match_operand:SWI48 1 "register_operand" "")) - (use (match_operand:QI 2 "register_operand" ""))] + [(use (match_operand:SWI48 0 "register_operand")) + (use (match_operand:SWI48 1 "register_operand")) + (use (match_operand:QI 2 "register_operand"))] "" { rtx label = gen_label_rtx (); @@ -9790,7 +9737,7 @@ (set_attr "type" "ishift,ishiftx") (set (attr "length_immediate") (if_then_else - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))) (const_string "0") @@ -9799,9 +9746,9 @@ ;; Convert shift to the shiftx pattern to avoid flags dependency. (define_split - [(set (match_operand:SWI48 0 "register_operand" "") - (any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "") - (match_operand:QI 2 "register_operand" ""))) + [(set (match_operand:SWI48 0 "register_operand") + (any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") + (match_operand:QI 2 "register_operand"))) (clobber (reg:CC FLAGS_REG))] "TARGET_BMI2 && reload_completed" [(set (match_dup 0) @@ -9843,7 +9790,7 @@ (set_attr "type" "ishift,ishiftx") (set (attr "length_immediate") (if_then_else - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))) (const_string "0") @@ -9852,10 +9799,10 @@ ;; Convert shift to the shiftx pattern to avoid flags dependency. (define_split - [(set (match_operand:DI 0 "register_operand" "") + [(set (match_operand:DI 0 "register_operand") (zero_extend:DI - (any_shiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "") - (match_operand:QI 2 "register_operand" "")))) + (any_shiftrt:SI (match_operand:SI 1 "nonimmediate_operand") + (match_operand:QI 2 "register_operand")))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && TARGET_BMI2 && reload_completed" [(set (match_dup 0) @@ -9879,7 +9826,7 @@ [(set_attr "type" "ishift") (set (attr "length_immediate") (if_then_else - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))) (const_string "0") @@ -9905,7 +9852,7 @@ [(set_attr "type" "ishift1") (set (attr "length_immediate") (if_then_else - (and (match_operand 1 "const1_operand" "") + (and (match_operand 1 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))) (const_string "0") @@ -9940,7 +9887,7 @@ [(set_attr "type" "ishift") (set (attr "length_immediate") (if_then_else - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))) (const_string "0") @@ -9972,7 +9919,7 @@ [(set_attr "type" "ishift") (set (attr "length_immediate") (if_then_else - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))) (const_string "0") @@ -10002,7 +9949,7 @@ [(set_attr "type" "ishift") (set (attr "length_immediate") (if_then_else - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))) (const_string "0") @@ -10012,9 +9959,9 @@ ;; Rotate instructions (define_expand "ti3" - [(set (match_operand:TI 0 "register_operand" "") - (any_rotate:TI (match_operand:TI 1 "register_operand" "") - (match_operand:QI 2 "nonmemory_operand" "")))] + [(set (match_operand:TI 0 "register_operand") + (any_rotate:TI (match_operand:TI 1 "register_operand") + (match_operand:QI 2 "nonmemory_operand")))] "TARGET_64BIT" { if (const_1_to_63_operand (operands[2], VOIDmode)) @@ -10027,9 +9974,9 @@ }) (define_expand "di3" - [(set (match_operand:DI 0 "shiftdi_operand" "") - (any_rotate:DI (match_operand:DI 1 "shiftdi_operand" "") - (match_operand:QI 2 "nonmemory_operand" "")))] + [(set (match_operand:DI 0 "shiftdi_operand") + (any_rotate:DI (match_operand:DI 1 "shiftdi_operand") + (match_operand:QI 2 "nonmemory_operand")))] "" { if (TARGET_64BIT) @@ -10044,9 +9991,9 @@ }) (define_expand "3" - [(set (match_operand:SWIM124 0 "nonimmediate_operand" "") - (any_rotate:SWIM124 (match_operand:SWIM124 1 "nonimmediate_operand" "") - (match_operand:QI 2 "nonmemory_operand" "")))] + [(set (match_operand:SWIM124 0 "nonimmediate_operand") + (any_rotate:SWIM124 (match_operand:SWIM124 1 "nonimmediate_operand") + (match_operand:QI 2 "nonmemory_operand")))] "" "ix86_expand_binary_operator (, mode, operands); DONE;") @@ -10171,7 +10118,7 @@ (set (attr "length_immediate") (if_then_else (and (eq_attr "type" "rotate") - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)")))) (const_string "0") @@ -10180,9 +10127,9 @@ ;; Convert rotate to the rotatex pattern to avoid flags dependency. (define_split - [(set (match_operand:SWI48 0 "register_operand" "") - (rotate:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "") - (match_operand:QI 2 "immediate_operand" ""))) + [(set (match_operand:SWI48 0 "register_operand") + (rotate:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") + (match_operand:QI 2 "immediate_operand"))) (clobber (reg:CC FLAGS_REG))] "TARGET_BMI2 && reload_completed" [(set (match_dup 0) @@ -10193,9 +10140,9 @@ }) (define_split - [(set (match_operand:SWI48 0 "register_operand" "") - (rotatert:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "") - (match_operand:QI 2 "immediate_operand" ""))) + [(set (match_operand:SWI48 0 "register_operand") + (rotatert:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") + (match_operand:QI 2 "immediate_operand"))) (clobber (reg:CC FLAGS_REG))] "TARGET_BMI2 && reload_completed" [(set (match_dup 0) @@ -10237,7 +10184,7 @@ (set (attr "length_immediate") (if_then_else (and (eq_attr "type" "rotate") - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)")))) (const_string "0") @@ -10246,10 +10193,10 @@ ;; Convert rotate to the rotatex pattern to avoid flags dependency. (define_split - [(set (match_operand:DI 0 "register_operand" "") + [(set (match_operand:DI 0 "register_operand") (zero_extend:DI - (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "") - (match_operand:QI 2 "immediate_operand" "")))) + (rotate:SI (match_operand:SI 1 "nonimmediate_operand") + (match_operand:QI 2 "immediate_operand")))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && TARGET_BMI2 && reload_completed" [(set (match_dup 0) @@ -10260,10 +10207,10 @@ }) (define_split - [(set (match_operand:DI 0 "register_operand" "") + [(set (match_operand:DI 0 "register_operand") (zero_extend:DI - (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "") - (match_operand:QI 2 "immediate_operand" "")))) + (rotatert:SI (match_operand:SI 1 "nonimmediate_operand") + (match_operand:QI 2 "immediate_operand")))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && TARGET_BMI2 && reload_completed" [(set (match_dup 0) @@ -10285,7 +10232,7 @@ [(set_attr "type" "rotate") (set (attr "length_immediate") (if_then_else - (and (match_operand 2 "const1_operand" "") + (and (match_operand 2 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))) (const_string "0") @@ -10311,7 +10258,7 @@ [(set_attr "type" "rotate1") (set (attr "length_immediate") (if_then_else - (and (match_operand 1 "const1_operand" "") + (and (match_operand 1 "const1_operand") (ior (match_test "TARGET_SHIFT1") (match_test "optimize_function_for_size_p (cfun)"))) (const_string "0") @@ -10319,7 +10266,7 @@ (set_attr "mode" "QI")]) (define_split - [(set (match_operand:HI 0 "register_operand" "") + [(set (match_operand:HI 0 "register_operand") (any_rotate:HI (match_dup 0) (const_int 8))) (clobber (reg:CC FLAGS_REG))] "reload_completed @@ -10331,10 +10278,10 @@ ;; Bit set / bit test instructions (define_expand "extv" - [(set (match_operand:SI 0 "register_operand" "") - (sign_extract:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "const8_operand" "") - (match_operand:SI 3 "const8_operand" "")))] + [(set (match_operand:SI 0 "register_operand") + (sign_extract:SI (match_operand:SI 1 "register_operand") + (match_operand:SI 2 "const8_operand") + (match_operand:SI 3 "const8_operand")))] "" { /* Handle extractions from %ah et al. */ @@ -10348,10 +10295,10 @@ }) (define_expand "extzv" - [(set (match_operand:SI 0 "register_operand" "") - (zero_extract:SI (match_operand 1 "ext_register_operand" "") - (match_operand:SI 2 "const8_operand" "") - (match_operand:SI 3 "const8_operand" "")))] + [(set (match_operand:SI 0 "register_operand") + (zero_extract:SI (match_operand 1 "ext_register_operand") + (match_operand:SI 2 "const8_operand") + (match_operand:SI 3 "const8_operand")))] "" { /* Handle extractions from %ah et al. */ @@ -10365,10 +10312,10 @@ }) (define_expand "insv" - [(set (zero_extract (match_operand 0 "register_operand" "") - (match_operand 1 "const_int_operand" "") - (match_operand 2 "const_int_operand" "")) - (match_operand 3 "register_operand" ""))] + [(set (zero_extract (match_operand 0 "register_operand") + (match_operand 1 "const_int_operand") + (match_operand 2 "const_int_operand")) + (match_operand 3 "register_operand"))] "" { rtx (*gen_mov_insv_1) (rtx, rtx); @@ -10408,7 +10355,7 @@ (define_insn "*btsq" [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r") (const_int 1) - (match_operand:DI 1 "const_0_to_63_operand" "")) + (match_operand:DI 1 "const_0_to_63_operand")) (const_int 1)) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (TARGET_USE_BT || reload_completed)" @@ -10420,7 +10367,7 @@ (define_insn "*btrq" [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r") (const_int 1) - (match_operand:DI 1 "const_0_to_63_operand" "")) + (match_operand:DI 1 "const_0_to_63_operand")) (const_int 0)) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (TARGET_USE_BT || reload_completed)" @@ -10432,7 +10379,7 @@ (define_insn "*btcq" [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r") (const_int 1) - (match_operand:DI 1 "const_0_to_63_operand" "")) + (match_operand:DI 1 "const_0_to_63_operand")) (not:DI (zero_extract:DI (match_dup 0) (const_int 1) (match_dup 1)))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (TARGET_USE_BT || reload_completed)" @@ -10446,9 +10393,9 @@ (define_peephole2 [(match_scratch:DI 2 "r") (parallel [(set (zero_extract:DI - (match_operand:DI 0 "register_operand" "") + (match_operand:DI 0 "register_operand") (const_int 1) - (match_operand:DI 1 "const_0_to_63_operand" "")) + (match_operand:DI 1 "const_0_to_63_operand")) (const_int 1)) (clobber (reg:CC FLAGS_REG))])] "TARGET_64BIT && !TARGET_USE_BT" @@ -10478,9 +10425,9 @@ (define_peephole2 [(match_scratch:DI 2 "r") (parallel [(set (zero_extract:DI - (match_operand:DI 0 "register_operand" "") + (match_operand:DI 0 "register_operand") (const_int 1) - (match_operand:DI 1 "const_0_to_63_operand" "")) + (match_operand:DI 1 "const_0_to_63_operand")) (const_int 0)) (clobber (reg:CC FLAGS_REG))])] "TARGET_64BIT && !TARGET_USE_BT" @@ -10510,9 +10457,9 @@ (define_peephole2 [(match_scratch:DI 2 "r") (parallel [(set (zero_extract:DI - (match_operand:DI 0 "register_operand" "") + (match_operand:DI 0 "register_operand") (const_int 1) - (match_operand:DI 1 "const_0_to_63_operand" "")) + (match_operand:DI 1 "const_0_to_63_operand")) (not:DI (zero_extract:DI (match_dup 0) (const_int 1) (match_dup 1)))) (clobber (reg:CC FLAGS_REG))])] @@ -10632,7 +10579,7 @@ ;; sete %al (define_split - [(set (match_operand:QI 0 "nonimmediate_operand" "") + [(set (match_operand:QI 0 "nonimmediate_operand") (ne:QI (match_operator 1 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)]) (const_int 0)))] @@ -10641,7 +10588,7 @@ "PUT_MODE (operands[1], QImode);") (define_split - [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "")) + [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand")) (ne:QI (match_operator 1 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)]) (const_int 0)))] @@ -10650,7 +10597,7 @@ "PUT_MODE (operands[1], QImode);") (define_split - [(set (match_operand:QI 0 "nonimmediate_operand" "") + [(set (match_operand:QI 0 "nonimmediate_operand") (eq:QI (match_operator 1 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)]) (const_int 0)))] @@ -10670,7 +10617,7 @@ }) (define_split - [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "")) + [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand")) (eq:QI (match_operator 1 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)]) (const_int 0)))] @@ -10716,7 +10663,7 @@ [(set (pc) (if_then_else (match_operator 1 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)]) - (label_ref (match_operand 0 "" "")) + (label_ref (match_operand 0)) (pc)))] "" "%+j%C1\t%l0" @@ -10735,7 +10682,7 @@ (if_then_else (match_operator 1 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)]) (pc) - (label_ref (match_operand 0 "" ""))))] + (label_ref (match_operand 0))))] "" "%+j%c1\t%l0" [(set_attr "type" "ibr") @@ -10761,7 +10708,7 @@ (if_then_else (ne (match_operator 0 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)]) (const_int 0)) - (label_ref (match_operand 1 "" "")) + (label_ref (match_operand 1)) (pc)))] "" [(set (pc) @@ -10775,7 +10722,7 @@ (if_then_else (eq (match_operator 0 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)]) (const_int 0)) - (label_ref (match_operand 1 "" "")) + (label_ref (match_operand 1)) (pc)))] "" [(set (pc) @@ -10809,7 +10756,7 @@ (zero_extend:SI (match_operand:QI 2 "register_operand" "r"))) (const_int 0)]) - (label_ref (match_operand 3 "" "")) + (label_ref (match_operand 3)) (pc))) (clobber (reg:CC FLAGS_REG))] "TARGET_USE_BT || optimize_function_for_size_p (cfun)" @@ -10843,7 +10790,7 @@ (and:SI (match_operand:SI 2 "register_operand" "r") (match_operand:SI 3 "const_int_operand" "n")))]) - (label_ref (match_operand 4 "" "")) + (label_ref (match_operand 4)) (pc))) (clobber (reg:CC FLAGS_REG))] "(TARGET_USE_BT || optimize_function_for_size_p (cfun)) @@ -10877,7 +10824,7 @@ (match_operand:QI 2 "register_operand" "r")) (const_int 1)) (const_int 0)]) - (label_ref (match_operand 3 "" "")) + (label_ref (match_operand 3)) (pc))) (clobber (reg:CC FLAGS_REG))] "TARGET_USE_BT || optimize_function_for_size_p (cfun)" @@ -10914,7 +10861,7 @@ (match_operand:SI 3 "const_int_operand" "n")) 0)) (const_int 1)) (const_int 0)]) - (label_ref (match_operand 4 "" "")) + (label_ref (match_operand 4)) (pc))) (clobber (reg:CC FLAGS_REG))] "(TARGET_USE_BT || optimize_function_for_size_p (cfun)) @@ -10942,7 +10889,7 @@ (if_then_else (match_operator 0 "ix86_fp_comparison_operator" [(match_operand 1 "register_operand" "f") (match_operand 2 "nonimmediate_operand" "fm")]) - (label_ref (match_operand 3 "" "")) + (label_ref (match_operand 3)) (pc))) (clobber (reg:CCFP FPSR_REG)) (clobber (reg:CCFP FLAGS_REG)) @@ -10961,7 +10908,7 @@ [(match_operand 1 "register_operand" "f") (match_operand 2 "nonimmediate_operand" "fm")]) (pc) - (label_ref (match_operand 3 "" "")))) + (label_ref (match_operand 3)))) (clobber (reg:CCFP FPSR_REG)) (clobber (reg:CCFP FLAGS_REG)) (clobber (match_scratch:HI 4 "=a"))] @@ -10978,7 +10925,7 @@ (if_then_else (match_operator 0 "ix86_fp_comparison_operator" [(match_operand 1 "register_operand" "f") (match_operand 2 "register_operand" "f")]) - (label_ref (match_operand 3 "" "")) + (label_ref (match_operand 3)) (pc))) (clobber (reg:CCFP FPSR_REG)) (clobber (reg:CCFP FLAGS_REG)) @@ -10994,7 +10941,7 @@ [(match_operand 1 "register_operand" "f") (match_operand 2 "register_operand" "f")]) (pc) - (label_ref (match_operand 3 "" "")))) + (label_ref (match_operand 3)))) (clobber (reg:CCFP FPSR_REG)) (clobber (reg:CCFP FLAGS_REG)) (clobber (match_scratch:HI 4 "=a"))] @@ -11007,8 +10954,8 @@ [(set (pc) (if_then_else (match_operator 0 "ix86_fp_comparison_operator" [(match_operand 1 "register_operand" "f") - (match_operand 2 "const0_operand" "")]) - (label_ref (match_operand 3 "" "")) + (match_operand 2 "const0_operand")]) + (label_ref (match_operand 3)) (pc))) (clobber (reg:CCFP FPSR_REG)) (clobber (reg:CCFP FLAGS_REG)) @@ -11023,10 +10970,10 @@ (define_split [(set (pc) (if_then_else (match_operator 0 "ix86_fp_comparison_operator" - [(match_operand 1 "register_operand" "") - (match_operand 2 "nonimmediate_operand" "")]) - (match_operand 3 "" "") - (match_operand 4 "" ""))) + [(match_operand 1 "register_operand") + (match_operand 2 "nonimmediate_operand")]) + (match_operand 3) + (match_operand 4))) (clobber (reg:CCFP FPSR_REG)) (clobber (reg:CCFP FLAGS_REG))] "reload_completed" @@ -11040,10 +10987,10 @@ (define_split [(set (pc) (if_then_else (match_operator 0 "ix86_fp_comparison_operator" - [(match_operand 1 "register_operand" "") - (match_operand 2 "general_operand" "")]) - (match_operand 3 "" "") - (match_operand 4 "" ""))) + [(match_operand 1 "register_operand") + (match_operand 2 "general_operand")]) + (match_operand 3) + (match_operand 4))) (clobber (reg:CCFP FPSR_REG)) (clobber (reg:CCFP FLAGS_REG)) (clobber (match_scratch:HI 5 "=a"))] @@ -11067,7 +11014,7 @@ [(match_operator 1 "float_operator" [(match_operand:SWI24 2 "nonimmediate_operand" "m,?r")]) (match_operand 3 "register_operand" "f,f")]) - (label_ref (match_operand 4 "" "")) + (label_ref (match_operand 4)) (pc))) (clobber (reg:CCFP FPSR_REG)) (clobber (reg:CCFP FLAGS_REG)) @@ -11084,10 +11031,10 @@ (if_then_else (match_operator 0 "ix86_swapped_fp_comparison_operator" [(match_operator 1 "float_operator" - [(match_operand:SWI24 2 "memory_operand" "")]) - (match_operand 3 "register_operand" "")]) - (match_operand 4 "" "") - (match_operand 5 "" ""))) + [(match_operand:SWI24 2 "memory_operand")]) + (match_operand 3 "register_operand")]) + (match_operand 4) + (match_operand 5))) (clobber (reg:CCFP FPSR_REG)) (clobber (reg:CCFP FLAGS_REG)) (clobber (match_scratch:HI 6 "=a"))] @@ -11108,10 +11055,10 @@ (if_then_else (match_operator 0 "ix86_swapped_fp_comparison_operator" [(match_operator 1 "float_operator" - [(match_operand:SWI24 2 "register_operand" "")]) - (match_operand 3 "register_operand" "")]) - (match_operand 4 "" "") - (match_operand 5 "" ""))) + [(match_operand:SWI24 2 "register_operand")]) + (match_operand 3 "register_operand")]) + (match_operand 4) + (match_operand 5))) (clobber (reg:CCFP FPSR_REG)) (clobber (reg:CCFP FLAGS_REG)) (clobber (match_scratch:HI 6 "=a"))] @@ -11131,7 +11078,7 @@ (define_insn "jump" [(set (pc) - (label_ref (match_operand 0 "" "")))] + (label_ref (match_operand 0)))] "" "jmp\t%l0" [(set_attr "type" "ibr") @@ -11145,18 +11092,23 @@ (set_attr "modrm" "0")]) (define_expand "indirect_jump" - [(set (pc) (match_operand 0 "indirect_branch_operand" ""))]) + [(set (pc) (match_operand 0 "indirect_branch_operand"))] + "" +{ + if (TARGET_X32) + operands[0] = convert_memory_address (word_mode, operands[0]); +}) (define_insn "*indirect_jump" - [(set (pc) (match_operand:P 0 "indirect_branch_operand" "rw"))] + [(set (pc) (match_operand:W 0 "indirect_branch_operand" "rw"))] "" "jmp\t%A0" [(set_attr "type" "ibr") (set_attr "length_immediate" "0")]) (define_expand "tablejump" - [(parallel [(set (pc) (match_operand 0 "indirect_branch_operand" "")) - (use (label_ref (match_operand 1 "" "")))])] + [(parallel [(set (pc) (match_operand 0 "indirect_branch_operand")) + (use (label_ref (match_operand 1)))])] "" { /* In PIC mode, the table entries are stored GOT (32-bit) or PC (64-bit) @@ -11190,13 +11142,14 @@ operands[0] = expand_simple_binop (Pmode, code, op0, op1, NULL_RTX, 0, OPTAB_DIRECT); } - else if (TARGET_X32) - operands[0] = convert_memory_address (Pmode, operands[0]); + + if (TARGET_X32) + operands[0] = convert_memory_address (word_mode, operands[0]); }) (define_insn "*tablejump_1" - [(set (pc) (match_operand:P 0 "indirect_branch_operand" "rw")) - (use (label_ref (match_operand 1 "" "")))] + [(set (pc) (match_operand:W 0 "indirect_branch_operand" "rw")) + (use (label_ref (match_operand 1)))] "" "jmp\t%A0" [(set_attr "type" "ibr") @@ -11205,11 +11158,11 @@ ;; Convert setcc + movzbl to xor + setcc if operands don't overlap. (define_peephole2 - [(set (reg FLAGS_REG) (match_operand 0 "" "")) - (set (match_operand:QI 1 "register_operand" "") + [(set (reg FLAGS_REG) (match_operand 0)) + (set (match_operand:QI 1 "register_operand") (match_operator:QI 2 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)])) - (set (match_operand 3 "q_regs_operand" "") + (set (match_operand 3 "q_regs_operand") (zero_extend (match_dup 1)))] "(peep2_reg_dead_p (3, operands[1]) || operands_match_p (operands[1], operands[3])) @@ -11223,19 +11176,39 @@ ix86_expand_clear (operands[3]); }) -;; Similar, but match zero_extendhisi2_and, which adds a clobber. - (define_peephole2 - [(set (reg FLAGS_REG) (match_operand 0 "" "")) - (set (match_operand:QI 1 "register_operand" "") + [(parallel [(set (reg FLAGS_REG) (match_operand 0)) + (match_operand 4)]) + (set (match_operand:QI 1 "register_operand") (match_operator:QI 2 "ix86_comparison_operator" [(reg FLAGS_REG) (const_int 0)])) - (parallel [(set (match_operand 3 "q_regs_operand" "") - (zero_extend (match_dup 1))) - (clobber (reg:CC FLAGS_REG))])] + (set (match_operand 3 "q_regs_operand") + (zero_extend (match_dup 1)))] "(peep2_reg_dead_p (3, operands[1]) || operands_match_p (operands[1], operands[3])) && ! reg_overlap_mentioned_p (operands[3], operands[0])" + [(parallel [(set (match_dup 5) (match_dup 0)) + (match_dup 4)]) + (set (strict_low_part (match_dup 6)) + (match_dup 2))] +{ + operands[5] = gen_rtx_REG (GET_MODE (operands[0]), FLAGS_REG); + operands[6] = gen_lowpart (QImode, operands[3]); + ix86_expand_clear (operands[3]); +}) + +;; Similar, but match zero extend with andsi3. + +(define_peephole2 + [(set (reg FLAGS_REG) (match_operand 0)) + (set (match_operand:QI 1 "register_operand") + (match_operator:QI 2 "ix86_comparison_operator" + [(reg FLAGS_REG) (const_int 0)])) + (parallel [(set (match_operand:SI 3 "q_regs_operand") + (and:SI (match_dup 3) (const_int 255))) + (clobber (reg:CC FLAGS_REG))])] + "REGNO (operands[1]) == REGNO (operands[3]) + && ! reg_overlap_mentioned_p (operands[3], operands[0])" [(set (match_dup 4) (match_dup 0)) (set (strict_low_part (match_dup 5)) (match_dup 2))] @@ -11244,6 +11217,28 @@ operands[5] = gen_lowpart (QImode, operands[3]); ix86_expand_clear (operands[3]); }) + +(define_peephole2 + [(parallel [(set (reg FLAGS_REG) (match_operand 0)) + (match_operand 4)]) + (set (match_operand:QI 1 "register_operand") + (match_operator:QI 2 "ix86_comparison_operator" + [(reg FLAGS_REG) (const_int 0)])) + (parallel [(set (match_operand 3 "q_regs_operand") + (zero_extend (match_dup 1))) + (clobber (reg:CC FLAGS_REG))])] + "(peep2_reg_dead_p (3, operands[1]) + || operands_match_p (operands[1], operands[3])) + && ! reg_overlap_mentioned_p (operands[3], operands[0])" + [(parallel [(set (match_dup 5) (match_dup 0)) + (match_dup 4)]) + (set (strict_low_part (match_dup 6)) + (match_dup 2))] +{ + operands[5] = gen_rtx_REG (GET_MODE (operands[0]), FLAGS_REG); + operands[6] = gen_lowpart (QImode, operands[3]); + ix86_expand_clear (operands[3]); +}) ;; Call instructions. @@ -11261,9 +11256,9 @@ ;; Call subroutine returning no value. (define_expand "call" - [(call (match_operand:QI 0 "" "") - (match_operand 1 "" "")) - (use (match_operand 2 "" ""))] + [(call (match_operand:QI 0) + (match_operand 1)) + (use (match_operand 2))] "" { ix86_expand_call (NULL, operands[0], operands[1], @@ -11272,9 +11267,9 @@ }) (define_expand "sibcall" - [(call (match_operand:QI 0 "" "") - (match_operand 1 "" "")) - (use (match_operand 2 "" ""))] + [(call (match_operand:QI 0) + (match_operand 1)) + (use (match_operand 2))] "" { ix86_expand_call (NULL, operands[0], operands[1], @@ -11283,9 +11278,9 @@ }) (define_insn_and_split "*call_vzeroupper" - [(call (mem:QI (match_operand:P 0 "call_insn_operand" "zw")) - (match_operand 1 "" "")) - (unspec [(match_operand 2 "const_int_operand" "")] + [(call (mem:QI (match_operand:W 0 "call_insn_operand" "zw")) + (match_operand 1)) + (unspec [(match_operand 2 "const_int_operand")] UNSPEC_CALL_NEEDS_VZEROUPPER)] "TARGET_VZEROUPPER && !SIBLING_CALL_P (insn)" "#" @@ -11295,15 +11290,15 @@ [(set_attr "type" "call")]) (define_insn "*call" - [(call (mem:QI (match_operand:P 0 "call_insn_operand" "zw")) - (match_operand 1 "" ""))] + [(call (mem:QI (match_operand:W 0 "call_insn_operand" "zw")) + (match_operand 1))] "!SIBLING_CALL_P (insn)" "* return ix86_output_call_insn (insn, operands[0]);" [(set_attr "type" "call")]) (define_insn_and_split "*call_rex64_ms_sysv_vzeroupper" [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rzw")) - (match_operand 1 "" "")) + (match_operand 1)) (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL) (clobber (reg:TI XMM6_REG)) (clobber (reg:TI XMM7_REG)) @@ -11317,7 +11312,7 @@ (clobber (reg:TI XMM15_REG)) (clobber (reg:DI SI_REG)) (clobber (reg:DI DI_REG)) - (unspec [(match_operand 2 "const_int_operand" "")] + (unspec [(match_operand 2 "const_int_operand")] UNSPEC_CALL_NEEDS_VZEROUPPER)] "TARGET_VZEROUPPER && TARGET_64BIT && !SIBLING_CALL_P (insn)" "#" @@ -11328,7 +11323,7 @@ (define_insn "*call_rex64_ms_sysv" [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rzw")) - (match_operand 1 "" "")) + (match_operand 1)) (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL) (clobber (reg:TI XMM6_REG)) (clobber (reg:TI XMM7_REG)) @@ -11347,9 +11342,9 @@ [(set_attr "type" "call")]) (define_insn_and_split "*sibcall_vzeroupper" - [(call (mem:QI (match_operand:P 0 "sibcall_insn_operand" "Uz")) - (match_operand 1 "" "")) - (unspec [(match_operand 2 "const_int_operand" "")] + [(call (mem:QI (match_operand:W 0 "sibcall_insn_operand" "Uz")) + (match_operand 1)) + (unspec [(match_operand 2 "const_int_operand")] UNSPEC_CALL_NEEDS_VZEROUPPER)] "TARGET_VZEROUPPER && SIBLING_CALL_P (insn)" "#" @@ -11359,18 +11354,18 @@ [(set_attr "type" "call")]) (define_insn "*sibcall" - [(call (mem:QI (match_operand:P 0 "sibcall_insn_operand" "Uz")) - (match_operand 1 "" ""))] + [(call (mem:QI (match_operand:W 0 "sibcall_insn_operand" "Uz")) + (match_operand 1))] "SIBLING_CALL_P (insn)" "* return ix86_output_call_insn (insn, operands[0]);" [(set_attr "type" "call")]) (define_expand "call_pop" - [(parallel [(call (match_operand:QI 0 "" "") - (match_operand:SI 1 "" "")) + [(parallel [(call (match_operand:QI 0) + (match_operand:SI 1)) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) - (match_operand:SI 3 "" "")))])] + (match_operand:SI 3)))])] "!TARGET_64BIT" { ix86_expand_call (NULL, operands[0], operands[1], @@ -11380,11 +11375,11 @@ (define_insn_and_split "*call_pop_vzeroupper" [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lzm")) - (match_operand:SI 1 "" "")) + (match_operand 1)) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand:SI 2 "immediate_operand" "i"))) - (unspec [(match_operand 3 "const_int_operand" "")] + (unspec [(match_operand 3 "const_int_operand")] UNSPEC_CALL_NEEDS_VZEROUPPER)] "TARGET_VZEROUPPER && !TARGET_64BIT && !SIBLING_CALL_P (insn)" "#" @@ -11395,7 +11390,7 @@ (define_insn "*call_pop" [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lzm")) - (match_operand 1 "" "")) + (match_operand 1)) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand:SI 2 "immediate_operand" "i")))] @@ -11405,11 +11400,11 @@ (define_insn_and_split "*sibcall_pop_vzeroupper" [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "Uz")) - (match_operand 1 "" "")) + (match_operand 1)) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand:SI 2 "immediate_operand" "i"))) - (unspec [(match_operand 3 "const_int_operand" "")] + (unspec [(match_operand 3 "const_int_operand")] UNSPEC_CALL_NEEDS_VZEROUPPER)] "TARGET_VZEROUPPER && !TARGET_64BIT && SIBLING_CALL_P (insn)" "#" @@ -11420,7 +11415,7 @@ (define_insn "*sibcall_pop" [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "Uz")) - (match_operand 1 "" "")) + (match_operand 1)) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand:SI 2 "immediate_operand" "i")))] @@ -11431,10 +11426,10 @@ ;; Call subroutine, returning value in operand 0 (define_expand "call_value" - [(set (match_operand 0 "" "") - (call (match_operand:QI 1 "" "") - (match_operand 2 "" ""))) - (use (match_operand 3 "" ""))] + [(set (match_operand 0) + (call (match_operand:QI 1) + (match_operand 2))) + (use (match_operand 3))] "" { ix86_expand_call (operands[0], operands[1], operands[2], @@ -11443,10 +11438,10 @@ }) (define_expand "sibcall_value" - [(set (match_operand 0 "" "") - (call (match_operand:QI 1 "" "") - (match_operand 2 "" ""))) - (use (match_operand 3 "" ""))] + [(set (match_operand 0) + (call (match_operand:QI 1) + (match_operand 2))) + (use (match_operand 3))] "" { ix86_expand_call (operands[0], operands[1], operands[2], @@ -11455,10 +11450,10 @@ }) (define_insn_and_split "*call_value_vzeroupper" - [(set (match_operand 0 "" "") - (call (mem:QI (match_operand:P 1 "call_insn_operand" "zw")) - (match_operand 2 "" ""))) - (unspec [(match_operand 3 "const_int_operand" "")] + [(set (match_operand 0) + (call (mem:QI (match_operand:W 1 "call_insn_operand" "zw")) + (match_operand 2))) + (unspec [(match_operand 3 "const_int_operand")] UNSPEC_CALL_NEEDS_VZEROUPPER)] "TARGET_VZEROUPPER && !SIBLING_CALL_P (insn)" "#" @@ -11468,18 +11463,18 @@ [(set_attr "type" "callv")]) (define_insn "*call_value" - [(set (match_operand 0 "" "") - (call (mem:QI (match_operand:P 1 "call_insn_operand" "zw")) - (match_operand 2 "" "")))] + [(set (match_operand 0) + (call (mem:QI (match_operand:W 1 "call_insn_operand" "zw")) + (match_operand 2)))] "!SIBLING_CALL_P (insn)" "* return ix86_output_call_insn (insn, operands[1]);" [(set_attr "type" "callv")]) (define_insn_and_split "*sibcall_value_vzeroupper" - [(set (match_operand 0 "" "") - (call (mem:QI (match_operand:P 1 "sibcall_insn_operand" "Uz")) - (match_operand 2 "" ""))) - (unspec [(match_operand 3 "const_int_operand" "")] + [(set (match_operand 0) + (call (mem:QI (match_operand:W 1 "sibcall_insn_operand" "Uz")) + (match_operand 2))) + (unspec [(match_operand 3 "const_int_operand")] UNSPEC_CALL_NEEDS_VZEROUPPER)] "TARGET_VZEROUPPER && SIBLING_CALL_P (insn)" "#" @@ -11489,17 +11484,17 @@ [(set_attr "type" "callv")]) (define_insn "*sibcall_value" - [(set (match_operand 0 "" "") - (call (mem:QI (match_operand:P 1 "sibcall_insn_operand" "Uz")) - (match_operand 2 "" "")))] + [(set (match_operand 0) + (call (mem:QI (match_operand:W 1 "sibcall_insn_operand" "Uz")) + (match_operand 2)))] "SIBLING_CALL_P (insn)" "* return ix86_output_call_insn (insn, operands[1]);" [(set_attr "type" "callv")]) (define_insn_and_split "*call_value_rex64_ms_sysv_vzeroupper" - [(set (match_operand 0 "" "") + [(set (match_operand 0) (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rzw")) - (match_operand 2 "" ""))) + (match_operand 2))) (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL) (clobber (reg:TI XMM6_REG)) (clobber (reg:TI XMM7_REG)) @@ -11513,7 +11508,7 @@ (clobber (reg:TI XMM15_REG)) (clobber (reg:DI SI_REG)) (clobber (reg:DI DI_REG)) - (unspec [(match_operand 3 "const_int_operand" "")] + (unspec [(match_operand 3 "const_int_operand")] UNSPEC_CALL_NEEDS_VZEROUPPER)] "TARGET_VZEROUPPER && TARGET_64BIT && !SIBLING_CALL_P (insn)" "#" @@ -11523,9 +11518,9 @@ [(set_attr "type" "callv")]) (define_insn "*call_value_rex64_ms_sysv" - [(set (match_operand 0 "" "") + [(set (match_operand 0) (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rzw")) - (match_operand 2 "" ""))) + (match_operand 2))) (unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL) (clobber (reg:TI XMM6_REG)) (clobber (reg:TI XMM7_REG)) @@ -11544,12 +11539,12 @@ [(set_attr "type" "callv")]) (define_expand "call_value_pop" - [(parallel [(set (match_operand 0 "" "") - (call (match_operand:QI 1 "" "") - (match_operand:SI 2 "" ""))) + [(parallel [(set (match_operand 0) + (call (match_operand:QI 1) + (match_operand:SI 2))) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) - (match_operand:SI 4 "" "")))])] + (match_operand:SI 4)))])] "!TARGET_64BIT" { ix86_expand_call (operands[0], operands[1], operands[2], @@ -11558,13 +11553,13 @@ }) (define_insn_and_split "*call_value_pop_vzeroupper" - [(set (match_operand 0 "" "") + [(set (match_operand 0) (call (mem:QI (match_operand:SI 1 "call_insn_operand" "lzm")) - (match_operand 2 "" ""))) + (match_operand 2))) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand:SI 3 "immediate_operand" "i"))) - (unspec [(match_operand 4 "const_int_operand" "")] + (unspec [(match_operand 4 "const_int_operand")] UNSPEC_CALL_NEEDS_VZEROUPPER)] "TARGET_VZEROUPPER && !TARGET_64BIT && !SIBLING_CALL_P (insn)" "#" @@ -11574,9 +11569,9 @@ [(set_attr "type" "callv")]) (define_insn "*call_value_pop" - [(set (match_operand 0 "" "") + [(set (match_operand 0) (call (mem:QI (match_operand:SI 1 "call_insn_operand" "lzm")) - (match_operand 2 "" ""))) + (match_operand 2))) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand:SI 3 "immediate_operand" "i")))] @@ -11585,13 +11580,13 @@ [(set_attr "type" "callv")]) (define_insn_and_split "*sibcall_value_pop_vzeroupper" - [(set (match_operand 0 "" "") + [(set (match_operand 0) (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "Uz")) - (match_operand 2 "" ""))) + (match_operand 2))) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand:SI 3 "immediate_operand" "i"))) - (unspec [(match_operand 4 "const_int_operand" "")] + (unspec [(match_operand 4 "const_int_operand")] UNSPEC_CALL_NEEDS_VZEROUPPER)] "TARGET_VZEROUPPER && !TARGET_64BIT && SIBLING_CALL_P (insn)" "#" @@ -11601,9 +11596,9 @@ [(set_attr "type" "callv")]) (define_insn "*sibcall_value_pop" - [(set (match_operand 0 "" "") + [(set (match_operand 0) (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "Uz")) - (match_operand 2 "" ""))) + (match_operand 2))) (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand:SI 3 "immediate_operand" "i")))] @@ -11614,10 +11609,10 @@ ;; Call subroutine returning any type. (define_expand "untyped_call" - [(parallel [(call (match_operand 0 "" "") + [(parallel [(call (match_operand 0) (const_int 0)) - (match_operand 1 "" "") - (match_operand 2 "" "")])] + (match_operand 1) + (match_operand 2)])] "" { int i; @@ -11679,7 +11674,7 @@ }) (define_insn "*memory_blockage" - [(set (match_operand:BLK 0 "" "") + [(set (match_operand:BLK 0) (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BLOCKAGE))] "" "" @@ -11688,7 +11683,7 @@ ;; As USE insns aren't meaningful after reload, this is used instead ;; to prevent deleting instructions setting registers for PIC code (define_insn "prologue_use" - [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_PROLOGUE_USE)] + [(unspec_volatile [(match_operand 0)] UNSPECV_PROLOGUE_USE)] "" "" [(set_attr "length" "0")]) @@ -11701,6 +11696,7 @@ [(simple_return)] "ix86_can_use_return_insn_p ()" { + ix86_maybe_emit_epilogue_vzeroupper (); if (crtl->args.pops_args) { rtx popc = GEN_INT (crtl->args.pops_args); @@ -11717,6 +11713,7 @@ [(simple_return)] "!TARGET_SEH" { + ix86_maybe_emit_epilogue_vzeroupper (); if (crtl->args.pops_args) { rtx popc = GEN_INT (crtl->args.pops_args); @@ -11750,7 +11747,7 @@ (define_insn "simple_return_pop_internal" [(simple_return) - (use (match_operand:SI 0 "const_int_operand" ""))] + (use (match_operand:SI 0 "const_int_operand"))] "reload_completed" "ret\t%0" [(set_attr "length" "3") @@ -11776,7 +11773,7 @@ ;; Generate nops. Operand 0 is the number of nops, up to 8. (define_insn "nops" - [(unspec_volatile [(match_operand 0 "const_int_operand" "")] + [(unspec_volatile [(match_operand 0 "const_int_operand")] UNSPECV_NOPS)] "reload_completed" { @@ -11798,7 +11795,7 @@ ;; block on K8. (define_insn "pad" - [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_ALIGN)] + [(unspec_volatile [(match_operand 0)] UNSPECV_ALIGN)] "" { #ifdef ASM_OUTPUT_MAX_SKIP_PAD @@ -11829,7 +11826,7 @@ (define_insn "set_got_labelled" [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(label_ref (match_operand 1 "" ""))] + (unspec:SI [(label_ref (match_operand 1))] UNSPEC_SET_GOT)) (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT" @@ -11848,7 +11845,7 @@ (define_insn "set_rip_rex64" [(set (match_operand:DI 0 "register_operand" "=r") - (unspec:DI [(label_ref (match_operand 1 "" ""))] UNSPEC_SET_RIP))] + (unspec:DI [(label_ref (match_operand 1))] UNSPEC_SET_RIP))] "TARGET_64BIT" "lea{q}\t{%l1(%%rip), %0|%0, %l1[rip]}" [(set_attr "type" "lea") @@ -11858,7 +11855,7 @@ (define_insn "set_got_offset_rex64" [(set (match_operand:DI 0 "register_operand" "=r") (unspec:DI - [(label_ref (match_operand 1 "" ""))] + [(label_ref (match_operand 1))] UNSPEC_SET_GOT_OFFSET))] "TARGET_LP64" "movabs{q}\t{$_GLOBAL_OFFSET_TABLE_-%l1, %0|%0, OFFSET FLAT:_GLOBAL_OFFSET_TABLE_-%l1}" @@ -11878,7 +11875,7 @@ "ix86_expand_epilogue (0); DONE;") (define_expand "eh_return" - [(use (match_operand 0 "register_operand" ""))] + [(use (match_operand 0 "register_operand"))] "" { rtx tmp, sa = EH_RETURN_STACKADJ_RTX, ra = operands[0]; @@ -11933,7 +11930,7 @@ ;; In order to support the call/return predictor, we use a return ;; instruction which the middle-end doesn't see. (define_insn "split_stack_return" - [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "")] + [(unspec_volatile [(match_operand:SI 0 "const_int_operand")] UNSPECV_SPLIT_STACK_RETURN)] "" { @@ -11945,11 +11942,11 @@ [(set_attr "atom_unit" "jeu") (set_attr "modrm" "0") (set (attr "length") - (if_then_else (match_operand:SI 0 "const0_operand" "") + (if_then_else (match_operand:SI 0 "const0_operand") (const_int 1) (const_int 3))) (set (attr "length_immediate") - (if_then_else (match_operand:SI 0 "const0_operand" "") + (if_then_else (match_operand:SI 0 "const0_operand") (const_int 0) (const_int 2)))]) @@ -11959,9 +11956,9 @@ (define_expand "split_stack_space_check" [(set (pc) (if_then_else (ltu (minus (reg SP_REG) - (match_operand 0 "register_operand" "")) + (match_operand 0 "register_operand")) (unspec [(const_int 0)] UNSPEC_STACK_CHECK)) - (label_ref (match_operand 1 "" "")) + (label_ref (match_operand 1)) (pc)))] "" { @@ -11984,9 +11981,9 @@ [(set (match_dup 2) (const_int -1)) (parallel [(set (reg:CCZ FLAGS_REG) (compare:CCZ - (match_operand:SWI48 1 "nonimmediate_operand" "") + (match_operand:SWI48 1 "nonimmediate_operand") (const_int 0))) - (set (match_operand:SWI48 0 "register_operand" "") + (set (match_operand:SWI48 0 "register_operand") (ctz:SWI48 (match_dup 1)))]) (set (match_dup 0) (if_then_else:SWI48 (eq (reg:CCZ FLAGS_REG) (const_int 0)) @@ -12058,10 +12055,10 @@ (define_expand "clz2" [(parallel - [(set (match_operand:SWI248 0 "register_operand" "") + [(set (match_operand:SWI248 0 "register_operand") (minus:SWI248 (match_dup 2) - (clz:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" "")))) + (clz:SWI248 (match_operand:SWI248 1 "nonimmediate_operand")))) (clobber (reg:CC FLAGS_REG))]) (parallel [(set (match_dup 0) (xor:SWI248 (match_dup 0) (match_dup 2))) @@ -12411,8 +12408,8 @@ (set_attr "mode" "SI")]) (define_expand "bswap2" - [(set (match_operand:SWI48 0 "register_operand" "") - (bswap:SWI48 (match_operand:SWI48 1 "register_operand" "")))] + [(set (match_operand:SWI48 0 "register_operand") + (bswap:SWI48 (match_operand:SWI48 1 "register_operand")))] "" { if (mode == SImode && !(TARGET_BSWAP || TARGET_MOVBE)) @@ -12472,8 +12469,8 @@ (set_attr "mode" "HI")]) (define_expand "paritydi2" - [(set (match_operand:DI 0 "register_operand" "") - (parity:DI (match_operand:DI 1 "register_operand" "")))] + [(set (match_operand:DI 0 "register_operand") + (parity:DI (match_operand:DI 1 "register_operand")))] "! TARGET_POPCNT" { rtx scratch = gen_reg_rtx (QImode); @@ -12500,8 +12497,8 @@ }) (define_expand "paritysi2" - [(set (match_operand:SI 0 "register_operand" "") - (parity:SI (match_operand:SI 1 "register_operand" "")))] + [(set (match_operand:SI 0 "register_operand") + (parity:SI (match_operand:SI 1 "register_operand")))] "! TARGET_POPCNT" { rtx scratch = gen_reg_rtx (QImode); @@ -12593,8 +12590,8 @@ [(set (match_operand:SI 0 "register_operand" "=a") (unspec:SI [(match_operand:SI 1 "register_operand" "b") - (match_operand:SI 2 "tls_symbolic_operand" "") - (match_operand:SI 3 "constant_call_address_operand" "z")] + (match_operand 2 "tls_symbolic_operand") + (match_operand 3 "constant_call_address_operand" "z")] UNSPEC_TLS_GD)) (clobber (match_scratch:SI 4 "=d")) (clobber (match_scratch:SI 5 "=c")) @@ -12602,7 +12599,7 @@ "!TARGET_64BIT && TARGET_GNU_TLS" { output_asm_insn - ("lea{l}\t{%a2@tlsgd(,%1,1), %0|%0, %a2@tlsgd[%1*1]}", operands); + ("lea{l}\t{%E2@tlsgd(,%1,1), %0|%0, %E2@tlsgd[%1*1]}", operands); if (TARGET_SUN_TLS) #ifdef HAVE_AS_IX86_TLSGDPLT return "call\t%a2@tlsgdplt"; @@ -12616,28 +12613,28 @@ (define_expand "tls_global_dynamic_32" [(parallel - [(set (match_operand:SI 0 "register_operand" "") - (unspec:SI [(match_operand:SI 2 "register_operand" "") - (match_operand:SI 1 "tls_symbolic_operand" "") - (match_operand:SI 3 "constant_call_address_operand" "")] + [(set (match_operand:SI 0 "register_operand") + (unspec:SI [(match_operand:SI 2 "register_operand") + (match_operand 1 "tls_symbolic_operand") + (match_operand 3 "constant_call_address_operand")] UNSPEC_TLS_GD)) - (clobber (match_scratch:SI 4 "")) - (clobber (match_scratch:SI 5 "")) + (clobber (match_scratch:SI 4)) + (clobber (match_scratch:SI 5)) (clobber (reg:CC FLAGS_REG))])]) -(define_insn "*tls_global_dynamic_64" - [(set (match_operand:DI 0 "register_operand" "=a") - (call:DI - (mem:QI (match_operand:DI 2 "constant_call_address_operand" "z")) - (match_operand:DI 3 "" ""))) - (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] - UNSPEC_TLS_GD)] +(define_insn "*tls_global_dynamic_64_" + [(set (match_operand:P 0 "register_operand" "=a") + (call:P + (mem:QI (match_operand 2 "constant_call_address_operand" "z")) + (match_operand 3))) + (unspec:P [(match_operand 1 "tls_symbolic_operand")] + UNSPEC_TLS_GD)] "TARGET_64BIT" { if (!TARGET_X32) fputs (ASM_BYTE "0x66\n", asm_out_file); output_asm_insn - ("lea{q}\t{%a1@tlsgd(%%rip), %%rdi|rdi, %a1@tlsgd[rip]}", operands); + ("lea{q}\t{%E1@tlsgd(%%rip), %%rdi|rdi, %E1@tlsgd[rip]}", operands); fputs (ASM_SHORT "0x6666\n", asm_out_file); fputs ("\trex64\n", asm_out_file); if (TARGET_SUN_TLS) @@ -12648,20 +12645,21 @@ (set (attr "length") (symbol_ref "TARGET_X32 ? 15 : 16"))]) -(define_expand "tls_global_dynamic_64" +(define_expand "tls_global_dynamic_64_" [(parallel - [(set (match_operand:DI 0 "register_operand" "") - (call:DI - (mem:QI (match_operand:DI 2 "constant_call_address_operand" "")) + [(set (match_operand:P 0 "register_operand") + (call:P + (mem:QI (match_operand 2 "constant_call_address_operand")) (const_int 0))) - (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] - UNSPEC_TLS_GD)])]) + (unspec:P [(match_operand 1 "tls_symbolic_operand")] + UNSPEC_TLS_GD)])] + "TARGET_64BIT") (define_insn "*tls_local_dynamic_base_32_gnu" [(set (match_operand:SI 0 "register_operand" "=a") (unspec:SI [(match_operand:SI 1 "register_operand" "b") - (match_operand:SI 2 "constant_call_address_operand" "z")] + (match_operand 2 "constant_call_address_operand" "z")] UNSPEC_TLS_LD_BASE)) (clobber (match_scratch:SI 3 "=d")) (clobber (match_scratch:SI 4 "=c")) @@ -12683,21 +12681,21 @@ (define_expand "tls_local_dynamic_base_32" [(parallel - [(set (match_operand:SI 0 "register_operand" "") + [(set (match_operand:SI 0 "register_operand") (unspec:SI - [(match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "constant_call_address_operand" "")] + [(match_operand:SI 1 "register_operand") + (match_operand 2 "constant_call_address_operand")] UNSPEC_TLS_LD_BASE)) - (clobber (match_scratch:SI 3 "")) - (clobber (match_scratch:SI 4 "")) + (clobber (match_scratch:SI 3)) + (clobber (match_scratch:SI 4)) (clobber (reg:CC FLAGS_REG))])]) -(define_insn "*tls_local_dynamic_base_64" - [(set (match_operand:DI 0 "register_operand" "=a") - (call:DI - (mem:QI (match_operand:DI 1 "constant_call_address_operand" "z")) - (match_operand:DI 2 "" ""))) - (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)] +(define_insn "*tls_local_dynamic_base_64_" + [(set (match_operand:P 0 "register_operand" "=a") + (call:P + (mem:QI (match_operand 1 "constant_call_address_operand" "z")) + (match_operand 2))) + (unspec:P [(const_int 0)] UNSPEC_TLS_LD_BASE)] "TARGET_64BIT" { output_asm_insn @@ -12709,13 +12707,14 @@ [(set_attr "type" "multi") (set_attr "length" "12")]) -(define_expand "tls_local_dynamic_base_64" +(define_expand "tls_local_dynamic_base_64_" [(parallel - [(set (match_operand:DI 0 "register_operand" "") - (call:DI - (mem:QI (match_operand:DI 1 "constant_call_address_operand" "")) + [(set (match_operand:P 0 "register_operand") + (call:P + (mem:QI (match_operand 1 "constant_call_address_operand")) (const_int 0))) - (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)])]) + (unspec:P [(const_int 0)] UNSPEC_TLS_LD_BASE)])] + "TARGET_64BIT") ;; Local dynamic of a single variable is a lose. Show combine how ;; to convert that back to global dynamic. @@ -12724,10 +12723,10 @@ [(set (match_operand:SI 0 "register_operand" "=a") (plus:SI (unspec:SI [(match_operand:SI 1 "register_operand" "b") - (match_operand:SI 2 "constant_call_address_operand" "z")] + (match_operand 2 "constant_call_address_operand" "z")] UNSPEC_TLS_LD_BASE) (const:SI (unspec:SI - [(match_operand:SI 3 "tls_symbolic_operand" "")] + [(match_operand 3 "tls_symbolic_operand")] UNSPEC_DTPOFF)))) (clobber (match_scratch:SI 4 "=d")) (clobber (match_scratch:SI 5 "=c")) @@ -12825,7 +12824,7 @@ (define_insn "tls_initial_exec_64_sun" [(set (match_operand:DI 0 "register_operand" "=a") (unspec:DI - [(match_operand:DI 1 "tls_symbolic_operand" "")] + [(match_operand 1 "tls_symbolic_operand")] UNSPEC_TLS_IE_SUN)) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && TARGET_SUN_TLS" @@ -12840,12 +12839,12 @@ (define_expand "tls_dynamic_gnu2_32" [(set (match_dup 3) - (plus:SI (match_operand:SI 2 "register_operand" "") + (plus:SI (match_operand:SI 2 "register_operand") (const:SI - (unspec:SI [(match_operand:SI 1 "tls_symbolic_operand" "")] + (unspec:SI [(match_operand 1 "tls_symbolic_operand")] UNSPEC_TLSDESC)))) (parallel - [(set (match_operand:SI 0 "register_operand" "") + [(set (match_operand:SI 0 "register_operand") (unspec:SI [(match_dup 1) (match_dup 3) (match_dup 2) (reg:SI SP_REG)] UNSPEC_TLSDESC)) @@ -12860,10 +12859,10 @@ [(set (match_operand:SI 0 "register_operand" "=r") (plus:SI (match_operand:SI 1 "register_operand" "b") (const:SI - (unspec:SI [(match_operand:SI 2 "tls_symbolic_operand" "")] + (unspec:SI [(match_operand 2 "tls_symbolic_operand")] UNSPEC_TLSDESC))))] "!TARGET_64BIT && TARGET_GNU2_TLS" - "lea{l}\t{%a2@TLSDESC(%1), %0|%0, %a2@TLSDESC[%1]}" + "lea{l}\t{%E2@TLSDESC(%1), %0|%0, %E2@TLSDESC[%1]}" [(set_attr "type" "lea") (set_attr "mode" "SI") (set_attr "length" "6") @@ -12871,7 +12870,7 @@ (define_insn "*tls_dynamic_gnu2_call_32" [(set (match_operand:SI 0 "register_operand" "=a") - (unspec:SI [(match_operand:SI 1 "tls_symbolic_operand" "") + (unspec:SI [(match_operand 1 "tls_symbolic_operand") (match_operand:SI 2 "register_operand" "0") ;; we have to make sure %ebx still points to the GOT (match_operand:SI 3 "register_operand" "b") @@ -12887,13 +12886,13 @@ (define_insn_and_split "*tls_dynamic_gnu2_combine_32" [(set (match_operand:SI 0 "register_operand" "=&a") (plus:SI - (unspec:SI [(match_operand:SI 3 "tls_modbase_operand" "") - (match_operand:SI 4 "" "") + (unspec:SI [(match_operand 3 "tls_modbase_operand") + (match_operand:SI 4) (match_operand:SI 2 "register_operand" "b") (reg:SI SP_REG)] UNSPEC_TLSDESC) (const:SI (unspec:SI - [(match_operand:SI 1 "tls_symbolic_operand" "")] + [(match_operand 1 "tls_symbolic_operand")] UNSPEC_DTPOFF)))) (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && TARGET_GNU2_TLS" @@ -12907,10 +12906,10 @@ (define_expand "tls_dynamic_gnu2_64" [(set (match_dup 2) - (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] + (unspec:DI [(match_operand 1 "tls_symbolic_operand")] UNSPEC_TLSDESC)) (parallel - [(set (match_operand:DI 0 "register_operand" "") + [(set (match_operand:DI 0 "register_operand") (unspec:DI [(match_dup 1) (match_dup 2) (reg:DI SP_REG)] UNSPEC_TLSDESC)) (clobber (reg:CC FLAGS_REG))])] @@ -12922,10 +12921,10 @@ (define_insn "*tls_dynamic_gnu2_lea_64" [(set (match_operand:DI 0 "register_operand" "=r") - (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")] + (unspec:DI [(match_operand 1 "tls_symbolic_operand")] UNSPEC_TLSDESC))] "TARGET_64BIT && TARGET_GNU2_TLS" - "lea{q}\t{%a1@TLSDESC(%%rip), %0|%0, %a1@TLSDESC[rip]}" + "lea{q}\t{%E1@TLSDESC(%%rip), %0|%0, %E1@TLSDESC[rip]}" [(set_attr "type" "lea") (set_attr "mode" "DI") (set_attr "length" "7") @@ -12933,7 +12932,7 @@ (define_insn "*tls_dynamic_gnu2_call_64" [(set (match_operand:DI 0 "register_operand" "=a") - (unspec:DI [(match_operand 1 "tls_symbolic_operand" "") + (unspec:DI [(match_operand 1 "tls_symbolic_operand") (match_operand:DI 2 "register_operand" "0") (reg:DI SP_REG)] UNSPEC_TLSDESC)) @@ -12947,12 +12946,12 @@ (define_insn_and_split "*tls_dynamic_gnu2_combine_64" [(set (match_operand:DI 0 "register_operand" "=&a") (plus:DI - (unspec:DI [(match_operand:DI 2 "tls_modbase_operand" "") - (match_operand:DI 3 "" "") + (unspec:DI [(match_operand 2 "tls_modbase_operand") + (match_operand:DI 3) (reg:DI SP_REG)] UNSPEC_TLSDESC) (const:DI (unspec:DI - [(match_operand 1 "tls_symbolic_operand" "")] + [(match_operand 1 "tls_symbolic_operand")] UNSPEC_DTPOFF)))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && TARGET_GNU2_TLS" @@ -12986,10 +12985,10 @@ "* return output_387_binary_op (insn, operands);" [(set (attr "type") (if_then_else (eq_attr "alternative" "1,2") - (if_then_else (match_operand:MODEF 3 "mult_operator" "") + (if_then_else (match_operand:MODEF 3 "mult_operator") (const_string "ssemul") (const_string "sseadd")) - (if_then_else (match_operand:MODEF 3 "mult_operator" "") + (if_then_else (match_operand:MODEF 3 "mult_operator") (const_string "fmul") (const_string "fop")))) (set_attr "isa" "*,noavx,avx") @@ -13006,7 +13005,7 @@ && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "* return output_387_binary_op (insn, operands);" [(set (attr "type") - (if_then_else (match_operand:MODEF 3 "mult_operator" "") + (if_then_else (match_operand:MODEF 3 "mult_operator") (const_string "ssemul") (const_string "sseadd"))) (set_attr "isa" "noavx,avx") @@ -13023,7 +13022,7 @@ && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "* return output_387_binary_op (insn, operands);" [(set (attr "type") - (if_then_else (match_operand:MODEF 3 "mult_operator" "") + (if_then_else (match_operand:MODEF 3 "mult_operator") (const_string "fmul") (const_string "fop"))) (set_attr "mode" "")]) @@ -13039,16 +13038,16 @@ "* return output_387_binary_op (insn, operands);" [(set (attr "type") (cond [(and (eq_attr "alternative" "2,3") - (match_operand:MODEF 3 "mult_operator" "")) + (match_operand:MODEF 3 "mult_operator")) (const_string "ssemul") (and (eq_attr "alternative" "2,3") - (match_operand:MODEF 3 "div_operator" "")) + (match_operand:MODEF 3 "div_operator")) (const_string "ssediv") (eq_attr "alternative" "2,3") (const_string "sseadd") - (match_operand:MODEF 3 "mult_operator" "") + (match_operand:MODEF 3 "mult_operator") (const_string "fmul") - (match_operand:MODEF 3 "div_operator" "") + (match_operand:MODEF 3 "div_operator") (const_string "fdiv") ] (const_string "fop"))) @@ -13076,9 +13075,9 @@ && !COMMUTATIVE_ARITH_P (operands[3])" "* return output_387_binary_op (insn, operands);" [(set (attr "type") - (cond [(match_operand:MODEF 3 "mult_operator" "") + (cond [(match_operand:MODEF 3 "mult_operator") (const_string "ssemul") - (match_operand:MODEF 3 "div_operator" "") + (match_operand:MODEF 3 "div_operator") (const_string "ssediv") ] (const_string "sseadd"))) @@ -13098,9 +13097,9 @@ && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "* return output_387_binary_op (insn, operands);" [(set (attr "type") - (cond [(match_operand:MODEF 3 "mult_operator" "") + (cond [(match_operand:MODEF 3 "mult_operator") (const_string "fmul") - (match_operand:MODEF 3 "div_operator" "") + (match_operand:MODEF 3 "div_operator") (const_string "fdiv") ] (const_string "fop"))) @@ -13118,9 +13117,9 @@ && (TARGET_USE_MODE_FIOP || optimize_function_for_size_p (cfun))" "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" [(set (attr "type") - (cond [(match_operand:MODEF 3 "mult_operator" "") + (cond [(match_operand:MODEF 3 "mult_operator") (const_string "fmul") - (match_operand:MODEF 3 "div_operator" "") + (match_operand:MODEF 3 "div_operator") (const_string "fdiv") ] (const_string "fop"))) @@ -13138,9 +13137,9 @@ && (TARGET_USE_MODE_FIOP || optimize_function_for_size_p (cfun))" "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" [(set (attr "type") - (cond [(match_operand:MODEF 3 "mult_operator" "") + (cond [(match_operand:MODEF 3 "mult_operator") (const_string "fmul") - (match_operand:MODEF 3 "div_operator" "") + (match_operand:MODEF 3 "div_operator") (const_string "fdiv") ] (const_string "fop"))) @@ -13158,9 +13157,9 @@ && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "* return output_387_binary_op (insn, operands);" [(set (attr "type") - (cond [(match_operand:DF 3 "mult_operator" "") + (cond [(match_operand:DF 3 "mult_operator") (const_string "fmul") - (match_operand:DF 3 "div_operator" "") + (match_operand:DF 3 "div_operator") (const_string "fdiv") ] (const_string "fop"))) @@ -13176,9 +13175,9 @@ && !(TARGET_SSE2 && TARGET_SSE_MATH)" "* return output_387_binary_op (insn, operands);" [(set (attr "type") - (cond [(match_operand:DF 3 "mult_operator" "") + (cond [(match_operand:DF 3 "mult_operator") (const_string "fmul") - (match_operand:DF 3 "div_operator" "") + (match_operand:DF 3 "div_operator") (const_string "fdiv") ] (const_string "fop"))) @@ -13195,9 +13194,9 @@ && !(TARGET_SSE2 && TARGET_SSE_MATH)" "* return output_387_binary_op (insn, operands);" [(set (attr "type") - (cond [(match_operand:DF 3 "mult_operator" "") + (cond [(match_operand:DF 3 "mult_operator") (const_string "fmul") - (match_operand:DF 3 "div_operator" "") + (match_operand:DF 3 "div_operator") (const_string "fdiv") ] (const_string "fop"))) @@ -13212,7 +13211,7 @@ && COMMUTATIVE_ARITH_P (operands[3])" "* return output_387_binary_op (insn, operands);" [(set (attr "type") - (if_then_else (match_operand:XF 3 "mult_operator" "") + (if_then_else (match_operand:XF 3 "mult_operator") (const_string "fmul") (const_string "fop"))) (set_attr "mode" "XF")]) @@ -13226,9 +13225,9 @@ && !COMMUTATIVE_ARITH_P (operands[3])" "* return output_387_binary_op (insn, operands);" [(set (attr "type") - (cond [(match_operand:XF 3 "mult_operator" "") + (cond [(match_operand:XF 3 "mult_operator") (const_string "fmul") - (match_operand:XF 3 "div_operator" "") + (match_operand:XF 3 "div_operator") (const_string "fdiv") ] (const_string "fop"))) @@ -13243,9 +13242,9 @@ "TARGET_80387 && (TARGET_USE_MODE_FIOP || optimize_function_for_size_p (cfun))" "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" [(set (attr "type") - (cond [(match_operand:XF 3 "mult_operator" "") + (cond [(match_operand:XF 3 "mult_operator") (const_string "fmul") - (match_operand:XF 3 "div_operator" "") + (match_operand:XF 3 "div_operator") (const_string "fdiv") ] (const_string "fop"))) @@ -13261,9 +13260,9 @@ "TARGET_80387 && (TARGET_USE_MODE_FIOP || optimize_function_for_size_p (cfun))" "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);" [(set (attr "type") - (cond [(match_operand:XF 3 "mult_operator" "") + (cond [(match_operand:XF 3 "mult_operator") (const_string "fmul") - (match_operand:XF 3 "div_operator" "") + (match_operand:XF 3 "div_operator") (const_string "fdiv") ] (const_string "fop"))) @@ -13279,9 +13278,9 @@ "TARGET_80387" "* return output_387_binary_op (insn, operands);" [(set (attr "type") - (cond [(match_operand:XF 3 "mult_operator" "") + (cond [(match_operand:XF 3 "mult_operator") (const_string "fmul") - (match_operand:XF 3 "div_operator" "") + (match_operand:XF 3 "div_operator") (const_string "fdiv") ] (const_string "fop"))) @@ -13296,9 +13295,9 @@ "TARGET_80387" "* return output_387_binary_op (insn, operands);" [(set (attr "type") - (cond [(match_operand:XF 3 "mult_operator" "") + (cond [(match_operand:XF 3 "mult_operator") (const_string "fmul") - (match_operand:XF 3 "div_operator" "") + (match_operand:XF 3 "div_operator") (const_string "fdiv") ] (const_string "fop"))) @@ -13314,19 +13313,19 @@ "TARGET_80387" "* return output_387_binary_op (insn, operands);" [(set (attr "type") - (cond [(match_operand:XF 3 "mult_operator" "") + (cond [(match_operand:XF 3 "mult_operator") (const_string "fmul") - (match_operand:XF 3 "div_operator" "") + (match_operand:XF 3 "div_operator") (const_string "fdiv") ] (const_string "fop"))) (set_attr "mode" "")]) (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "register_operand") (match_operator 3 "binary_fp_operator" - [(float (match_operand:SWI24 1 "register_operand" "")) - (match_operand 2 "register_operand" "")]))] + [(float (match_operand:SWI24 1 "register_operand")) + (match_operand 2 "register_operand")]))] "reload_completed && X87_FLOAT_MODE_P (GET_MODE (operands[0])) && X87_ENABLE_FLOAT (GET_MODE (operands[0]), GET_MODE (operands[1]))" @@ -13344,10 +13343,10 @@ }) (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "register_operand") (match_operator 3 "binary_fp_operator" - [(match_operand 1 "register_operand" "") - (float (match_operand:SWI24 2 "register_operand" ""))]))] + [(match_operand 1 "register_operand") + (float (match_operand:SWI24 2 "register_operand"))]))] "reload_completed && X87_FLOAT_MODE_P (GET_MODE (operands[0])) && X87_ENABLE_FLOAT (GET_MODE (operands[0]), GET_MODE (operands[2]))" @@ -13414,8 +13413,8 @@ (set_attr "mode" "SF")]) (define_expand "rsqrtsf2" - [(set (match_operand:SF 0 "register_operand" "") - (unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "")] + [(set (match_operand:SF 0 "register_operand") + (unspec:SF [(match_operand:SF 1 "nonimmediate_operand")] UNSPEC_RSQRT))] "TARGET_SSE_MATH" { @@ -13438,9 +13437,9 @@ (set_attr "bdver1_decode" "*")]) (define_expand "sqrt2" - [(set (match_operand:MODEF 0 "register_operand" "") + [(set (match_operand:MODEF 0 "register_operand") (sqrt:MODEF - (match_operand:MODEF 1 "nonimmediate_operand" "")))] + (match_operand:MODEF 1 "nonimmediate_operand")))] "(TARGET_USE_FANCY_MATH_387 && X87_ENABLE_ARITH (mode)) || (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)" { @@ -13483,9 +13482,9 @@ (set_attr "mode" "XF")]) (define_expand "fmodxf3" - [(use (match_operand:XF 0 "register_operand" "")) - (use (match_operand:XF 1 "general_operand" "")) - (use (match_operand:XF 2 "general_operand" ""))] + [(use (match_operand:XF 0 "register_operand")) + (use (match_operand:XF 1 "general_operand")) + (use (match_operand:XF 2 "general_operand"))] "TARGET_USE_FANCY_MATH_387" { rtx label = gen_label_rtx (); @@ -13506,9 +13505,9 @@ }) (define_expand "fmod3" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "general_operand" "")) - (use (match_operand:MODEF 2 "general_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "general_operand")) + (use (match_operand:MODEF 2 "general_operand"))] "TARGET_USE_FANCY_MATH_387" { rtx (*gen_truncxf) (rtx, rtx); @@ -13554,9 +13553,9 @@ (set_attr "mode" "XF")]) (define_expand "remainderxf3" - [(use (match_operand:XF 0 "register_operand" "")) - (use (match_operand:XF 1 "general_operand" "")) - (use (match_operand:XF 2 "general_operand" ""))] + [(use (match_operand:XF 0 "register_operand")) + (use (match_operand:XF 1 "general_operand")) + (use (match_operand:XF 2 "general_operand"))] "TARGET_USE_FANCY_MATH_387" { rtx label = gen_label_rtx (); @@ -13577,9 +13576,9 @@ }) (define_expand "remainder3" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "general_operand" "")) - (use (match_operand:MODEF 2 "general_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "general_operand")) + (use (match_operand:MODEF 2 "general_operand"))] "TARGET_USE_FANCY_MATH_387" { rtx (*gen_truncxf) (rtx, rtx); @@ -13672,20 +13671,20 @@ (set_attr "mode" "XF")]) (define_split - [(set (match_operand:XF 0 "register_operand" "") - (unspec:XF [(match_operand:XF 2 "register_operand" "")] + [(set (match_operand:XF 0 "register_operand") + (unspec:XF [(match_operand:XF 2 "register_operand")] UNSPEC_SINCOS_COS)) - (set (match_operand:XF 1 "register_operand" "") + (set (match_operand:XF 1 "register_operand") (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))] "find_regno_note (insn, REG_UNUSED, REGNO (operands[0])) && can_create_pseudo_p ()" [(set (match_dup 1) (unspec:XF [(match_dup 2)] UNSPEC_SIN))]) (define_split - [(set (match_operand:XF 0 "register_operand" "") - (unspec:XF [(match_operand:XF 2 "register_operand" "")] + [(set (match_operand:XF 0 "register_operand") + (unspec:XF [(match_operand:XF 2 "register_operand")] UNSPEC_SINCOS_COS)) - (set (match_operand:XF 1 "register_operand" "") + (set (match_operand:XF 1 "register_operand") (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))] "find_regno_note (insn, REG_UNUSED, REGNO (operands[1])) && can_create_pseudo_p ()" @@ -13707,11 +13706,11 @@ (set_attr "mode" "XF")]) (define_split - [(set (match_operand:XF 0 "register_operand" "") + [(set (match_operand:XF 0 "register_operand") (unspec:XF [(float_extend:XF - (match_operand:MODEF 2 "register_operand" ""))] + (match_operand:MODEF 2 "register_operand"))] UNSPEC_SINCOS_COS)) - (set (match_operand:XF 1 "register_operand" "") + (set (match_operand:XF 1 "register_operand") (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))] "find_regno_note (insn, REG_UNUSED, REGNO (operands[0])) && can_create_pseudo_p ()" @@ -13719,11 +13718,11 @@ (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SIN))]) (define_split - [(set (match_operand:XF 0 "register_operand" "") + [(set (match_operand:XF 0 "register_operand") (unspec:XF [(float_extend:XF - (match_operand:MODEF 2 "register_operand" ""))] + (match_operand:MODEF 2 "register_operand"))] UNSPEC_SINCOS_COS)) - (set (match_operand:XF 1 "register_operand" "") + (set (match_operand:XF 1 "register_operand") (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))] "find_regno_note (insn, REG_UNUSED, REGNO (operands[1])) && can_create_pseudo_p ()" @@ -13731,9 +13730,9 @@ (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_COS))]) (define_expand "sincos3" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" "")) - (use (match_operand:MODEF 2 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand")) + (use (match_operand:MODEF 2 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -13778,8 +13777,8 @@ (set_attr "mode" "XF")]) (define_expand "tanxf2" - [(use (match_operand:XF 0 "register_operand" "")) - (use (match_operand:XF 1 "register_operand" ""))] + [(use (match_operand:XF 0 "register_operand")) + (use (match_operand:XF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -13791,8 +13790,8 @@ }) (define_expand "tan2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -13838,18 +13837,18 @@ (set_attr "mode" "XF")]) (define_expand "atan2xf3" - [(parallel [(set (match_operand:XF 0 "register_operand" "") - (unspec:XF [(match_operand:XF 2 "register_operand" "") - (match_operand:XF 1 "register_operand" "")] + [(parallel [(set (match_operand:XF 0 "register_operand") + (unspec:XF [(match_operand:XF 2 "register_operand") + (match_operand:XF 1 "register_operand")] UNSPEC_FPATAN)) - (clobber (match_scratch:XF 3 ""))])] + (clobber (match_scratch:XF 3))])] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations") (define_expand "atan23" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" "")) - (use (match_operand:MODEF 2 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand")) + (use (match_operand:MODEF 2 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -13863,11 +13862,11 @@ }) (define_expand "atanxf2" - [(parallel [(set (match_operand:XF 0 "register_operand" "") + [(parallel [(set (match_operand:XF 0 "register_operand") (unspec:XF [(match_dup 2) - (match_operand:XF 1 "register_operand" "")] + (match_operand:XF 1 "register_operand")] UNSPEC_FPATAN)) - (clobber (match_scratch:XF 3 ""))])] + (clobber (match_scratch:XF 3))])] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -13876,8 +13875,8 @@ }) (define_expand "atan2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -13895,14 +13894,14 @@ (define_expand "asinxf2" [(set (match_dup 2) - (mult:XF (match_operand:XF 1 "register_operand" "") + (mult:XF (match_operand:XF 1 "register_operand") (match_dup 1))) (set (match_dup 4) (minus:XF (match_dup 3) (match_dup 2))) (set (match_dup 5) (sqrt:XF (match_dup 4))) - (parallel [(set (match_operand:XF 0 "register_operand" "") + (parallel [(set (match_operand:XF 0 "register_operand") (unspec:XF [(match_dup 5) (match_dup 1)] UNSPEC_FPATAN)) - (clobber (match_scratch:XF 6 ""))])] + (clobber (match_scratch:XF 6))])] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -13918,8 +13917,8 @@ }) (define_expand "asin2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "general_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "general_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -13939,14 +13938,14 @@ (define_expand "acosxf2" [(set (match_dup 2) - (mult:XF (match_operand:XF 1 "register_operand" "") + (mult:XF (match_operand:XF 1 "register_operand") (match_dup 1))) (set (match_dup 4) (minus:XF (match_dup 3) (match_dup 2))) (set (match_dup 5) (sqrt:XF (match_dup 4))) - (parallel [(set (match_operand:XF 0 "register_operand" "") + (parallel [(set (match_operand:XF 0 "register_operand") (unspec:XF [(match_dup 1) (match_dup 5)] UNSPEC_FPATAN)) - (clobber (match_scratch:XF 6 ""))])] + (clobber (match_scratch:XF 6))])] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -13962,8 +13961,8 @@ }) (define_expand "acos2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "general_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "general_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14009,10 +14008,10 @@ (set_attr "mode" "XF")]) (define_expand "logxf2" - [(parallel [(set (match_operand:XF 0 "register_operand" "") - (unspec:XF [(match_operand:XF 1 "register_operand" "") + [(parallel [(set (match_operand:XF 0 "register_operand") + (unspec:XF [(match_operand:XF 1 "register_operand") (match_dup 2)] UNSPEC_FYL2X)) - (clobber (match_scratch:XF 3 ""))])] + (clobber (match_scratch:XF 3))])] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -14021,8 +14020,8 @@ }) (define_expand "log2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14039,10 +14038,10 @@ }) (define_expand "log10xf2" - [(parallel [(set (match_operand:XF 0 "register_operand" "") - (unspec:XF [(match_operand:XF 1 "register_operand" "") + [(parallel [(set (match_operand:XF 0 "register_operand") + (unspec:XF [(match_operand:XF 1 "register_operand") (match_dup 2)] UNSPEC_FYL2X)) - (clobber (match_scratch:XF 3 ""))])] + (clobber (match_scratch:XF 3))])] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -14051,8 +14050,8 @@ }) (define_expand "log102" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14069,10 +14068,10 @@ }) (define_expand "log2xf2" - [(parallel [(set (match_operand:XF 0 "register_operand" "") - (unspec:XF [(match_operand:XF 1 "register_operand" "") + [(parallel [(set (match_operand:XF 0 "register_operand") + (unspec:XF [(match_operand:XF 1 "register_operand") (match_dup 2)] UNSPEC_FYL2X)) - (clobber (match_scratch:XF 3 ""))])] + (clobber (match_scratch:XF 3))])] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -14081,8 +14080,8 @@ }) (define_expand "log22" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14126,8 +14125,8 @@ (set_attr "mode" "XF")]) (define_expand "log1pxf2" - [(use (match_operand:XF 0 "register_operand" "")) - (use (match_operand:XF 1 "register_operand" ""))] + [(use (match_operand:XF 0 "register_operand")) + (use (match_operand:XF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -14139,8 +14138,8 @@ }) (define_expand "log1p2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14189,17 +14188,17 @@ (define_expand "logbxf2" [(parallel [(set (match_dup 2) - (unspec:XF [(match_operand:XF 1 "register_operand" "")] + (unspec:XF [(match_operand:XF 1 "register_operand")] UNSPEC_XTRACT_FRACT)) - (set (match_operand:XF 0 "register_operand" "") + (set (match_operand:XF 0 "register_operand") (unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" "operands[2] = gen_reg_rtx (XFmode);") (define_expand "logb2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14214,8 +14213,8 @@ }) (define_expand "ilogbxf2" - [(use (match_operand:SI 0 "register_operand" "")) - (use (match_operand:XF 1 "register_operand" ""))] + [(use (match_operand:SI 0 "register_operand")) + (use (match_operand:XF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -14233,8 +14232,8 @@ }) (define_expand "ilogb2" - [(use (match_operand:SI 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" ""))] + [(use (match_operand:SI 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14278,13 +14277,13 @@ (set_attr "mode" "XF")]) (define_expand "expNcorexf3" - [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "") - (match_operand:XF 2 "register_operand" ""))) + [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand") + (match_operand:XF 2 "register_operand"))) (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT)) (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4))) (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1)) (set (match_dup 8) (plus:XF (match_dup 6) (match_dup 7))) - (parallel [(set (match_operand:XF 0 "register_operand" "") + (parallel [(set (match_operand:XF 0 "register_operand") (unspec:XF [(match_dup 8) (match_dup 4)] UNSPEC_FSCALE_FRACT)) (set (match_dup 9) @@ -14305,8 +14304,8 @@ }) (define_expand "expxf2" - [(use (match_operand:XF 0 "register_operand" "")) - (use (match_operand:XF 1 "register_operand" ""))] + [(use (match_operand:XF 0 "register_operand")) + (use (match_operand:XF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -14323,8 +14322,8 @@ }) (define_expand "exp2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "general_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "general_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14345,8 +14344,8 @@ }) (define_expand "exp10xf2" - [(use (match_operand:XF 0 "register_operand" "")) - (use (match_operand:XF 1 "register_operand" ""))] + [(use (match_operand:XF 0 "register_operand")) + (use (match_operand:XF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -14363,8 +14362,8 @@ }) (define_expand "exp102" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "general_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "general_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14385,8 +14384,8 @@ }) (define_expand "exp2xf2" - [(use (match_operand:XF 0 "register_operand" "")) - (use (match_operand:XF 1 "register_operand" ""))] + [(use (match_operand:XF 0 "register_operand")) + (use (match_operand:XF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -14403,8 +14402,8 @@ }) (define_expand "exp22" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "general_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "general_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14425,7 +14424,7 @@ }) (define_expand "expm1xf2" - [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "") + [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand") (match_dup 2))) (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT)) (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4))) @@ -14445,7 +14444,7 @@ UNSPEC_FSCALE_EXP))]) (set (match_dup 12) (minus:XF (match_dup 10) (float_extend:XF (match_dup 13)))) - (set (match_operand:XF 0 "register_operand" "") + (set (match_operand:XF 0 "register_operand") (plus:XF (match_dup 12) (match_dup 7)))] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" @@ -14465,8 +14464,8 @@ }) (define_expand "expm12" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "general_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "general_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14488,9 +14487,9 @@ (define_expand "ldexpxf3" [(set (match_dup 3) - (float:XF (match_operand:SI 2 "register_operand" ""))) - (parallel [(set (match_operand:XF 0 " register_operand" "") - (unspec:XF [(match_operand:XF 1 "register_operand" "") + (float:XF (match_operand:SI 2 "register_operand"))) + (parallel [(set (match_operand:XF 0 " register_operand") + (unspec:XF [(match_operand:XF 1 "register_operand") (match_dup 3)] UNSPEC_FSCALE_FRACT)) (set (match_dup 4) @@ -14507,9 +14506,9 @@ }) (define_expand "ldexp3" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "general_operand" "")) - (use (match_operand:SI 2 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "general_operand")) + (use (match_operand:SI 2 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14530,9 +14529,9 @@ }) (define_expand "scalbxf3" - [(parallel [(set (match_operand:XF 0 " register_operand" "") - (unspec:XF [(match_operand:XF 1 "register_operand" "") - (match_operand:XF 2 "register_operand" "")] + [(parallel [(set (match_operand:XF 0 " register_operand") + (unspec:XF [(match_operand:XF 1 "register_operand") + (match_operand:XF 2 "register_operand")] UNSPEC_FSCALE_FRACT)) (set (match_dup 3) (unspec:XF [(match_dup 1) (match_dup 2)] @@ -14547,9 +14546,9 @@ }) (define_expand "scalb3" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "general_operand" "")) - (use (match_operand:MODEF 2 "general_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "general_operand")) + (use (match_operand:MODEF 2 "general_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14572,8 +14571,8 @@ }) (define_expand "significandxf2" - [(parallel [(set (match_operand:XF 0 "register_operand" "") - (unspec:XF [(match_operand:XF 1 "register_operand" "")] + [(parallel [(set (match_operand:XF 0 "register_operand") + (unspec:XF [(match_operand:XF 1 "register_operand")] UNSPEC_XTRACT_FRACT)) (set (match_dup 2) (unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])] @@ -14582,8 +14581,8 @@ "operands[2] = gen_reg_rtx (XFmode);") (define_expand "significand2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14621,8 +14620,8 @@ (set_attr "mode" "XF")]) (define_expand "rint2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand"))] "(TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14639,7 +14638,7 @@ else if (optimize_insn_for_size_p ()) FAIL; else - ix86_expand_rint (operand0, operand1); + ix86_expand_rint (operands[0], operands[1]); } else { @@ -14655,8 +14654,8 @@ }) (define_expand "round2" - [(match_operand:X87MODEF 0 "register_operand" "") - (match_operand:X87MODEF 1 "nonimmediate_operand" "")] + [(match_operand:X87MODEF 0 "register_operand") + (match_operand:X87MODEF 1 "nonimmediate_operand")] "(TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14689,8 +14688,8 @@ }) (define_insn_and_split "*fistdi2_1" - [(set (match_operand:DI 0 "nonimmediate_operand" "") - (unspec:DI [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:DI 0 "nonimmediate_operand") + (unspec:DI [(match_operand:XF 1 "register_operand")] UNSPEC_FIST))] "TARGET_USE_FANCY_MATH_387 && can_create_pseudo_p ()" @@ -14733,29 +14732,29 @@ (set_attr "mode" "DI")]) (define_split - [(set (match_operand:DI 0 "register_operand" "") - (unspec:DI [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:DI 0 "register_operand") + (unspec:DI [(match_operand:XF 1 "register_operand")] UNSPEC_FIST)) - (clobber (match_operand:DI 2 "memory_operand" "")) - (clobber (match_scratch 3 ""))] + (clobber (match_operand:DI 2 "memory_operand")) + (clobber (match_scratch 3))] "reload_completed" [(parallel [(set (match_dup 2) (unspec:DI [(match_dup 1)] UNSPEC_FIST)) (clobber (match_dup 3))]) (set (match_dup 0) (match_dup 2))]) (define_split - [(set (match_operand:DI 0 "memory_operand" "") - (unspec:DI [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:DI 0 "memory_operand") + (unspec:DI [(match_operand:XF 1 "register_operand")] UNSPEC_FIST)) - (clobber (match_operand:DI 2 "memory_operand" "")) - (clobber (match_scratch 3 ""))] + (clobber (match_operand:DI 2 "memory_operand")) + (clobber (match_scratch 3))] "reload_completed" [(parallel [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_FIST)) (clobber (match_dup 3))])]) (define_insn_and_split "*fist2_1" - [(set (match_operand:SWI24 0 "register_operand" "") - (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:SWI24 0 "register_operand") + (unspec:SWI24 [(match_operand:XF 1 "register_operand")] UNSPEC_FIST))] "TARGET_USE_FANCY_MATH_387 && can_create_pseudo_p ()" @@ -14791,38 +14790,38 @@ (set_attr "mode" "")]) (define_split - [(set (match_operand:SWI24 0 "register_operand" "") - (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:SWI24 0 "register_operand") + (unspec:SWI24 [(match_operand:XF 1 "register_operand")] UNSPEC_FIST)) - (clobber (match_operand:SWI24 2 "memory_operand" ""))] + (clobber (match_operand:SWI24 2 "memory_operand"))] "reload_completed" [(set (match_dup 2) (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST)) (set (match_dup 0) (match_dup 2))]) (define_split - [(set (match_operand:SWI24 0 "memory_operand" "") - (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:SWI24 0 "memory_operand") + (unspec:SWI24 [(match_operand:XF 1 "register_operand")] UNSPEC_FIST)) - (clobber (match_operand:SWI24 2 "memory_operand" ""))] + (clobber (match_operand:SWI24 2 "memory_operand"))] "reload_completed" [(set (match_dup 0) (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST))]) (define_expand "lrintxf2" - [(set (match_operand:SWI248x 0 "nonimmediate_operand" "") - (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:SWI248x 0 "nonimmediate_operand") + (unspec:SWI248x [(match_operand:XF 1 "register_operand")] UNSPEC_FIST))] "TARGET_USE_FANCY_MATH_387") (define_expand "lrint2" - [(set (match_operand:SWI48x 0 "nonimmediate_operand" "") - (unspec:SWI48x [(match_operand:MODEF 1 "register_operand" "")] + [(set (match_operand:SWI48x 0 "nonimmediate_operand") + (unspec:SWI48x [(match_operand:MODEF 1 "register_operand")] UNSPEC_FIX_NOTRUNC))] "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH && ((mode != DImode) || TARGET_64BIT)") (define_expand "lround2" - [(match_operand:SWI248x 0 "nonimmediate_operand" "") - (match_operand:X87MODEF 1 "register_operand" "")] + [(match_operand:SWI248x 0 "nonimmediate_operand") + (match_operand:X87MODEF 1 "register_operand")] "(TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14839,7 +14838,7 @@ && mode != HImode && ((mode != DImode) || TARGET_64BIT) && !flag_trapping_math && !flag_rounding_math) - ix86_expand_lround (operand0, operand1); + ix86_expand_lround (operands[0], operands[1]); else ix86_emit_i387_round (operands[0], operands[1]); DONE; @@ -14847,8 +14846,8 @@ ;; Rounding mode control word calculation could clobber FLAGS_REG. (define_insn_and_split "frndintxf2_floor" - [(set (match_operand:XF 0 "register_operand" "") - (unspec:XF [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:XF 0 "register_operand") + (unspec:XF [(match_operand:XF 1 "register_operand")] UNSPEC_FRNDINT_FLOOR)) (clobber (reg:CC FLAGS_REG))] "TARGET_USE_FANCY_MATH_387 @@ -14885,8 +14884,8 @@ (set_attr "mode" "XF")]) (define_expand "floorxf2" - [(use (match_operand:XF 0 "register_operand" "")) - (use (match_operand:XF 1 "register_operand" ""))] + [(use (match_operand:XF 0 "register_operand")) + (use (match_operand:XF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -14897,8 +14896,8 @@ }) (define_expand "floor2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand"))] "(TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -14915,9 +14914,9 @@ else if (optimize_insn_for_size_p ()) FAIL; else if (TARGET_64BIT || (mode != DFmode)) - ix86_expand_floorceil (operand0, operand1, true); + ix86_expand_floorceil (operands[0], operands[1], true); else - ix86_expand_floorceildf_32 (operand0, operand1, true); + ix86_expand_floorceildf_32 (operands[0], operands[1], true); } else { @@ -14937,8 +14936,8 @@ }) (define_insn_and_split "*fist2_floor_1" - [(set (match_operand:SWI248x 0 "nonimmediate_operand" "") - (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:SWI248x 0 "nonimmediate_operand") + (unspec:SWI248x [(match_operand:XF 1 "register_operand")] UNSPEC_FIST_FLOOR)) (clobber (reg:CC FLAGS_REG))] "TARGET_USE_FANCY_MATH_387 @@ -14998,13 +14997,13 @@ (set_attr "mode" "DI")]) (define_split - [(set (match_operand:DI 0 "register_operand" "") - (unspec:DI [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:DI 0 "register_operand") + (unspec:DI [(match_operand:XF 1 "register_operand")] UNSPEC_FIST_FLOOR)) - (use (match_operand:HI 2 "memory_operand" "")) - (use (match_operand:HI 3 "memory_operand" "")) - (clobber (match_operand:DI 4 "memory_operand" "")) - (clobber (match_scratch 5 ""))] + (use (match_operand:HI 2 "memory_operand")) + (use (match_operand:HI 3 "memory_operand")) + (clobber (match_operand:DI 4 "memory_operand")) + (clobber (match_scratch 5))] "reload_completed" [(parallel [(set (match_dup 4) (unspec:DI [(match_dup 1)] UNSPEC_FIST_FLOOR)) @@ -15014,13 +15013,13 @@ (set (match_dup 0) (match_dup 4))]) (define_split - [(set (match_operand:DI 0 "memory_operand" "") - (unspec:DI [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:DI 0 "memory_operand") + (unspec:DI [(match_operand:XF 1 "register_operand")] UNSPEC_FIST_FLOOR)) - (use (match_operand:HI 2 "memory_operand" "")) - (use (match_operand:HI 3 "memory_operand" "")) - (clobber (match_operand:DI 4 "memory_operand" "")) - (clobber (match_scratch 5 ""))] + (use (match_operand:HI 2 "memory_operand")) + (use (match_operand:HI 3 "memory_operand")) + (clobber (match_operand:DI 4 "memory_operand")) + (clobber (match_scratch 5))] "reload_completed" [(parallel [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_FIST_FLOOR)) @@ -15056,12 +15055,12 @@ (set_attr "mode" "")]) (define_split - [(set (match_operand:SWI24 0 "register_operand" "") - (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:SWI24 0 "register_operand") + (unspec:SWI24 [(match_operand:XF 1 "register_operand")] UNSPEC_FIST_FLOOR)) - (use (match_operand:HI 2 "memory_operand" "")) - (use (match_operand:HI 3 "memory_operand" "")) - (clobber (match_operand:SWI24 4 "memory_operand" ""))] + (use (match_operand:HI 2 "memory_operand")) + (use (match_operand:HI 3 "memory_operand")) + (clobber (match_operand:SWI24 4 "memory_operand"))] "reload_completed" [(parallel [(set (match_dup 4) (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST_FLOOR)) @@ -15070,12 +15069,12 @@ (set (match_dup 0) (match_dup 4))]) (define_split - [(set (match_operand:SWI24 0 "memory_operand" "") - (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:SWI24 0 "memory_operand") + (unspec:SWI24 [(match_operand:XF 1 "register_operand")] UNSPEC_FIST_FLOOR)) - (use (match_operand:HI 2 "memory_operand" "")) - (use (match_operand:HI 3 "memory_operand" "")) - (clobber (match_operand:SWI24 4 "memory_operand" ""))] + (use (match_operand:HI 2 "memory_operand")) + (use (match_operand:HI 3 "memory_operand")) + (clobber (match_operand:SWI24 4 "memory_operand"))] "reload_completed" [(parallel [(set (match_dup 0) (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST_FLOOR)) @@ -15083,8 +15082,8 @@ (use (match_dup 3))])]) (define_expand "lfloorxf2" - [(parallel [(set (match_operand:SWI248x 0 "nonimmediate_operand" "") - (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")] + [(parallel [(set (match_operand:SWI248x 0 "nonimmediate_operand") + (unspec:SWI248x [(match_operand:XF 1 "register_operand")] UNSPEC_FIST_FLOOR)) (clobber (reg:CC FLAGS_REG))])] "TARGET_USE_FANCY_MATH_387 @@ -15092,21 +15091,21 @@ && flag_unsafe_math_optimizations") (define_expand "lfloor2" - [(match_operand:SWI48 0 "nonimmediate_operand" "") - (match_operand:MODEF 1 "register_operand" "")] + [(match_operand:SWI48 0 "nonimmediate_operand") + (match_operand:MODEF 1 "register_operand")] "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH && !flag_trapping_math" { if (TARGET_64BIT && optimize_insn_for_size_p ()) FAIL; - ix86_expand_lfloorceil (operand0, operand1, true); + ix86_expand_lfloorceil (operands[0], operands[1], true); DONE; }) ;; Rounding mode control word calculation could clobber FLAGS_REG. (define_insn_and_split "frndintxf2_ceil" - [(set (match_operand:XF 0 "register_operand" "") - (unspec:XF [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:XF 0 "register_operand") + (unspec:XF [(match_operand:XF 1 "register_operand")] UNSPEC_FRNDINT_CEIL)) (clobber (reg:CC FLAGS_REG))] "TARGET_USE_FANCY_MATH_387 @@ -15143,8 +15142,8 @@ (set_attr "mode" "XF")]) (define_expand "ceilxf2" - [(use (match_operand:XF 0 "register_operand" "")) - (use (match_operand:XF 1 "register_operand" ""))] + [(use (match_operand:XF 0 "register_operand")) + (use (match_operand:XF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -15155,8 +15154,8 @@ }) (define_expand "ceil2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand"))] "(TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -15173,9 +15172,9 @@ else if (optimize_insn_for_size_p ()) FAIL; else if (TARGET_64BIT || (mode != DFmode)) - ix86_expand_floorceil (operand0, operand1, false); + ix86_expand_floorceil (operands[0], operands[1], false); else - ix86_expand_floorceildf_32 (operand0, operand1, false); + ix86_expand_floorceildf_32 (operands[0], operands[1], false); } else { @@ -15195,8 +15194,8 @@ }) (define_insn_and_split "*fist2_ceil_1" - [(set (match_operand:SWI248x 0 "nonimmediate_operand" "") - (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:SWI248x 0 "nonimmediate_operand") + (unspec:SWI248x [(match_operand:XF 1 "register_operand")] UNSPEC_FIST_CEIL)) (clobber (reg:CC FLAGS_REG))] "TARGET_USE_FANCY_MATH_387 @@ -15256,13 +15255,13 @@ (set_attr "mode" "DI")]) (define_split - [(set (match_operand:DI 0 "register_operand" "") - (unspec:DI [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:DI 0 "register_operand") + (unspec:DI [(match_operand:XF 1 "register_operand")] UNSPEC_FIST_CEIL)) - (use (match_operand:HI 2 "memory_operand" "")) - (use (match_operand:HI 3 "memory_operand" "")) - (clobber (match_operand:DI 4 "memory_operand" "")) - (clobber (match_scratch 5 ""))] + (use (match_operand:HI 2 "memory_operand")) + (use (match_operand:HI 3 "memory_operand")) + (clobber (match_operand:DI 4 "memory_operand")) + (clobber (match_scratch 5))] "reload_completed" [(parallel [(set (match_dup 4) (unspec:DI [(match_dup 1)] UNSPEC_FIST_CEIL)) @@ -15272,13 +15271,13 @@ (set (match_dup 0) (match_dup 4))]) (define_split - [(set (match_operand:DI 0 "memory_operand" "") - (unspec:DI [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:DI 0 "memory_operand") + (unspec:DI [(match_operand:XF 1 "register_operand")] UNSPEC_FIST_CEIL)) - (use (match_operand:HI 2 "memory_operand" "")) - (use (match_operand:HI 3 "memory_operand" "")) - (clobber (match_operand:DI 4 "memory_operand" "")) - (clobber (match_scratch 5 ""))] + (use (match_operand:HI 2 "memory_operand")) + (use (match_operand:HI 3 "memory_operand")) + (clobber (match_operand:DI 4 "memory_operand")) + (clobber (match_scratch 5))] "reload_completed" [(parallel [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_FIST_CEIL)) @@ -15314,12 +15313,12 @@ (set_attr "mode" "")]) (define_split - [(set (match_operand:SWI24 0 "register_operand" "") - (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:SWI24 0 "register_operand") + (unspec:SWI24 [(match_operand:XF 1 "register_operand")] UNSPEC_FIST_CEIL)) - (use (match_operand:HI 2 "memory_operand" "")) - (use (match_operand:HI 3 "memory_operand" "")) - (clobber (match_operand:SWI24 4 "memory_operand" ""))] + (use (match_operand:HI 2 "memory_operand")) + (use (match_operand:HI 3 "memory_operand")) + (clobber (match_operand:SWI24 4 "memory_operand"))] "reload_completed" [(parallel [(set (match_dup 4) (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST_CEIL)) @@ -15328,12 +15327,12 @@ (set (match_dup 0) (match_dup 4))]) (define_split - [(set (match_operand:SWI24 0 "memory_operand" "") - (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:SWI24 0 "memory_operand") + (unspec:SWI24 [(match_operand:XF 1 "register_operand")] UNSPEC_FIST_CEIL)) - (use (match_operand:HI 2 "memory_operand" "")) - (use (match_operand:HI 3 "memory_operand" "")) - (clobber (match_operand:SWI24 4 "memory_operand" ""))] + (use (match_operand:HI 2 "memory_operand")) + (use (match_operand:HI 3 "memory_operand")) + (clobber (match_operand:SWI24 4 "memory_operand"))] "reload_completed" [(parallel [(set (match_dup 0) (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST_CEIL)) @@ -15341,8 +15340,8 @@ (use (match_dup 3))])]) (define_expand "lceilxf2" - [(parallel [(set (match_operand:SWI248x 0 "nonimmediate_operand" "") - (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")] + [(parallel [(set (match_operand:SWI248x 0 "nonimmediate_operand") + (unspec:SWI248x [(match_operand:XF 1 "register_operand")] UNSPEC_FIST_CEIL)) (clobber (reg:CC FLAGS_REG))])] "TARGET_USE_FANCY_MATH_387 @@ -15350,19 +15349,19 @@ && flag_unsafe_math_optimizations") (define_expand "lceil2" - [(match_operand:SWI48 0 "nonimmediate_operand" "") - (match_operand:MODEF 1 "register_operand" "")] + [(match_operand:SWI48 0 "nonimmediate_operand") + (match_operand:MODEF 1 "register_operand")] "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH && !flag_trapping_math" { - ix86_expand_lfloorceil (operand0, operand1, false); + ix86_expand_lfloorceil (operands[0], operands[1], false); DONE; }) ;; Rounding mode control word calculation could clobber FLAGS_REG. (define_insn_and_split "frndintxf2_trunc" - [(set (match_operand:XF 0 "register_operand" "") - (unspec:XF [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:XF 0 "register_operand") + (unspec:XF [(match_operand:XF 1 "register_operand")] UNSPEC_FRNDINT_TRUNC)) (clobber (reg:CC FLAGS_REG))] "TARGET_USE_FANCY_MATH_387 @@ -15399,8 +15398,8 @@ (set_attr "mode" "XF")]) (define_expand "btruncxf2" - [(use (match_operand:XF 0 "register_operand" "")) - (use (match_operand:XF 1 "register_operand" ""))] + [(use (match_operand:XF 0 "register_operand")) + (use (match_operand:XF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -15411,8 +15410,8 @@ }) (define_expand "btrunc2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand"))] "(TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -15429,9 +15428,9 @@ else if (optimize_insn_for_size_p ()) FAIL; else if (TARGET_64BIT || (mode != DFmode)) - ix86_expand_trunc (operand0, operand1); + ix86_expand_trunc (operands[0], operands[1]); else - ix86_expand_truncdf_32 (operand0, operand1); + ix86_expand_truncdf_32 (operands[0], operands[1]); } else { @@ -15452,8 +15451,8 @@ ;; Rounding mode control word calculation could clobber FLAGS_REG. (define_insn_and_split "frndintxf2_mask_pm" - [(set (match_operand:XF 0 "register_operand" "") - (unspec:XF [(match_operand:XF 1 "register_operand" "")] + [(set (match_operand:XF 0 "register_operand") + (unspec:XF [(match_operand:XF 1 "register_operand")] UNSPEC_FRNDINT_MASK_PM)) (clobber (reg:CC FLAGS_REG))] "TARGET_USE_FANCY_MATH_387 @@ -15490,8 +15489,8 @@ (set_attr "mode" "XF")]) (define_expand "nearbyintxf2" - [(use (match_operand:XF 0 "register_operand" "")) - (use (match_operand:XF 1 "register_operand" ""))] + [(use (match_operand:XF 0 "register_operand")) + (use (match_operand:XF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { @@ -15500,8 +15499,8 @@ }) (define_expand "nearbyint2" - [(use (match_operand:MODEF 0 "register_operand" "")) - (use (match_operand:MODEF 1 "register_operand" ""))] + [(use (match_operand:MODEF 0 "register_operand")) + (use (match_operand:MODEF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -15530,9 +15529,9 @@ (set_attr "mode" "")]) (define_insn_and_split "fxam2_i387_with_temp" - [(set (match_operand:HI 0 "register_operand" "") + [(set (match_operand:HI 0 "register_operand") (unspec:HI - [(match_operand:MODEF 1 "memory_operand" "")] + [(match_operand:MODEF 1 "memory_operand")] UNSPEC_FXAM_MEM))] "TARGET_USE_FANCY_MATH_387 && can_create_pseudo_p ()" @@ -15551,8 +15550,8 @@ (set_attr "mode" "")]) (define_expand "isinfxf2" - [(use (match_operand:SI 0 "register_operand" "")) - (use (match_operand:XF 1 "register_operand" ""))] + [(use (match_operand:SI 0 "register_operand")) + (use (match_operand:XF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && TARGET_C99_FUNCTIONS" { @@ -15577,8 +15576,8 @@ }) (define_expand "isinf2" - [(use (match_operand:SI 0 "register_operand" "")) - (use (match_operand:MODEF 1 "nonimmediate_operand" ""))] + [(use (match_operand:SI 0 "register_operand")) + (use (match_operand:MODEF 1 "nonimmediate_operand"))] "TARGET_USE_FANCY_MATH_387 && TARGET_C99_FUNCTIONS && !(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)" @@ -15616,8 +15615,8 @@ }) (define_expand "signbitxf2" - [(use (match_operand:SI 0 "register_operand" "")) - (use (match_operand:XF 1 "register_operand" ""))] + [(use (match_operand:SI 0 "register_operand")) + (use (match_operand:XF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387" { rtx scratch = gen_reg_rtx (HImode); @@ -15642,8 +15641,8 @@ ;; Use movmskpd in SSE mode to avoid store forwarding stall ;; for 32bit targets and movq+shrq sequence for 64bit targets. (define_expand "signbitdf2" - [(use (match_operand:SI 0 "register_operand" "")) - (use (match_operand:DF 1 "register_operand" ""))] + [(use (match_operand:SI 0 "register_operand")) + (use (match_operand:DF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 || (SSE_FLOAT_MODE_P (DFmode) && TARGET_SSE_MATH)" { @@ -15664,8 +15663,8 @@ }) (define_expand "signbitsf2" - [(use (match_operand:SI 0 "register_operand" "")) - (use (match_operand:SF 1 "register_operand" ""))] + [(use (match_operand:SI 0 "register_operand")) + (use (match_operand:SF 1 "register_operand"))] "TARGET_USE_FANCY_MATH_387 && !(SSE_FLOAT_MODE_P (SFmode) && TARGET_SSE_MATH)" { @@ -15688,12 +15687,12 @@ (set_attr "modrm" "0")]) (define_expand "movmem" - [(use (match_operand:BLK 0 "memory_operand" "")) - (use (match_operand:BLK 1 "memory_operand" "")) - (use (match_operand:SWI48 2 "nonmemory_operand" "")) - (use (match_operand:SWI48 3 "const_int_operand" "")) - (use (match_operand:SI 4 "const_int_operand" "")) - (use (match_operand:SI 5 "const_int_operand" ""))] + [(use (match_operand:BLK 0 "memory_operand")) + (use (match_operand:BLK 1 "memory_operand")) + (use (match_operand:SWI48 2 "nonmemory_operand")) + (use (match_operand:SWI48 3 "const_int_operand")) + (use (match_operand:SI 4 "const_int_operand")) + (use (match_operand:SI 5 "const_int_operand"))] "" { if (ix86_expand_movmem (operands[0], operands[1], operands[2], operands[3], @@ -15707,11 +15706,11 @@ ;; Handle this case here to simplify previous expander. (define_expand "strmov" - [(set (match_dup 4) (match_operand 3 "memory_operand" "")) - (set (match_operand 1 "memory_operand" "") (match_dup 4)) - (parallel [(set (match_operand 0 "register_operand" "") (match_dup 5)) + [(set (match_dup 4) (match_operand 3 "memory_operand")) + (set (match_operand 1 "memory_operand") (match_dup 4)) + (parallel [(set (match_operand 0 "register_operand") (match_dup 5)) (clobber (reg:CC FLAGS_REG))]) - (parallel [(set (match_operand 2 "register_operand" "") (match_dup 6)) + (parallel [(set (match_operand 2 "register_operand") (match_dup 6)) (clobber (reg:CC FLAGS_REG))])] "" { @@ -15736,27 +15735,27 @@ }) (define_expand "strmov_singleop" - [(parallel [(set (match_operand 1 "memory_operand" "") - (match_operand 3 "memory_operand" "")) - (set (match_operand 0 "register_operand" "") - (match_operand 4 "" "")) - (set (match_operand 2 "register_operand" "") - (match_operand 5 "" ""))])] + [(parallel [(set (match_operand 1 "memory_operand") + (match_operand 3 "memory_operand")) + (set (match_operand 0 "register_operand") + (match_operand 4)) + (set (match_operand 2 "register_operand") + (match_operand 5))])] "" "ix86_current_function_needs_cld = 1;") (define_insn "*strmovdi_rex_1" - [(set (mem:DI (match_operand:DI 2 "register_operand" "0")) - (mem:DI (match_operand:DI 3 "register_operand" "1"))) - (set (match_operand:DI 0 "register_operand" "=D") - (plus:DI (match_dup 2) - (const_int 8))) - (set (match_operand:DI 1 "register_operand" "=S") - (plus:DI (match_dup 3) - (const_int 8)))] + [(set (mem:DI (match_operand:P 2 "register_operand" "0")) + (mem:DI (match_operand:P 3 "register_operand" "1"))) + (set (match_operand:P 0 "register_operand" "=D") + (plus:P (match_dup 2) + (const_int 8))) + (set (match_operand:P 1 "register_operand" "=S") + (plus:P (match_dup 3) + (const_int 8)))] "TARGET_64BIT && !(fixed_regs[SI_REG] || fixed_regs[DI_REG])" - "movsq" + "%^movsq" [(set_attr "type" "str") (set_attr "memory" "both") (set_attr "mode" "DI")]) @@ -15771,7 +15770,7 @@ (plus:P (match_dup 3) (const_int 4)))] "!(fixed_regs[SI_REG] || fixed_regs[DI_REG])" - "movs{l|d}" + "%^movs{l|d}" [(set_attr "type" "str") (set_attr "memory" "both") (set_attr "mode" "SI")]) @@ -15786,7 +15785,7 @@ (plus:P (match_dup 3) (const_int 2)))] "!(fixed_regs[SI_REG] || fixed_regs[DI_REG])" - "movsw" + "%^movsw" [(set_attr "type" "str") (set_attr "memory" "both") (set_attr "mode" "HI")]) @@ -15801,7 +15800,7 @@ (plus:P (match_dup 3) (const_int 1)))] "!(fixed_regs[SI_REG] || fixed_regs[DI_REG])" - "movsb" + "%^movsb" [(set_attr "type" "str") (set_attr "memory" "both") (set (attr "prefix_rex") @@ -15812,32 +15811,32 @@ (set_attr "mode" "QI")]) (define_expand "rep_mov" - [(parallel [(set (match_operand 4 "register_operand" "") (const_int 0)) - (set (match_operand 0 "register_operand" "") - (match_operand 5 "" "")) - (set (match_operand 2 "register_operand" "") - (match_operand 6 "" "")) - (set (match_operand 1 "memory_operand" "") - (match_operand 3 "memory_operand" "")) + [(parallel [(set (match_operand 4 "register_operand") (const_int 0)) + (set (match_operand 0 "register_operand") + (match_operand 5)) + (set (match_operand 2 "register_operand") + (match_operand 6)) + (set (match_operand 1 "memory_operand") + (match_operand 3 "memory_operand")) (use (match_dup 4))])] "" "ix86_current_function_needs_cld = 1;") (define_insn "*rep_movdi_rex64" - [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0)) - (set (match_operand:DI 0 "register_operand" "=D") - (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2") - (const_int 3)) - (match_operand:DI 3 "register_operand" "0"))) - (set (match_operand:DI 1 "register_operand" "=S") - (plus:DI (ashift:DI (match_dup 5) (const_int 3)) - (match_operand:DI 4 "register_operand" "1"))) + [(set (match_operand:P 2 "register_operand" "=c") (const_int 0)) + (set (match_operand:P 0 "register_operand" "=D") + (plus:P (ashift:P (match_operand:P 5 "register_operand" "2") + (const_int 3)) + (match_operand:P 3 "register_operand" "0"))) + (set (match_operand:P 1 "register_operand" "=S") + (plus:P (ashift:P (match_dup 5) (const_int 3)) + (match_operand:P 4 "register_operand" "1"))) (set (mem:BLK (match_dup 3)) (mem:BLK (match_dup 4))) (use (match_dup 5))] "TARGET_64BIT && !(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])" - "rep{%;} movsq" + "%^rep{%;} movsq" [(set_attr "type" "str") (set_attr "prefix_rep" "1") (set_attr "memory" "both") @@ -15856,7 +15855,7 @@ (mem:BLK (match_dup 4))) (use (match_dup 5))] "!(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])" - "rep{%;} movs{l|d}" + "%^rep{%;} movs{l|d}" [(set_attr "type" "str") (set_attr "prefix_rep" "1") (set_attr "memory" "both") @@ -15873,19 +15872,19 @@ (mem:BLK (match_dup 4))) (use (match_dup 5))] "!(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])" - "rep{%;} movsb" + "%^rep{%;} movsb" [(set_attr "type" "str") (set_attr "prefix_rep" "1") (set_attr "memory" "both") (set_attr "mode" "QI")]) (define_expand "setmem" - [(use (match_operand:BLK 0 "memory_operand" "")) - (use (match_operand:SWI48 1 "nonmemory_operand" "")) - (use (match_operand:QI 2 "nonmemory_operand" "")) - (use (match_operand 3 "const_int_operand" "")) - (use (match_operand:SI 4 "const_int_operand" "")) - (use (match_operand:SI 5 "const_int_operand" ""))] + [(use (match_operand:BLK 0 "memory_operand")) + (use (match_operand:SWI48 1 "nonmemory_operand")) + (use (match_operand:QI 2 "nonmemory_operand")) + (use (match_operand 3 "const_int_operand")) + (use (match_operand:SI 4 "const_int_operand")) + (use (match_operand:SI 5 "const_int_operand"))] "" { if (ix86_expand_setmem (operands[0], operands[1], @@ -15900,9 +15899,9 @@ ;; Handle this case here to simplify previous expander. (define_expand "strset" - [(set (match_operand 1 "memory_operand" "") - (match_operand 2 "register_operand" "")) - (parallel [(set (match_operand 0 "register_operand" "") + [(set (match_operand 1 "memory_operand") + (match_operand 2 "register_operand")) + (parallel [(set (match_operand 0 "register_operand") (match_dup 3)) (clobber (reg:CC FLAGS_REG))])] "" @@ -15926,22 +15925,22 @@ }) (define_expand "strset_singleop" - [(parallel [(set (match_operand 1 "memory_operand" "") - (match_operand 2 "register_operand" "")) - (set (match_operand 0 "register_operand" "") - (match_operand 3 "" ""))])] + [(parallel [(set (match_operand 1 "memory_operand") + (match_operand 2 "register_operand")) + (set (match_operand 0 "register_operand") + (match_operand 3))])] "" "ix86_current_function_needs_cld = 1;") (define_insn "*strsetdi_rex_1" - [(set (mem:DI (match_operand:DI 1 "register_operand" "0")) + [(set (mem:DI (match_operand:P 1 "register_operand" "0")) (match_operand:DI 2 "register_operand" "a")) - (set (match_operand:DI 0 "register_operand" "=D") - (plus:DI (match_dup 1) - (const_int 8)))] + (set (match_operand:P 0 "register_operand" "=D") + (plus:P (match_dup 1) + (const_int 8)))] "TARGET_64BIT && !(fixed_regs[AX_REG] || fixed_regs[DI_REG])" - "stosq" + "%^stosq" [(set_attr "type" "str") (set_attr "memory" "store") (set_attr "mode" "DI")]) @@ -15953,7 +15952,7 @@ (plus:P (match_dup 1) (const_int 4)))] "!(fixed_regs[AX_REG] || fixed_regs[DI_REG])" - "stos{l|d}" + "%^stos{l|d}" [(set_attr "type" "str") (set_attr "memory" "store") (set_attr "mode" "SI")]) @@ -15965,7 +15964,7 @@ (plus:P (match_dup 1) (const_int 2)))] "!(fixed_regs[AX_REG] || fixed_regs[DI_REG])" - "stosw" + "%^stosw" [(set_attr "type" "str") (set_attr "memory" "store") (set_attr "mode" "HI")]) @@ -15977,7 +15976,7 @@ (plus:P (match_dup 1) (const_int 1)))] "!(fixed_regs[AX_REG] || fixed_regs[DI_REG])" - "stosb" + "%^stosb" [(set_attr "type" "str") (set_attr "memory" "store") (set (attr "prefix_rex") @@ -15988,28 +15987,28 @@ (set_attr "mode" "QI")]) (define_expand "rep_stos" - [(parallel [(set (match_operand 1 "register_operand" "") (const_int 0)) - (set (match_operand 0 "register_operand" "") - (match_operand 4 "" "")) - (set (match_operand 2 "memory_operand" "") (const_int 0)) - (use (match_operand 3 "register_operand" "")) + [(parallel [(set (match_operand 1 "register_operand") (const_int 0)) + (set (match_operand 0 "register_operand") + (match_operand 4)) + (set (match_operand 2 "memory_operand") (const_int 0)) + (use (match_operand 3 "register_operand")) (use (match_dup 1))])] "" "ix86_current_function_needs_cld = 1;") (define_insn "*rep_stosdi_rex64" - [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0)) - (set (match_operand:DI 0 "register_operand" "=D") - (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1") - (const_int 3)) - (match_operand:DI 3 "register_operand" "0"))) + [(set (match_operand:P 1 "register_operand" "=c") (const_int 0)) + (set (match_operand:P 0 "register_operand" "=D") + (plus:P (ashift:P (match_operand:P 4 "register_operand" "1") + (const_int 3)) + (match_operand:P 3 "register_operand" "0"))) (set (mem:BLK (match_dup 3)) (const_int 0)) (use (match_operand:DI 2 "register_operand" "a")) (use (match_dup 4))] "TARGET_64BIT && !(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])" - "rep{%;} stosq" + "%^rep{%;} stosq" [(set_attr "type" "str") (set_attr "prefix_rep" "1") (set_attr "memory" "store") @@ -16026,7 +16025,7 @@ (use (match_operand:SI 2 "register_operand" "a")) (use (match_dup 4))] "!(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])" - "rep{%;} stos{l|d}" + "%^rep{%;} stos{l|d}" [(set_attr "type" "str") (set_attr "prefix_rep" "1") (set_attr "memory" "store") @@ -16042,7 +16041,7 @@ (use (match_operand:QI 2 "register_operand" "a")) (use (match_dup 4))] "!(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])" - "rep{%;} stosb" + "%^rep{%;} stosb" [(set_attr "type" "str") (set_attr "prefix_rep" "1") (set_attr "memory" "store") @@ -16054,11 +16053,11 @@ (set_attr "mode" "QI")]) (define_expand "cmpstrnsi" - [(set (match_operand:SI 0 "register_operand" "") - (compare:SI (match_operand:BLK 1 "general_operand" "") - (match_operand:BLK 2 "general_operand" ""))) - (use (match_operand 3 "general_operand" "")) - (use (match_operand 4 "immediate_operand" ""))] + [(set (match_operand:SI 0 "register_operand") + (compare:SI (match_operand:BLK 1 "general_operand") + (match_operand:BLK 2 "general_operand"))) + (use (match_operand 3 "general_operand")) + (use (match_operand 4 "immediate_operand"))] "" { rtx addr1, addr2, out, outlow, count, countreg, align; @@ -16074,8 +16073,8 @@ if (!REG_P (out)) out = gen_reg_rtx (SImode); - addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); - addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0)); + addr1 = copy_addr_to_reg (XEXP (operands[1], 0)); + addr2 = copy_addr_to_reg (XEXP (operands[2], 0)); if (addr1 != XEXP (operands[1], 0)) operands[1] = replace_equiv_address_nv (operands[1], addr1); if (addr2 != XEXP (operands[2], 0)) @@ -16128,7 +16127,7 @@ (gtu:QI (reg:CC FLAGS_REG) (const_int 0))) (set (match_dup 2) (ltu:QI (reg:CC FLAGS_REG) (const_int 0))) - (parallel [(set (match_operand:QI 0 "register_operand" "") + (parallel [(set (match_operand:QI 0 "register_operand") (minus:QI (match_dup 1) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] @@ -16143,12 +16142,12 @@ (define_expand "cmpstrnqi_nz_1" [(parallel [(set (reg:CC FLAGS_REG) - (compare:CC (match_operand 4 "memory_operand" "") - (match_operand 5 "memory_operand" ""))) - (use (match_operand 2 "register_operand" "")) - (use (match_operand:SI 3 "immediate_operand" "")) - (clobber (match_operand 0 "register_operand" "")) - (clobber (match_operand 1 "register_operand" "")) + (compare:CC (match_operand 4 "memory_operand") + (match_operand 5 "memory_operand"))) + (use (match_operand 2 "register_operand")) + (use (match_operand:SI 3 "immediate_operand")) + (clobber (match_operand 0 "register_operand")) + (clobber (match_operand 1 "register_operand")) (clobber (match_dup 2))])] "" "ix86_current_function_needs_cld = 1;") @@ -16163,7 +16162,7 @@ (clobber (match_operand:P 1 "register_operand" "=D")) (clobber (match_operand:P 2 "register_operand" "=c"))] "!(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])" - "repz{%;} cmpsb" + "%^repz{%;} cmpsb" [(set_attr "type" "str") (set_attr "mode" "QI") (set (attr "prefix_rex") @@ -16177,15 +16176,15 @@ (define_expand "cmpstrnqi_1" [(parallel [(set (reg:CC FLAGS_REG) - (if_then_else:CC (ne (match_operand 2 "register_operand" "") + (if_then_else:CC (ne (match_operand 2 "register_operand") (const_int 0)) - (compare:CC (match_operand 4 "memory_operand" "") - (match_operand 5 "memory_operand" "")) + (compare:CC (match_operand 4 "memory_operand") + (match_operand 5 "memory_operand")) (const_int 0))) - (use (match_operand:SI 3 "immediate_operand" "")) + (use (match_operand:SI 3 "immediate_operand")) (use (reg:CC FLAGS_REG)) - (clobber (match_operand 0 "register_operand" "")) - (clobber (match_operand 1 "register_operand" "")) + (clobber (match_operand 0 "register_operand")) + (clobber (match_operand 1 "register_operand")) (clobber (match_dup 2))])] "" "ix86_current_function_needs_cld = 1;") @@ -16203,7 +16202,7 @@ (clobber (match_operand:P 1 "register_operand" "=D")) (clobber (match_operand:P 2 "register_operand" "=c"))] "!(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])" - "repz{%;} cmpsb" + "%^repz{%;} cmpsb" [(set_attr "type" "str") (set_attr "mode" "QI") (set (attr "prefix_rex") @@ -16214,10 +16213,10 @@ (set_attr "prefix_rep" "1")]) (define_expand "strlen" - [(set (match_operand:P 0 "register_operand" "") - (unspec:P [(match_operand:BLK 1 "general_operand" "") - (match_operand:QI 2 "immediate_operand" "") - (match_operand 3 "immediate_operand" "")] + [(set (match_operand:P 0 "register_operand") + (unspec:P [(match_operand:BLK 1 "general_operand") + (match_operand:QI 2 "immediate_operand") + (match_operand 3 "immediate_operand")] UNSPEC_SCAS))] "" { @@ -16228,9 +16227,9 @@ }) (define_expand "strlenqi_1" - [(parallel [(set (match_operand 0 "register_operand" "") - (match_operand 2 "" "")) - (clobber (match_operand 1 "register_operand" "")) + [(parallel [(set (match_operand 0 "register_operand") + (match_operand 2)) + (clobber (match_operand 1 "register_operand")) (clobber (reg:CC FLAGS_REG))])] "" "ix86_current_function_needs_cld = 1;") @@ -16244,7 +16243,7 @@ (clobber (match_operand:P 1 "register_operand" "=D")) (clobber (reg:CC FLAGS_REG))] "!(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])" - "repnz{%;} scasb" + "%^repnz{%;} scasb" [(set_attr "type" "str") (set_attr "mode" "QI") (set (attr "prefix_rex") @@ -16271,16 +16270,16 @@ (define_peephole2 [(parallel[ (set (reg:CC FLAGS_REG) - (compare:CC (mem:BLK (match_operand 4 "register_operand" "")) - (mem:BLK (match_operand 5 "register_operand" "")))) - (use (match_operand 6 "register_operand" "")) - (use (match_operand:SI 3 "immediate_operand" "")) - (clobber (match_operand 0 "register_operand" "")) - (clobber (match_operand 1 "register_operand" "")) - (clobber (match_operand 2 "register_operand" ""))]) - (set (match_operand:QI 7 "register_operand" "") + (compare:CC (mem:BLK (match_operand 4 "register_operand")) + (mem:BLK (match_operand 5 "register_operand")))) + (use (match_operand 6 "register_operand")) + (use (match_operand:SI 3 "immediate_operand")) + (clobber (match_operand 0 "register_operand")) + (clobber (match_operand 1 "register_operand")) + (clobber (match_operand 2 "register_operand"))]) + (set (match_operand:QI 7 "register_operand") (gtu:QI (reg:CC FLAGS_REG) (const_int 0))) - (set (match_operand:QI 8 "register_operand" "") + (set (match_operand:QI 8 "register_operand") (ltu:QI (reg:CC FLAGS_REG) (const_int 0))) (set (reg FLAGS_REG) (compare (match_dup 7) (match_dup 8))) @@ -16300,19 +16299,19 @@ (define_peephole2 [(parallel[ (set (reg:CC FLAGS_REG) - (if_then_else:CC (ne (match_operand 6 "register_operand" "") + (if_then_else:CC (ne (match_operand 6 "register_operand") (const_int 0)) - (compare:CC (mem:BLK (match_operand 4 "register_operand" "")) - (mem:BLK (match_operand 5 "register_operand" ""))) + (compare:CC (mem:BLK (match_operand 4 "register_operand")) + (mem:BLK (match_operand 5 "register_operand"))) (const_int 0))) - (use (match_operand:SI 3 "immediate_operand" "")) + (use (match_operand:SI 3 "immediate_operand")) (use (reg:CC FLAGS_REG)) - (clobber (match_operand 0 "register_operand" "")) - (clobber (match_operand 1 "register_operand" "")) - (clobber (match_operand 2 "register_operand" ""))]) - (set (match_operand:QI 7 "register_operand" "") + (clobber (match_operand 0 "register_operand")) + (clobber (match_operand 1 "register_operand")) + (clobber (match_operand 2 "register_operand"))]) + (set (match_operand:QI 7 "register_operand") (gtu:QI (reg:CC FLAGS_REG) (const_int 0))) - (set (match_operand:QI 8 "register_operand" "") + (set (match_operand:QI 8 "register_operand") (ltu:QI (reg:CC FLAGS_REG) (const_int 0))) (set (reg FLAGS_REG) (compare (match_dup 7) (match_dup 8))) @@ -16334,10 +16333,10 @@ ;; Conditional move instructions. (define_expand "movcc" - [(set (match_operand:SWIM 0 "register_operand" "") - (if_then_else:SWIM (match_operand 1 "ordered_comparison_operator" "") - (match_operand:SWIM 2 "" "") - (match_operand:SWIM 3 "" "")))] + [(set (match_operand:SWIM 0 "register_operand") + (if_then_else:SWIM (match_operand 1 "ordered_comparison_operator") + (match_operand:SWIM 2 "") + (match_operand:SWIM 3 "")))] "" "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;") @@ -16347,10 +16346,10 @@ (define_expand "x86_movcc_0_m1" [(parallel - [(set (match_operand:SWI48 0 "register_operand" "") + [(set (match_operand:SWI48 0 "register_operand") (if_then_else:SWI48 (match_operator:SWI48 2 "ix86_carry_flag_operator" - [(match_operand 1 "flags_reg_operand" "") + [(match_operand 1 "flags_reg_operand") (const_int 0)]) (const_int -1) (const_int 0))) @@ -16422,7 +16421,7 @@ (define_insn_and_split "*movqicc_noc" [(set (match_operand:QI 0 "register_operand" "=r,r") (if_then_else:QI (match_operator 1 "ix86_comparison_operator" - [(match_operand 4 "flags_reg_operand" "") + [(match_operand 4 "flags_reg_operand") (const_int 0)]) (match_operand:QI 2 "register_operand" "r,0") (match_operand:QI 3 "register_operand" "0,r")))] @@ -16440,11 +16439,11 @@ (set_attr "mode" "SI")]) (define_expand "movcc" - [(set (match_operand:X87MODEF 0 "register_operand" "") + [(set (match_operand:X87MODEF 0 "register_operand") (if_then_else:X87MODEF - (match_operand 1 "ix86_fp_comparison_operator" "") - (match_operand:X87MODEF 2 "register_operand" "") - (match_operand:X87MODEF 3 "register_operand" "")))] + (match_operand 1 "ix86_fp_comparison_operator") + (match_operand:X87MODEF 2 "register_operand") + (match_operand:X87MODEF 3 "register_operand")))] "(TARGET_80387 && TARGET_CMOVE) || (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)" "if (ix86_expand_fp_movcc (operands)) DONE; else FAIL;") @@ -16495,12 +16494,12 @@ (set_attr "mode" "DF,DF,DI,DI")]) (define_split - [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand" "") + [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand") (if_then_else:DF (match_operator 1 "fcmov_comparison_operator" - [(match_operand 4 "flags_reg_operand" "") + [(match_operand 4 "flags_reg_operand") (const_int 0)]) - (match_operand:DF 2 "nonimmediate_operand" "") - (match_operand:DF 3 "nonimmediate_operand" "")))] + (match_operand:DF 2 "nonimmediate_operand") + (match_operand:DF 3 "nonimmediate_operand")))] "!TARGET_64BIT && reload_completed" [(set (match_dup 2) (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)]) @@ -16607,33 +16606,37 @@ ;; ;; Actually we only match the last two instructions for simplicity. (define_peephole2 - [(set (match_operand 0 "fp_register_operand" "") - (match_operand 1 "fp_register_operand" "")) + [(set (match_operand 0 "fp_register_operand") + (match_operand 1 "fp_register_operand")) (set (match_dup 0) (match_operator 2 "binary_fp_operator" [(match_dup 0) - (match_operand 3 "memory_operand" "")]))] + (match_operand 3 "memory_operand")]))] "REGNO (operands[0]) != REGNO (operands[1])" [(set (match_dup 0) (match_dup 3)) (set (match_dup 0) (match_dup 4))] ;; The % modifier is not operational anymore in peephole2's, so we have to ;; swap the operands manually in the case of addition and multiplication. - "if (COMMUTATIVE_ARITH_P (operands[2])) - operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]), - GET_MODE (operands[2]), - operands[0], operands[1]); - else - operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]), - GET_MODE (operands[2]), - operands[1], operands[0]);") +{ + rtx op0, op1; + + if (COMMUTATIVE_ARITH_P (operands[2])) + op0 = operands[0], op1 = operands[1]; + else + op0 = operands[1], op1 = operands[0]; + + operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]), + GET_MODE (operands[2]), + op0, op1); +}) ;; Conditional addition patterns (define_expand "addcc" - [(match_operand:SWI 0 "register_operand" "") - (match_operand 1 "ordered_comparison_operator" "") - (match_operand:SWI 2 "register_operand" "") - (match_operand:SWI 3 "const_int_operand" "")] + [(match_operand:SWI 0 "register_operand") + (match_operand 1 "ordered_comparison_operator") + (match_operand:SWI 2 "register_operand") + (match_operand:SWI 3 "const_int_operand")] "" "if (ix86_expand_int_addcc (operands)) DONE; else FAIL;") @@ -16671,14 +16674,14 @@ default: operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0)); - return "lea{}\t{%a2, %0|%0, %a2}"; + return "lea{}\t{%E2, %0|%0, %E2}"; } } [(set (attr "type") (cond [(and (eq_attr "alternative" "0") (not (match_test "TARGET_OPT_AGU"))) (const_string "alu") - (match_operand: 2 "const0_operand" "") + (match_operand: 2 "const0_operand") (const_string "imov") ] (const_string "lea"))) @@ -16686,7 +16689,7 @@ (cond [(eq_attr "type" "imov") (const_string "0") (and (eq_attr "type" "alu") - (match_operand 2 "const128_operand" "")) + (match_operand 2 "const128_operand")) (const_string "1") ] (const_string "*"))) @@ -16714,8 +16717,8 @@ (set_attr "length" "5")]) (define_expand "allocate_stack" - [(match_operand 0 "register_operand" "") - (match_operand 1 "general_operand" "")] + [(match_operand 0 "register_operand") + (match_operand 1 "general_operand")] "ix86_target_stack_probe ()" { rtx x; @@ -16734,7 +16737,7 @@ } else { - x = copy_to_mode_reg (Pmode, operands[1]); + x = copy_addr_to_reg (operands[1]); if (TARGET_64BIT) emit_insn (gen_allocate_stack_worker_probe_di (x, x)); else @@ -16751,7 +16754,7 @@ ;; Use IOR for stack probes, this is shorter. (define_expand "probe_stack" - [(match_operand 0 "memory_operand" "")] + [(match_operand 0 "memory_operand")] "" { rtx (*gen_ior3) (rtx, rtx, rtx); @@ -16786,7 +16789,7 @@ [(set_attr "type" "multi")]) (define_expand "builtin_setjmp_receiver" - [(label_ref (match_operand 0 "" ""))] + [(label_ref (match_operand 0))] "!TARGET_64BIT && flag_pic" { #if TARGET_MACHO @@ -16809,10 +16812,10 @@ ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode. (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "register_operand") (match_operator 3 "promotable_binary_operator" - [(match_operand 1 "register_operand" "") - (match_operand 2 "aligned_operand" "")])) + [(match_operand 1 "register_operand") + (match_operand 2 "aligned_operand")])) (clobber (reg:CC FLAGS_REG))] "! TARGET_PARTIAL_REG_STALL && reload_completed && ((GET_MODE (operands[0]) == HImode @@ -16825,23 +16828,25 @@ [(parallel [(set (match_dup 0) (match_op_dup 3 [(match_dup 1) (match_dup 2)])) (clobber (reg:CC FLAGS_REG))])] - "operands[0] = gen_lowpart (SImode, operands[0]); - operands[1] = gen_lowpart (SImode, operands[1]); - if (GET_CODE (operands[3]) != ASHIFT) - operands[2] = gen_lowpart (SImode, operands[2]); - PUT_MODE (operands[3], SImode);") +{ + operands[0] = gen_lowpart (SImode, operands[0]); + operands[1] = gen_lowpart (SImode, operands[1]); + if (GET_CODE (operands[3]) != ASHIFT) + operands[2] = gen_lowpart (SImode, operands[2]); + PUT_MODE (operands[3], SImode); +}) ; Promote the QImode tests, as i386 has encoding of the AND ; instruction with 32-bit sign-extended immediate and thus the ; instruction size is unchanged, except in the %eax case for ; which it is increased by one byte, hence the ! optimize_size. (define_split - [(set (match_operand 0 "flags_reg_operand" "") + [(set (match_operand 0 "flags_reg_operand") (match_operator 2 "compare_operator" - [(and (match_operand 3 "aligned_operand" "") - (match_operand 4 "const_int_operand" "")) + [(and (match_operand 3 "aligned_operand") + (match_operand 4 "const_int_operand")) (const_int 0)])) - (set (match_operand 1 "register_operand" "") + (set (match_operand 1 "register_operand") (and (match_dup 3) (match_dup 4)))] "! TARGET_PARTIAL_REG_STALL && reload_completed && optimize_insn_for_speed_p () @@ -16867,10 +16872,10 @@ ; the instruction size would at least double, which is not what we ; want even with ! optimize_size. (define_split - [(set (match_operand 0 "flags_reg_operand" "") + [(set (match_operand 0 "flags_reg_operand") (match_operator 1 "compare_operator" - [(and (match_operand:HI 2 "aligned_operand" "") - (match_operand:HI 3 "const_int_operand" "")) + [(and (match_operand:HI 2 "aligned_operand") + (match_operand:HI 3 "const_int_operand")) (const_int 0)]))] "! TARGET_PARTIAL_REG_STALL && reload_completed && ! TARGET_FAST_PREFIX @@ -16888,8 +16893,8 @@ }) (define_split - [(set (match_operand 0 "register_operand" "") - (neg (match_operand 1 "register_operand" ""))) + [(set (match_operand 0 "register_operand") + (neg (match_operand 1 "register_operand"))) (clobber (reg:CC FLAGS_REG))] "! TARGET_PARTIAL_REG_STALL && reload_completed && (GET_MODE (operands[0]) == HImode @@ -16899,12 +16904,14 @@ [(parallel [(set (match_dup 0) (neg:SI (match_dup 1))) (clobber (reg:CC FLAGS_REG))])] - "operands[0] = gen_lowpart (SImode, operands[0]); - operands[1] = gen_lowpart (SImode, operands[1]);") +{ + operands[0] = gen_lowpart (SImode, operands[0]); + operands[1] = gen_lowpart (SImode, operands[1]); +}) (define_split - [(set (match_operand 0 "register_operand" "") - (not (match_operand 1 "register_operand" "")))] + [(set (match_operand 0 "register_operand") + (not (match_operand 1 "register_operand")))] "! TARGET_PARTIAL_REG_STALL && reload_completed && (GET_MODE (operands[0]) == HImode || (GET_MODE (operands[0]) == QImode @@ -16912,15 +16919,17 @@ || optimize_insn_for_size_p ())))" [(set (match_dup 0) (not:SI (match_dup 1)))] - "operands[0] = gen_lowpart (SImode, operands[0]); - operands[1] = gen_lowpart (SImode, operands[1]);") +{ + operands[0] = gen_lowpart (SImode, operands[0]); + operands[1] = gen_lowpart (SImode, operands[1]); +}) (define_split - [(set (match_operand 0 "register_operand" "") + [(set (match_operand 0 "register_operand") (if_then_else (match_operator 1 "ordered_comparison_operator" [(reg FLAGS_REG) (const_int 0)]) - (match_operand 2 "register_operand" "") - (match_operand 3 "register_operand" "")))] + (match_operand 2 "register_operand") + (match_operand 3 "register_operand")))] "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE && (GET_MODE (operands[0]) == HImode || (GET_MODE (operands[0]) == QImode @@ -16928,17 +16937,19 @@ || optimize_insn_for_size_p ())))" [(set (match_dup 0) (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))] - "operands[0] = gen_lowpart (SImode, operands[0]); - operands[2] = gen_lowpart (SImode, operands[2]); - operands[3] = gen_lowpart (SImode, operands[3]);") +{ + operands[0] = gen_lowpart (SImode, operands[0]); + operands[2] = gen_lowpart (SImode, operands[2]); + operands[3] = gen_lowpart (SImode, operands[3]); +}) ;; RTL Peephole optimizations, run before sched2. These primarily look to ;; transform a complex memory operation into two memory to register operations. ;; Don't push memory operands (define_peephole2 - [(set (match_operand:SWI 0 "push_operand" "") - (match_operand:SWI 1 "memory_operand" "")) + [(set (match_operand:SWI 0 "push_operand") + (match_operand:SWI 1 "memory_operand")) (match_scratch:SWI 2 "")] "!(TARGET_PUSH_MEMORY || optimize_insn_for_size_p ()) && !RTX_FRAME_RELATED_P (peep2_next_insn (0))" @@ -16948,8 +16959,8 @@ ;; We need to handle SFmode only, because DFmode and XFmode are split to ;; SImode pushes. (define_peephole2 - [(set (match_operand:SF 0 "push_operand" "") - (match_operand:SF 1 "memory_operand" "")) + [(set (match_operand:SF 0 "push_operand") + (match_operand:SF 1 "memory_operand")) (match_scratch:SF 2 "r")] "!(TARGET_PUSH_MEMORY || optimize_insn_for_size_p ()) && !RTX_FRAME_RELATED_P (peep2_next_insn (0))" @@ -16960,7 +16971,7 @@ ;; gets too big. (define_peephole2 [(match_scratch:SWI124 1 "") - (set (match_operand:SWI124 0 "memory_operand" "") + (set (match_operand:SWI124 0 "memory_operand") (const_int 0))] "optimize_insn_for_speed_p () && !TARGET_USE_MOV0 @@ -16974,8 +16985,8 @@ (define_peephole2 [(match_scratch:SWI124 2 "") - (set (match_operand:SWI124 0 "memory_operand" "") - (match_operand:SWI124 1 "immediate_operand" ""))] + (set (match_operand:SWI124 0 "memory_operand") + (match_operand:SWI124 1 "immediate_operand"))] "optimize_insn_for_speed_p () && TARGET_SPLIT_LONG_MOVES && get_attr_length (insn) >= ix86_cur_cost ()->large_insn" @@ -16984,9 +16995,9 @@ ;; Don't compare memory with zero, load and use a test instead. (define_peephole2 - [(set (match_operand 0 "flags_reg_operand" "") + [(set (match_operand 0 "flags_reg_operand") (match_operator 1 "compare_operator" - [(match_operand:SI 2 "memory_operand" "") + [(match_operand:SI 2 "memory_operand") (const_int 0)])) (match_scratch:SI 3 "r")] "optimize_insn_for_speed_p () && ix86_match_ccmode (insn, CCNOmode)" @@ -17005,8 +17016,8 @@ ;; lifetime information then. (define_peephole2 - [(set (match_operand:SWI124 0 "nonimmediate_operand" "") - (not:SWI124 (match_operand:SWI124 1 "nonimmediate_operand" "")))] + [(set (match_operand:SWI124 0 "nonimmediate_operand") + (not:SWI124 (match_operand:SWI124 1 "nonimmediate_operand")))] "optimize_insn_for_speed_p () && ((TARGET_NOT_UNPAIRABLE && (!MEM_P (operands[0]) @@ -17026,10 +17037,10 @@ ;; versions if we're concerned about partial register stalls. (define_peephole2 - [(set (match_operand 0 "flags_reg_operand" "") + [(set (match_operand 0 "flags_reg_operand") (match_operator 1 "compare_operator" - [(and:SI (match_operand:SI 2 "register_operand" "") - (match_operand:SI 3 "immediate_operand" "")) + [(and:SI (match_operand:SI 2 "register_operand") + (match_operand:SI 3 "immediate_operand")) (const_int 0)]))] "ix86_match_ccmode (insn, CCNOmode) && (true_regnum (operands[2]) != AX_REG @@ -17046,10 +17057,10 @@ ;; on ! TARGET_PARTIAL_REG_STALL (define_peephole2 - [(set (match_operand 0 "flags_reg_operand" "") + [(set (match_operand 0 "flags_reg_operand") (match_operator 1 "compare_operator" - [(and:QI (match_operand:QI 2 "register_operand" "") - (match_operand:QI 3 "immediate_operand" "")) + [(and:QI (match_operand:QI 2 "register_operand") + (match_operand:QI 3 "immediate_operand")) (const_int 0)]))] "! TARGET_PARTIAL_REG_STALL && ix86_match_ccmode (insn, CCNOmode) @@ -17063,14 +17074,14 @@ (and:QI (match_dup 2) (match_dup 3)))])]) (define_peephole2 - [(set (match_operand 0 "flags_reg_operand" "") + [(set (match_operand 0 "flags_reg_operand") (match_operator 1 "compare_operator" [(and:SI (zero_extract:SI - (match_operand 2 "ext_register_operand" "") + (match_operand 2 "ext_register_operand") (const_int 8) (const_int 8)) - (match_operand 3 "const_int_operand" "")) + (match_operand 3 "const_int_operand")) (const_int 0)]))] "! TARGET_PARTIAL_REG_STALL && ix86_match_ccmode (insn, CCNOmode) @@ -17098,10 +17109,10 @@ ;; Don't do logical operations with memory inputs. (define_peephole2 [(match_scratch:SI 2 "r") - (parallel [(set (match_operand:SI 0 "register_operand" "") + (parallel [(set (match_operand:SI 0 "register_operand") (match_operator:SI 3 "arith_or_logical_operator" [(match_dup 0) - (match_operand:SI 1 "memory_operand" "")])) + (match_operand:SI 1 "memory_operand")])) (clobber (reg:CC FLAGS_REG))])] "!(TARGET_READ_MODIFY || optimize_insn_for_size_p ())" [(set (match_dup 2) (match_dup 1)) @@ -17111,9 +17122,9 @@ (define_peephole2 [(match_scratch:SI 2 "r") - (parallel [(set (match_operand:SI 0 "register_operand" "") + (parallel [(set (match_operand:SI 0 "register_operand") (match_operator:SI 3 "arith_or_logical_operator" - [(match_operand:SI 1 "memory_operand" "") + [(match_operand:SI 1 "memory_operand") (match_dup 0)])) (clobber (reg:CC FLAGS_REG))])] "!(TARGET_READ_MODIFY || optimize_insn_for_size_p ())" @@ -17126,12 +17137,12 @@ ;; refers to the destination of the load! (define_peephole2 - [(set (match_operand:SI 0 "register_operand" "") - (match_operand:SI 1 "register_operand" "")) + [(set (match_operand:SI 0 "register_operand") + (match_operand:SI 1 "register_operand")) (parallel [(set (match_dup 0) (match_operator:SI 3 "commutative_operator" [(match_dup 0) - (match_operand:SI 2 "memory_operand" "")])) + (match_operand:SI 2 "memory_operand")])) (clobber (reg:CC FLAGS_REG))])] "REGNO (operands[0]) != REGNO (operands[1]) && GENERAL_REGNO_P (REGNO (operands[0])) @@ -17143,12 +17154,12 @@ "operands[4] = replace_rtx (operands[2], operands[0], operands[1]);") (define_peephole2 - [(set (match_operand 0 "register_operand" "") - (match_operand 1 "register_operand" "")) + [(set (match_operand 0 "register_operand") + (match_operand 1 "register_operand")) (set (match_dup 0) (match_operator 3 "commutative_operator" [(match_dup 0) - (match_operand 2 "memory_operand" "")]))] + (match_operand 2 "memory_operand")]))] "REGNO (operands[0]) != REGNO (operands[1]) && ((MMX_REG_P (operands[0]) && MMX_REG_P (operands[1])) || (SSE_REG_P (operands[0]) && SSE_REG_P (operands[1])))" @@ -17164,10 +17175,10 @@ (define_peephole2 [(match_scratch:SI 2 "r") - (parallel [(set (match_operand:SI 0 "memory_operand" "") + (parallel [(set (match_operand:SI 0 "memory_operand") (match_operator:SI 3 "arith_or_logical_operator" [(match_dup 0) - (match_operand:SI 1 "nonmemory_operand" "")])) + (match_operand:SI 1 "nonmemory_operand")])) (clobber (reg:CC FLAGS_REG))])] "!(TARGET_READ_MODIFY_WRITE || optimize_insn_for_size_p ()) /* Do not split stack checking probes. */ @@ -17180,9 +17191,9 @@ (define_peephole2 [(match_scratch:SI 2 "r") - (parallel [(set (match_operand:SI 0 "memory_operand" "") + (parallel [(set (match_operand:SI 0 "memory_operand") (match_operator:SI 3 "arith_or_logical_operator" - [(match_operand:SI 1 "nonmemory_operand" "") + [(match_operand:SI 1 "nonmemory_operand") (match_dup 0)])) (clobber (reg:CC FLAGS_REG))])] "!(TARGET_READ_MODIFY_WRITE || optimize_insn_for_size_p ()) @@ -17197,12 +17208,12 @@ ;; Attempt to use arith or logical operations with memory outputs with ;; setting of flags. (define_peephole2 - [(set (match_operand:SWI 0 "register_operand" "") - (match_operand:SWI 1 "memory_operand" "")) + [(set (match_operand:SWI 0 "register_operand") + (match_operand:SWI 1 "memory_operand")) (parallel [(set (match_dup 0) (match_operator:SWI 3 "plusminuslogic_operator" [(match_dup 0) - (match_operand:SWI 2 "" "")])) + (match_operand:SWI 2 "")])) (clobber (reg:CC FLAGS_REG))]) (set (match_dup 1) (match_dup 0)) (set (reg FLAGS_REG) (compare (match_dup 0) (const_int 0)))] @@ -17216,18 +17227,20 @@ [(parallel [(set (match_dup 4) (match_dup 5)) (set (match_dup 1) (match_op_dup 3 [(match_dup 1) (match_dup 2)]))])] - "operands[4] = SET_DEST (PATTERN (peep2_next_insn (3))); - operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), mode, - copy_rtx (operands[1]), - copy_rtx (operands[2])); - operands[5] = gen_rtx_COMPARE (GET_MODE (operands[4]), - operands[5], const0_rtx);") +{ + operands[4] = SET_DEST (PATTERN (peep2_next_insn (3))); + operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), mode, + copy_rtx (operands[1]), + copy_rtx (operands[2])); + operands[5] = gen_rtx_COMPARE (GET_MODE (operands[4]), + operands[5], const0_rtx); +}) (define_peephole2 - [(parallel [(set (match_operand:SWI 0 "register_operand" "") + [(parallel [(set (match_operand:SWI 0 "register_operand") (match_operator:SWI 2 "plusminuslogic_operator" [(match_dup 0) - (match_operand:SWI 1 "memory_operand" "")])) + (match_operand:SWI 1 "memory_operand")])) (clobber (reg:CC FLAGS_REG))]) (set (match_dup 1) (match_dup 0)) (set (reg FLAGS_REG) (compare (match_dup 0) (const_int 0)))] @@ -17241,20 +17254,22 @@ [(parallel [(set (match_dup 3) (match_dup 4)) (set (match_dup 1) (match_op_dup 2 [(match_dup 1) (match_dup 0)]))])] - "operands[3] = SET_DEST (PATTERN (peep2_next_insn (2))); - operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]), mode, - copy_rtx (operands[1]), - copy_rtx (operands[0])); - operands[4] = gen_rtx_COMPARE (GET_MODE (operands[3]), - operands[4], const0_rtx);") +{ + operands[3] = SET_DEST (PATTERN (peep2_next_insn (2))); + operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]), mode, + copy_rtx (operands[1]), + copy_rtx (operands[0])); + operands[4] = gen_rtx_COMPARE (GET_MODE (operands[3]), + operands[4], const0_rtx); +}) (define_peephole2 - [(set (match_operand:SWI12 0 "register_operand" "") - (match_operand:SWI12 1 "memory_operand" "")) - (parallel [(set (match_operand:SI 4 "register_operand" "") + [(set (match_operand:SWI12 0 "register_operand") + (match_operand:SWI12 1 "memory_operand")) + (parallel [(set (match_operand:SI 4 "register_operand") (match_operator:SI 3 "plusminuslogic_operator" [(match_dup 4) - (match_operand:SI 2 "nonmemory_operand" "")])) + (match_operand:SI 2 "nonmemory_operand")])) (clobber (reg:CC FLAGS_REG))]) (set (match_dup 1) (match_dup 0)) (set (reg FLAGS_REG) (compare (match_dup 0) (const_int 0)))] @@ -17262,6 +17277,9 @@ && REG_P (operands[0]) && REG_P (operands[4]) && REGNO (operands[0]) == REGNO (operands[4]) && peep2_reg_dead_p (4, operands[0]) + && (mode != QImode + || immediate_operand (operands[2], SImode) + || q_regs_operand (operands[2], SImode)) && !reg_overlap_mentioned_p (operands[0], operands[1]) && ix86_match_ccmode (peep2_next_insn (3), (GET_CODE (operands[3]) == PLUS @@ -17269,20 +17287,22 @@ ? CCGOCmode : CCNOmode)" [(parallel [(set (match_dup 4) (match_dup 5)) (set (match_dup 1) (match_dup 6))])] - "operands[2] = gen_lowpart (mode, operands[2]); - operands[4] = SET_DEST (PATTERN (peep2_next_insn (3))); - operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), mode, - copy_rtx (operands[1]), operands[2]); - operands[5] = gen_rtx_COMPARE (GET_MODE (operands[4]), - operands[5], const0_rtx); - operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), mode, - copy_rtx (operands[1]), - copy_rtx (operands[2]));") +{ + operands[2] = gen_lowpart (mode, operands[2]); + operands[4] = SET_DEST (PATTERN (peep2_next_insn (3))); + operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), mode, + copy_rtx (operands[1]), operands[2]); + operands[5] = gen_rtx_COMPARE (GET_MODE (operands[4]), + operands[5], const0_rtx); + operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), mode, + copy_rtx (operands[1]), + copy_rtx (operands[2])); +}) ;; Attempt to always use XOR for zeroing registers. (define_peephole2 - [(set (match_operand 0 "register_operand" "") - (match_operand 1 "const0_operand" ""))] + [(set (match_operand 0 "register_operand") + (match_operand 1 "const0_operand"))] "GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD && (! TARGET_USE_MOV0 || optimize_insn_for_size_p ()) && GENERAL_REG_P (operands[0]) @@ -17292,7 +17312,7 @@ "operands[0] = gen_lowpart (word_mode, operands[0]);") (define_peephole2 - [(set (strict_low_part (match_operand 0 "register_operand" "")) + [(set (strict_low_part (match_operand 0 "register_operand")) (const_int 0))] "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode) @@ -17303,7 +17323,7 @@ ;; For HI, SI and DI modes, or $-1,reg is smaller than mov $-1,reg. (define_peephole2 - [(set (match_operand:SWI248 0 "register_operand" "") + [(set (match_operand:SWI248 0 "register_operand") (const_int -1))] "(optimize_insn_for_size_p () || TARGET_MOVE_M1_VIA_OR) && peep2_regno_dead_p (0, FLAGS_REG)" @@ -17318,17 +17338,17 @@ ;; These can be created by move expanders. (define_peephole2 - [(set (match_operand:SWI48 0 "register_operand" "") + [(set (match_operand:SWI48 0 "register_operand") (plus:SWI48 (match_dup 0) - (match_operand:SWI48 1 "" "")))] + (match_operand:SWI48 1 "")))] "peep2_regno_dead_p (0, FLAGS_REG)" [(parallel [(set (match_dup 0) (plus:SWI48 (match_dup 0) (match_dup 1))) (clobber (reg:CC FLAGS_REG))])]) (define_peephole2 - [(set (match_operand:SI 0 "register_operand" "") - (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "") - (match_operand:DI 2 "nonmemory_operand" "")) 0))] + [(set (match_operand:SI 0 "register_operand") + (subreg:SI (plus:DI (match_operand:DI 1 "register_operand") + (match_operand:DI 2 "nonmemory_operand")) 0))] "TARGET_64BIT && peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])" @@ -17337,9 +17357,9 @@ "operands[2] = gen_lowpart (SImode, operands[2]);") (define_peephole2 - [(set (match_operand:SWI48 0 "register_operand" "") + [(set (match_operand:SWI48 0 "register_operand") (mult:SWI48 (match_dup 0) - (match_operand:SWI48 1 "const_int_operand" "")))] + (match_operand:SWI48 1 "const_int_operand")))] "exact_log2 (INTVAL (operands[1])) >= 0 && peep2_regno_dead_p (0, FLAGS_REG)" [(parallel [(set (match_dup 0) (ashift:SWI48 (match_dup 0) (match_dup 2))) @@ -17347,9 +17367,9 @@ "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));") (define_peephole2 - [(set (match_operand:SI 0 "register_operand" "") - (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "") - (match_operand:DI 2 "const_int_operand" "")) 0))] + [(set (match_operand:SI 0 "register_operand") + (subreg:SI (mult:DI (match_operand:DI 1 "register_operand") + (match_operand:DI 2 "const_int_operand")) 0))] "TARGET_64BIT && exact_log2 (INTVAL (operands[2])) >= 0 && REGNO (operands[0]) == REGNO (operands[1]) @@ -17379,139 +17399,139 @@ ;; alternative when no register is available later. (define_peephole2 - [(match_scratch:P 1 "r") + [(match_scratch:W 1 "r") (parallel [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) - (match_operand:P 0 "const_int_operand" ""))) + (match_operand:P 0 "const_int_operand"))) (clobber (reg:CC FLAGS_REG)) (clobber (mem:BLK (scratch)))])] "(TARGET_SINGLE_PUSH || optimize_insn_for_size_p ()) - && INTVAL (operands[0]) == -GET_MODE_SIZE (Pmode)" + && INTVAL (operands[0]) == -GET_MODE_SIZE (word_mode)" [(clobber (match_dup 1)) - (parallel [(set (mem:P (pre_dec:P (reg:P SP_REG))) (match_dup 1)) + (parallel [(set (mem:W (pre_dec:P (reg:P SP_REG))) (match_dup 1)) (clobber (mem:BLK (scratch)))])]) (define_peephole2 - [(match_scratch:P 1 "r") + [(match_scratch:W 1 "r") (parallel [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) - (match_operand:P 0 "const_int_operand" ""))) + (match_operand:P 0 "const_int_operand"))) (clobber (reg:CC FLAGS_REG)) (clobber (mem:BLK (scratch)))])] "(TARGET_DOUBLE_PUSH || optimize_insn_for_size_p ()) - && INTVAL (operands[0]) == -2*GET_MODE_SIZE (Pmode)" + && INTVAL (operands[0]) == -2*GET_MODE_SIZE (word_mode)" [(clobber (match_dup 1)) - (set (mem:P (pre_dec:P (reg:P SP_REG))) (match_dup 1)) - (parallel [(set (mem:P (pre_dec:P (reg:P SP_REG))) (match_dup 1)) + (set (mem:W (pre_dec:P (reg:P SP_REG))) (match_dup 1)) + (parallel [(set (mem:W (pre_dec:P (reg:P SP_REG))) (match_dup 1)) (clobber (mem:BLK (scratch)))])]) ;; Convert esp subtractions to push. (define_peephole2 - [(match_scratch:P 1 "r") + [(match_scratch:W 1 "r") (parallel [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) - (match_operand:P 0 "const_int_operand" ""))) + (match_operand:P 0 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))])] "(TARGET_SINGLE_PUSH || optimize_insn_for_size_p ()) - && INTVAL (operands[0]) == -GET_MODE_SIZE (Pmode)" + && INTVAL (operands[0]) == -GET_MODE_SIZE (word_mode)" [(clobber (match_dup 1)) - (set (mem:P (pre_dec:P (reg:P SP_REG))) (match_dup 1))]) + (set (mem:W (pre_dec:P (reg:P SP_REG))) (match_dup 1))]) (define_peephole2 - [(match_scratch:P 1 "r") + [(match_scratch:W 1 "r") (parallel [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) - (match_operand:P 0 "const_int_operand" ""))) + (match_operand:P 0 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))])] "(TARGET_DOUBLE_PUSH || optimize_insn_for_size_p ()) - && INTVAL (operands[0]) == -2*GET_MODE_SIZE (Pmode)" + && INTVAL (operands[0]) == -2*GET_MODE_SIZE (word_mode)" [(clobber (match_dup 1)) - (set (mem:P (pre_dec:P (reg:P SP_REG))) (match_dup 1)) - (set (mem:P (pre_dec:P (reg:P SP_REG))) (match_dup 1))]) + (set (mem:W (pre_dec:P (reg:P SP_REG))) (match_dup 1)) + (set (mem:W (pre_dec:P (reg:P SP_REG))) (match_dup 1))]) ;; Convert epilogue deallocator to pop. (define_peephole2 - [(match_scratch:P 1 "r") + [(match_scratch:W 1 "r") (parallel [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) - (match_operand:P 0 "const_int_operand" ""))) + (match_operand:P 0 "const_int_operand"))) (clobber (reg:CC FLAGS_REG)) (clobber (mem:BLK (scratch)))])] "(TARGET_SINGLE_POP || optimize_insn_for_size_p ()) - && INTVAL (operands[0]) == GET_MODE_SIZE (Pmode)" - [(parallel [(set (match_dup 1) (mem:P (post_inc:P (reg:P SP_REG)))) + && INTVAL (operands[0]) == GET_MODE_SIZE (word_mode)" + [(parallel [(set (match_dup 1) (mem:W (post_inc:P (reg:P SP_REG)))) (clobber (mem:BLK (scratch)))])]) ;; Two pops case is tricky, since pop causes dependency ;; on destination register. We use two registers if available. (define_peephole2 - [(match_scratch:P 1 "r") - (match_scratch:P 2 "r") + [(match_scratch:W 1 "r") + (match_scratch:W 2 "r") (parallel [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) - (match_operand:P 0 "const_int_operand" ""))) + (match_operand:P 0 "const_int_operand"))) (clobber (reg:CC FLAGS_REG)) (clobber (mem:BLK (scratch)))])] "(TARGET_DOUBLE_POP || optimize_insn_for_size_p ()) - && INTVAL (operands[0]) == 2*GET_MODE_SIZE (Pmode)" - [(parallel [(set (match_dup 1) (mem:P (post_inc:P (reg:P SP_REG)))) + && INTVAL (operands[0]) == 2*GET_MODE_SIZE (word_mode)" + [(parallel [(set (match_dup 1) (mem:W (post_inc:P (reg:P SP_REG)))) (clobber (mem:BLK (scratch)))]) - (set (match_dup 2) (mem:P (post_inc:P (reg:P SP_REG))))]) + (set (match_dup 2) (mem:W (post_inc:P (reg:P SP_REG))))]) (define_peephole2 - [(match_scratch:P 1 "r") + [(match_scratch:W 1 "r") (parallel [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) - (match_operand:P 0 "const_int_operand" ""))) + (match_operand:P 0 "const_int_operand"))) (clobber (reg:CC FLAGS_REG)) (clobber (mem:BLK (scratch)))])] "optimize_insn_for_size_p () - && INTVAL (operands[0]) == 2*GET_MODE_SIZE (Pmode)" - [(parallel [(set (match_dup 1) (mem:P (post_inc:P (reg:P SP_REG)))) + && INTVAL (operands[0]) == 2*GET_MODE_SIZE (word_mode)" + [(parallel [(set (match_dup 1) (mem:W (post_inc:P (reg:P SP_REG)))) (clobber (mem:BLK (scratch)))]) - (set (match_dup 1) (mem:P (post_inc:P (reg:P SP_REG))))]) + (set (match_dup 1) (mem:W (post_inc:P (reg:P SP_REG))))]) ;; Convert esp additions to pop. (define_peephole2 - [(match_scratch:P 1 "r") + [(match_scratch:W 1 "r") (parallel [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) - (match_operand:P 0 "const_int_operand" ""))) + (match_operand:P 0 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))])] - "INTVAL (operands[0]) == GET_MODE_SIZE (Pmode)" - [(set (match_dup 1) (mem:P (post_inc:P (reg:P SP_REG))))]) + "INTVAL (operands[0]) == GET_MODE_SIZE (word_mode)" + [(set (match_dup 1) (mem:W (post_inc:P (reg:P SP_REG))))]) ;; Two pops case is tricky, since pop causes dependency ;; on destination register. We use two registers if available. (define_peephole2 - [(match_scratch:P 1 "r") - (match_scratch:P 2 "r") + [(match_scratch:W 1 "r") + (match_scratch:W 2 "r") (parallel [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) - (match_operand:P 0 "const_int_operand" ""))) + (match_operand:P 0 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))])] - "INTVAL (operands[0]) == 2*GET_MODE_SIZE (Pmode)" - [(set (match_dup 1) (mem:P (post_inc:P (reg:P SP_REG)))) - (set (match_dup 2) (mem:P (post_inc:P (reg:P SP_REG))))]) + "INTVAL (operands[0]) == 2*GET_MODE_SIZE (word_mode)" + [(set (match_dup 1) (mem:W (post_inc:P (reg:P SP_REG)))) + (set (match_dup 2) (mem:W (post_inc:P (reg:P SP_REG))))]) (define_peephole2 - [(match_scratch:P 1 "r") + [(match_scratch:W 1 "r") (parallel [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) - (match_operand:P 0 "const_int_operand" ""))) + (match_operand:P 0 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))])] "optimize_insn_for_size_p () - && INTVAL (operands[0]) == 2*GET_MODE_SIZE (Pmode)" - [(set (match_dup 1) (mem:P (post_inc:P (reg:P SP_REG)))) - (set (match_dup 1) (mem:P (post_inc:P (reg:P SP_REG))))]) + && INTVAL (operands[0]) == 2*GET_MODE_SIZE (word_mode)" + [(set (match_dup 1) (mem:W (post_inc:P (reg:P SP_REG)))) + (set (match_dup 1) (mem:W (post_inc:P (reg:P SP_REG))))]) ;; Convert compares with 1 to shorter inc/dec operations when CF is not ;; required and register dies. Similarly for 128 to -128. (define_peephole2 - [(set (match_operand 0 "flags_reg_operand" "") + [(set (match_operand 0 "flags_reg_operand") (match_operator 1 "compare_operator" - [(match_operand 2 "register_operand" "") - (match_operand 3 "const_int_operand" "")]))] + [(match_operand 2 "register_operand") + (match_operand 3 "const_int_operand")]))] "(((!TARGET_FUSE_CMP_AND_BRANCH || optimize_insn_for_size_p ()) && incdec_operand (operands[3], GET_MODE (operands[3]))) || (!TARGET_FUSE_CMP_AND_BRANCH @@ -17525,9 +17545,9 @@ ;; Convert imul by three, five and nine into lea (define_peephole2 [(parallel - [(set (match_operand:SWI48 0 "register_operand" "") - (mult:SWI48 (match_operand:SWI48 1 "register_operand" "") - (match_operand:SWI48 2 "const359_operand" ""))) + [(set (match_operand:SWI48 0 "register_operand") + (mult:SWI48 (match_operand:SWI48 1 "register_operand") + (match_operand:SWI48 2 "const359_operand"))) (clobber (reg:CC FLAGS_REG))])] "!TARGET_PARTIAL_REG_STALL || mode == SImode @@ -17539,9 +17559,9 @@ (define_peephole2 [(parallel - [(set (match_operand:SWI48 0 "register_operand" "") - (mult:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "") - (match_operand:SWI48 2 "const359_operand" ""))) + [(set (match_operand:SWI48 0 "register_operand") + (mult:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") + (match_operand:SWI48 2 "const359_operand"))) (clobber (reg:CC FLAGS_REG))])] "optimize_insn_for_speed_p () && (!TARGET_PARTIAL_REG_STALL || mode == SImode)" @@ -17555,9 +17575,9 @@ ;; imul $32bit_imm, reg, reg is direct decoded. (define_peephole2 [(match_scratch:SWI48 3 "r") - (parallel [(set (match_operand:SWI48 0 "register_operand" "") - (mult:SWI48 (match_operand:SWI48 1 "memory_operand" "") - (match_operand:SWI48 2 "immediate_operand" ""))) + (parallel [(set (match_operand:SWI48 0 "register_operand") + (mult:SWI48 (match_operand:SWI48 1 "memory_operand") + (match_operand:SWI48 2 "immediate_operand"))) (clobber (reg:CC FLAGS_REG))])] "TARGET_SLOW_IMUL_IMM32_MEM && optimize_insn_for_speed_p () && !satisfies_constraint_K (operands[2])" @@ -17567,10 +17587,10 @@ (define_peephole2 [(match_scratch:SI 3 "r") - (parallel [(set (match_operand:DI 0 "register_operand" "") + (parallel [(set (match_operand:DI 0 "register_operand") (zero_extend:DI - (mult:SI (match_operand:SI 1 "memory_operand" "") - (match_operand:SI 2 "immediate_operand" "")))) + (mult:SI (match_operand:SI 1 "memory_operand") + (match_operand:SI 2 "immediate_operand")))) (clobber (reg:CC FLAGS_REG))])] "TARGET_64BIT && TARGET_SLOW_IMUL_IMM32_MEM && optimize_insn_for_speed_p () @@ -17585,10 +17605,10 @@ ;; It would be better to force assembler to encode instruction using long ;; immediate, but there is apparently no way to do so. (define_peephole2 - [(parallel [(set (match_operand:SWI248 0 "register_operand" "") + [(parallel [(set (match_operand:SWI248 0 "register_operand") (mult:SWI248 - (match_operand:SWI248 1 "nonimmediate_operand" "") - (match_operand:SWI248 2 "const_int_operand" ""))) + (match_operand:SWI248 1 "nonimmediate_operand") + (match_operand:SWI248 2 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))]) (match_scratch:SWI248 3 "r")] "TARGET_SLOW_IMUL_IMM8 && optimize_insn_for_speed_p () @@ -17614,14 +17634,14 @@ ;; leal (%edx,%eax,4), %eax (define_peephole2 - [(match_scratch:P 5 "r") - (parallel [(set (match_operand 0 "register_operand" "") - (ashift (match_operand 1 "register_operand" "") - (match_operand 2 "const_int_operand" ""))) + [(match_scratch:W 5 "r") + (parallel [(set (match_operand 0 "register_operand") + (ashift (match_operand 1 "register_operand") + (match_operand 2 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))]) - (parallel [(set (match_operand 3 "register_operand" "") + (parallel [(set (match_operand 3 "register_operand") (plus (match_dup 0) - (match_operand 4 "x86_64_general_operand" ""))) + (match_operand 4 "x86_64_general_operand"))) (clobber (reg:CC FLAGS_REG))])] "IN_RANGE (INTVAL (operands[2]), 1, 3) /* Validate MODE for lea. */ @@ -17640,16 +17660,16 @@ enum machine_mode op1mode = GET_MODE (operands[1]); enum machine_mode mode = op1mode == DImode ? DImode : SImode; int scale = 1 << INTVAL (operands[2]); - rtx index = gen_lowpart (Pmode, operands[1]); - rtx base = gen_lowpart (Pmode, operands[5]); + rtx index = gen_lowpart (word_mode, operands[1]); + rtx base = gen_lowpart (word_mode, operands[5]); rtx dest = gen_lowpart (mode, operands[3]); - operands[1] = gen_rtx_PLUS (Pmode, base, - gen_rtx_MULT (Pmode, index, GEN_INT (scale))); + operands[1] = gen_rtx_PLUS (word_mode, base, + gen_rtx_MULT (word_mode, index, GEN_INT (scale))); operands[5] = base; - if (mode != Pmode) + if (mode != word_mode) operands[1] = gen_rtx_SUBREG (mode, operands[1], 0); - if (op1mode != Pmode) + if (op1mode != word_mode) operands[5] = gen_rtx_SUBREG (op1mode, operands[5], 0); operands[0] = dest; }) @@ -17666,9 +17686,9 @@ [(set_attr "length" "2")]) (define_expand "prefetch" - [(prefetch (match_operand 0 "address_operand" "") - (match_operand:SI 1 "const_int_operand" "") - (match_operand:SI 2 "const_int_operand" ""))] + [(prefetch (match_operand 0 "address_operand") + (match_operand:SI 1 "const_int_operand") + (match_operand:SI 2 "const_int_operand"))] "TARGET_PREFETCH_SSE || TARGET_3DNOW" { int rw = INTVAL (operands[1]); @@ -17692,7 +17712,7 @@ (define_insn "*prefetch_sse_" [(prefetch (match_operand:P 0 "address_operand" "p") (const_int 0) - (match_operand:SI 1 "const_int_operand" ""))] + (match_operand:SI 1 "const_int_operand"))] "TARGET_PREFETCH_SSE" { static const char * const patterns[4] = { @@ -17727,8 +17747,8 @@ (set_attr "memory" "none")]) (define_expand "stack_protect_set" - [(match_operand 0 "memory_operand" "") - (match_operand 1 "memory_operand" "")] + [(match_operand 0 "memory_operand") + (match_operand 1 "memory_operand")] "" { rtx (*insn)(rtx, rtx); @@ -17769,9 +17789,9 @@ [(set_attr "type" "multi")]) (define_expand "stack_protect_test" - [(match_operand 0 "memory_operand" "") - (match_operand 1 "memory_operand" "") - (match_operand 2 "" "")] + [(match_operand 0 "memory_operand") + (match_operand 1 "memory_operand") + (match_operand 2)] "" { rtx flags = gen_rtx_REG (CCZmode, FLAGS_REG); @@ -17797,7 +17817,7 @@ }) (define_insn "stack_protect_test_" - [(set (match_operand:CCZ 0 "flags_reg_operand" "") + [(set (match_operand:CCZ 0 "flags_reg_operand") (unspec:CCZ [(match_operand:PTR 1 "memory_operand" "m") (match_operand:PTR 2 "memory_operand" "m")] UNSPEC_SP_TEST)) @@ -17807,7 +17827,7 @@ [(set_attr "type" "multi")]) (define_insn "stack_tls_protect_test_" - [(set (match_operand:CCZ 0 "flags_reg_operand" "") + [(set (match_operand:CCZ 0 "flags_reg_operand") (unspec:CCZ [(match_operand:PTR 1 "memory_operand" "m") (match_operand:PTR 2 "const_int_operand" "i")] UNSPEC_SP_TLS_TEST)) @@ -17828,11 +17848,11 @@ (set_attr "prefix_rep" "1") (set_attr "prefix_extra" "1") (set (attr "prefix_data16") - (if_then_else (match_operand:HI 2 "" "") + (if_then_else (match_operand:HI 2) (const_string "1") (const_string "*"))) (set (attr "prefix_rex") - (if_then_else (match_operand:QI 2 "ext_QIreg_operand" "") + (if_then_else (match_operand:QI 2 "ext_QIreg_operand") (const_string "1") (const_string "*"))) (set_attr "mode" "SI")]) @@ -17851,8 +17871,8 @@ (set_attr "mode" "DI")]) (define_expand "rdpmc" - [(match_operand:DI 0 "register_operand" "") - (match_operand:SI 1 "register_operand" "")] + [(match_operand:DI 0 "register_operand") + (match_operand:SI 1 "register_operand")] "" { rtx reg = gen_reg_rtx (DImode); @@ -17907,7 +17927,7 @@ (set_attr "length" "2")]) (define_expand "rdtsc" - [(set (match_operand:DI 0 "register_operand" "") + [(set (match_operand:DI 0 "register_operand") (unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSC))] "" { @@ -17951,8 +17971,8 @@ (set_attr "length" "2")]) (define_expand "rdtscp" - [(match_operand:DI 0 "register_operand" "") - (match_operand:SI 1 "memory_operand" "")] + [(match_operand:DI 0 "register_operand") + (match_operand:SI 1 "memory_operand")] "" { rtx di = gen_rtx_UNSPEC_VOLATILE (DImode, @@ -18040,7 +18060,7 @@ { rtx (*insn)(rtx); - insn = (TARGET_64BIT + insn = (Pmode == DImode ? gen_lwp_slwpcbdi : gen_lwp_slwpcbsi); @@ -18063,8 +18083,8 @@ (match_operand:SI 3 "const_int_operand" "i")] UNSPECV_LWPVAL_INTRINSIC)] "TARGET_LWP" - "/* Avoid unused variable warning. */ - (void) operand0;") + ;; Avoid unused variable warning. + "(void) operands[0];") (define_insn "*lwp_lwpval3_1" [(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r") @@ -18155,13 +18175,79 @@ ;; Use "rep; nop", instead of "pause", to support older assemblers. ;; They have the same encoding. (define_insn "*pause" - [(set (match_operand:BLK 0 "" "") + [(set (match_operand:BLK 0) (unspec:BLK [(match_dup 0)] UNSPEC_PAUSE))] "" "rep; nop" [(set_attr "length" "2") (set_attr "memory" "unknown")]) +(define_expand "xbegin" + [(set (match_operand:SI 0 "register_operand") + (unspec_volatile:SI [(match_dup 1)] UNSPECV_XBEGIN))] + "TARGET_RTM" +{ + rtx label = gen_label_rtx (); + + operands[1] = force_reg (SImode, constm1_rtx); + + emit_jump_insn (gen_xbegin_1 (operands[0], operands[1], label)); + + emit_label (label); + LABEL_NUSES (label) = 1; + + DONE; +}) + +(define_insn "xbegin_1" + [(set (pc) + (if_then_else (ne (unspec [(const_int 0)] UNSPEC_XBEGIN_ABORT) + (const_int 0)) + (label_ref (match_operand 2)) + (pc))) + (set (match_operand:SI 0 "register_operand" "=a") + (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "0")] + UNSPECV_XBEGIN))] + "TARGET_RTM" + "xbegin\t%l2" + [(set_attr "type" "other") + (set_attr "length" "6")]) + +(define_insn "xend" + [(unspec_volatile [(const_int 0)] UNSPECV_XEND)] + "TARGET_RTM" + "xend" + [(set_attr "type" "other") + (set_attr "length" "3")]) + +(define_insn "xabort" + [(unspec_volatile [(match_operand:SI 0 "const_0_to_255_operand" "n")] + UNSPECV_XABORT)] + "TARGET_RTM" + "xabort\t%0" + [(set_attr "type" "other") + (set_attr "length" "3")]) + +(define_expand "xtest" + [(set (match_operand:QI 0 "register_operand") + (unspec_volatile:QI [(const_int 0)] UNSPECV_XTEST))] + "TARGET_RTM" +{ + emit_insn (gen_xtest_1 ()); + + ix86_expand_setcc (operands[0], EQ, + gen_rtx_REG (CCZmode, FLAGS_REG), const0_rtx); + DONE; +}) + +(define_insn "xtest_1" + [(set (reg:CCZ FLAGS_REG) + (unspec_volatile:CCZ [(const_int 0)] UNSPECV_XTEST))] + "TARGET_RTM" + "xtest" + [(set_attr "type" "other") + (set_attr "length" "3")]) + (include "mmx.md") (include "sse.md") (include "sync.md")