X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=gcc%2Fdoc%2Ftm.texi.in;h=dff6cf8e038701215ab81d0ac153231a68554adb;hb=29eb9a442b145c3b637e7b41000e51148969c989;hp=7d8dcff14ea8efb75b3b0df5e1a42b9a97cfbde2;hpb=42e02b207fdf71f09020eef2bba3e25f5f57a946;p=gcc.git diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in index 7d8dcff14ea..dff6cf8e038 100644 --- a/gcc/doc/tm.texi.in +++ b/gcc/doc/tm.texi.in @@ -1,4 +1,4 @@ -@c Copyright (C) 1988-2016 Free Software Foundation, Inc. +@c Copyright (C) 1988-2017 Free Software Foundation, Inc. @c This is part of the GCC manual. @c For copying conditions, see the file gcc.texi. @@ -990,13 +990,15 @@ structure and union fields only, unless the field alignment has been set by the @code{__attribute__ ((aligned (@var{n})))} construct. @end defmac -@defmac ADJUST_FIELD_ALIGN (@var{field}, @var{computed}) -An expression for the alignment of a structure field @var{field} if the -alignment computed in the usual way (including applying of -@code{BIGGEST_ALIGNMENT} and @code{BIGGEST_FIELD_ALIGNMENT} to the +@defmac ADJUST_FIELD_ALIGN (@var{field}, @var{type}, @var{computed}) +An expression for the alignment of a structure field @var{field} of +type @var{type} if the alignment computed in the usual way (including +applying of @code{BIGGEST_ALIGNMENT} and @code{BIGGEST_FIELD_ALIGNMENT} to the alignment) is @var{computed}. It overrides alignment only if the field alignment has not been set by the -@code{__attribute__ ((aligned (@var{n})))} construct. +@code{__attribute__ ((aligned (@var{n})))} construct. Note that @var{field} +may be @code{NULL_TREE} in case we just query for the minimum alignment +of a field of type @var{type} in structure context. @end defmac @defmac MAX_STACK_ALIGNMENT @@ -1402,13 +1404,6 @@ uses this macro should also arrange to use @file{t-gnu-prefix} in the libgcc @file{config.host}. @end defmac -@defmac TARGET_FLT_EVAL_METHOD -A C expression for the value for @code{FLT_EVAL_METHOD} in @file{float.h}, -assuming, if applicable, that the floating-point control word is in its -default state. If you do not define this macro the value of -@code{FLT_EVAL_METHOD} will be zero. -@end defmac - @defmac WIDEST_HARDWARE_FP_SIZE A C expression for the size in bits of the widest floating-point format supported by the hardware. If you define this macro, you must specify a @@ -2309,7 +2304,7 @@ force @var{x} into a memory location. For example, rs6000 can load immediate values into general-purpose registers, but does not have an instruction for loading an immediate value into a floating-point register, so @code{PREFERRED_RELOAD_CLASS} returns @code{NO_REGS} when -@var{x} is a floating-point constant. If the constant can't be loaded +@var{x} is a floating-point constant. If the constant cannot be loaded into any kind of register, code generation will be better if @code{TARGET_LEGITIMATE_CONSTANT_P} makes the constant illegitimate instead of using @code{TARGET_PREFERRED_RELOAD_CLASS}. @@ -2331,7 +2326,7 @@ to use when it is necessary to be able to hold a value of mode ordinarily be used. Unlike @code{PREFERRED_RELOAD_CLASS}, this macro should be used when -there are certain modes that simply can't go in certain reload classes. +there are certain modes that simply cannot go in certain reload classes. The value is a register class; perhaps @var{class}, or perhaps another, smaller class. @@ -3218,6 +3213,8 @@ such as the result of @code{get_frame_size ()} and the tables of registers @code{df_regs_ever_live_p} and @code{call_used_regs}. @end defmac +@hook TARGET_COMPUTE_FRAME_LAYOUT + @node Stack Arguments @subsection Passing Function Arguments on the Stack @cindex arguments on stack @@ -3827,6 +3824,8 @@ generic code. @hook TARGET_STACK_PROTECT_FAIL +@hook TARGET_STACK_PROTECT_RUNTIME_ENABLED_P + @hook TARGET_SUPPORTS_SPLIT_STACK @node Miscellaneous Register Hooks @@ -4111,8 +4110,6 @@ In either case, it remains possible to select code-generation for the alternate scheme, by means of compiler command line switches. @end defmac -@hook TARGET_PRINTF_POINTER_FORMAT - @node Addressing Modes @section Addressing Modes @cindex addressing modes @@ -4801,6 +4798,8 @@ Define this macro if a non-short-circuit operation produced by @hook TARGET_MAX_NOCE_IFCVT_SEQ_COST +@hook TARGET_NOCE_CONVERSION_PROFITABLE_P + @hook TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P @node Scheduling @@ -4889,6 +4888,8 @@ them: try the first ones in this list first. @hook TARGET_SCHED_SET_SCHED_FLAGS +@hook TARGET_SCHED_CAN_SPECULATE_INSN + @hook TARGET_SCHED_SMS_RES_MII @hook TARGET_SCHED_DISPATCH @@ -7269,7 +7270,7 @@ floating point operations, but to perform a single precision operation, the FPSCR PR bit has to be cleared, while for a double precision operation, this bit has to be set. Changing the PR bit requires a general purpose register as a scratch register, hence these FPSCR sets have to -be inserted before reload, i.e.@: you can't put this into instruction emitting +be inserted before reload, i.e.@: you cannot put this into instruction emitting or @code{TARGET_MACHINE_DEPENDENT_REORG}. You can have multiple entities that are mode-switched, and select at run time