X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=gdb%2Famd64-tdep.c;h=b95ab1e87b81db582768ca5696d588988f6730d1;hb=ea764154c27a11619ba764a4c92f395ba5007234;hp=c76810342f20dc1a8920b881293cb1cc40a64732;hpb=61012eef8463764ccd9117dc1c9bc43cc452b7cc;p=binutils-gdb.git diff --git a/gdb/amd64-tdep.c b/gdb/amd64-tdep.c index c76810342f2..b95ab1e87b8 100644 --- a/gdb/amd64-tdep.c +++ b/gdb/amd64-tdep.c @@ -1,6 +1,6 @@ /* Target-dependent code for AMD64. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2022 Free Software Foundation, Inc. Contributed by Jiri Smid, SuSE Labs. @@ -39,18 +39,17 @@ #include "disasm.h" #include "amd64-tdep.h" #include "i387-tdep.h" - -#include "features/i386/amd64.c" -#include "features/i386/amd64-avx.c" -#include "features/i386/amd64-mpx.c" -#include "features/i386/amd64-avx512.c" - -#include "features/i386/x32.c" -#include "features/i386/x32-avx.c" -#include "features/i386/x32-avx512.c" - +#include "gdbsupport/x86-xstate.h" +#include +#include "target-descriptions.h" +#include "arch/amd64.h" +#include "producer.h" #include "ax.h" #include "ax-gdb.h" +#include "gdbsupport/byte-vector.h" +#include "osabi.h" +#include "x86-tdep.h" +#include "amd64-ravenscar-thread.h" /* Note that the AMD64 architecture was previously known as x86-64. The latter is (forever) engraved into the canonical system name as @@ -61,7 +60,7 @@ /* Register information. */ -static const char *amd64_register_names[] = +static const char * const amd64_register_names[] = { "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp", @@ -79,7 +78,7 @@ static const char *amd64_register_names[] = "mxcsr", }; -static const char *amd64_ymm_names[] = +static const char * const amd64_ymm_names[] = { "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", @@ -87,7 +86,7 @@ static const char *amd64_ymm_names[] = "ymm12", "ymm13", "ymm14", "ymm15" }; -static const char *amd64_ymm_avx512_names[] = +static const char * const amd64_ymm_avx512_names[] = { "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", @@ -95,7 +94,7 @@ static const char *amd64_ymm_avx512_names[] = "ymm28", "ymm29", "ymm30", "ymm31" }; -static const char *amd64_ymmh_names[] = +static const char * const amd64_ymmh_names[] = { "ymm0h", "ymm1h", "ymm2h", "ymm3h", "ymm4h", "ymm5h", "ymm6h", "ymm7h", @@ -103,7 +102,7 @@ static const char *amd64_ymmh_names[] = "ymm12h", "ymm13h", "ymm14h", "ymm15h" }; -static const char *amd64_ymmh_avx512_names[] = +static const char * const amd64_ymmh_avx512_names[] = { "ymm16h", "ymm17h", "ymm18h", "ymm19h", "ymm20h", "ymm21h", "ymm22h", "ymm23h", @@ -111,18 +110,18 @@ static const char *amd64_ymmh_avx512_names[] = "ymm28h", "ymm29h", "ymm30h", "ymm31h" }; -static const char *amd64_mpx_names[] = +static const char * const amd64_mpx_names[] = { "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus" }; -static const char *amd64_k_names[] = +static const char * const amd64_k_names[] = { "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" }; -static const char *amd64_zmmh_names[] = +static const char * const amd64_zmmh_names[] = { "zmm0h", "zmm1h", "zmm2h", "zmm3h", "zmm4h", "zmm5h", "zmm6h", "zmm7h", @@ -134,7 +133,7 @@ static const char *amd64_zmmh_names[] = "zmm28h", "zmm29h", "zmm30h", "zmm31h" }; -static const char *amd64_zmm_names[] = +static const char * const amd64_zmm_names[] = { "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", @@ -146,13 +145,17 @@ static const char *amd64_zmm_names[] = "zmm28", "zmm29", "zmm30", "zmm31" }; -static const char *amd64_xmm_avx512_names[] = { +static const char * const amd64_xmm_avx512_names[] = { "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31" }; +static const char * const amd64_pkeys_names[] = { + "pkru" +}; + /* DWARF Register Number Mapping as defined in the System V psABI, section 3.6. */ @@ -244,16 +247,14 @@ static const int amd64_dwarf_regmap_len = static int amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) { - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + i386_gdbarch_tdep *tdep = (i386_gdbarch_tdep *) gdbarch_tdep (gdbarch); int ymm0_regnum = tdep->ymm0_regnum; int regnum = -1; if (reg >= 0 && reg < amd64_dwarf_regmap_len) regnum = amd64_dwarf_regmap[reg]; - if (regnum == -1) - warning (_("Unmapped DWARF Register #%d encountered."), reg); - else if (ymm0_regnum >= 0 + if (ymm0_regnum >= 0 && i386_xmm_regnum_p (gdbarch, regnum)) regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep); @@ -298,7 +299,7 @@ amd64_arch_reg_to_regnum (int reg) /* Register names for byte pseudo-registers. */ -static const char *amd64_byte_names[] = +static const char * const amd64_byte_names[] = { "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl", "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l", @@ -310,7 +311,7 @@ static const char *amd64_byte_names[] = /* Register names for word pseudo-registers. */ -static const char *amd64_word_names[] = +static const char * const amd64_word_names[] = { "ax", "bx", "cx", "dx", "si", "di", "bp", "", "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" @@ -318,7 +319,7 @@ static const char *amd64_word_names[] = /* Register names for dword pseudo-registers. */ -static const char *amd64_dword_names[] = +static const char * const amd64_dword_names[] = { "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp", "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d", @@ -330,7 +331,7 @@ static const char *amd64_dword_names[] = static const char * amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum) { - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + i386_gdbarch_tdep *tdep = (i386_gdbarch_tdep *) gdbarch_tdep (gdbarch); if (i386_byte_regnum_p (gdbarch, regnum)) return amd64_byte_names[regnum - tdep->al_regnum]; else if (i386_zmm_regnum_p (gdbarch, regnum)) @@ -349,19 +350,15 @@ amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum) static struct value * amd64_pseudo_register_read_value (struct gdbarch *gdbarch, - struct regcache *regcache, + readable_regcache *regcache, int regnum) { - gdb_byte raw_buf[MAX_REGISTER_SIZE]; - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - enum register_status status; - struct value *result_value; - gdb_byte *buf; + i386_gdbarch_tdep *tdep = (i386_gdbarch_tdep *) gdbarch_tdep (gdbarch); - result_value = allocate_value (register_type (gdbarch, regnum)); + value *result_value = allocate_value (register_type (gdbarch, regnum)); VALUE_LVAL (result_value) = lval_register; VALUE_REGNUM (result_value) = regnum; - buf = value_contents_raw (result_value); + gdb_byte *buf = value_contents_raw (result_value).data (); if (i386_byte_regnum_p (gdbarch, regnum)) { @@ -370,10 +367,11 @@ amd64_pseudo_register_read_value (struct gdbarch *gdbarch, /* Extract (always little endian). */ if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS) { + gpnum -= AMD64_NUM_LOWER_BYTE_REGS; + gdb_byte raw_buf[register_size (gdbarch, gpnum)]; + /* Special handling for AH, BH, CH, DH. */ - status = regcache_raw_read (regcache, - gpnum - AMD64_NUM_LOWER_BYTE_REGS, - raw_buf); + register_status status = regcache->raw_read (gpnum, raw_buf); if (status == REG_VALID) memcpy (buf, raw_buf + 1, 1); else @@ -382,7 +380,8 @@ amd64_pseudo_register_read_value (struct gdbarch *gdbarch, } else { - status = regcache_raw_read (regcache, gpnum, raw_buf); + gdb_byte raw_buf[register_size (gdbarch, gpnum)]; + register_status status = regcache->raw_read (gpnum, raw_buf); if (status == REG_VALID) memcpy (buf, raw_buf, 1); else @@ -393,8 +392,9 @@ amd64_pseudo_register_read_value (struct gdbarch *gdbarch, else if (i386_dword_regnum_p (gdbarch, regnum)) { int gpnum = regnum - tdep->eax_regnum; + gdb_byte raw_buf[register_size (gdbarch, gpnum)]; /* Extract (always little endian). */ - status = regcache_raw_read (regcache, gpnum, raw_buf); + register_status status = regcache->raw_read (gpnum, raw_buf); if (status == REG_VALID) memcpy (buf, raw_buf, 4); else @@ -413,8 +413,7 @@ amd64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, int regnum, const gdb_byte *buf) { - gdb_byte raw_buf[MAX_REGISTER_SIZE]; - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + i386_gdbarch_tdep *tdep = (i386_gdbarch_tdep *) gdbarch_tdep (gdbarch); if (i386_byte_regnum_p (gdbarch, regnum)) { @@ -422,40 +421,73 @@ amd64_pseudo_register_write (struct gdbarch *gdbarch, if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS) { + gpnum -= AMD64_NUM_LOWER_BYTE_REGS; + gdb_byte raw_buf[register_size (gdbarch, gpnum)]; + /* Read ... AH, BH, CH, DH. */ - regcache_raw_read (regcache, - gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf); + regcache->raw_read (gpnum, raw_buf); /* ... Modify ... (always little endian). */ memcpy (raw_buf + 1, buf, 1); /* ... Write. */ - regcache_raw_write (regcache, - gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf); + regcache->raw_write (gpnum, raw_buf); } else { + gdb_byte raw_buf[register_size (gdbarch, gpnum)]; + /* Read ... */ - regcache_raw_read (regcache, gpnum, raw_buf); + regcache->raw_read (gpnum, raw_buf); /* ... Modify ... (always little endian). */ memcpy (raw_buf, buf, 1); /* ... Write. */ - regcache_raw_write (regcache, gpnum, raw_buf); + regcache->raw_write (gpnum, raw_buf); } } else if (i386_dword_regnum_p (gdbarch, regnum)) { int gpnum = regnum - tdep->eax_regnum; + gdb_byte raw_buf[register_size (gdbarch, gpnum)]; /* Read ... */ - regcache_raw_read (regcache, gpnum, raw_buf); + regcache->raw_read (gpnum, raw_buf); /* ... Modify ... (always little endian). */ memcpy (raw_buf, buf, 4); /* ... Write. */ - regcache_raw_write (regcache, gpnum, raw_buf); + regcache->raw_write (gpnum, raw_buf); } else i386_pseudo_register_write (gdbarch, regcache, regnum, buf); } +/* Implement the 'ax_pseudo_register_collect' gdbarch method. */ + +static int +amd64_ax_pseudo_register_collect (struct gdbarch *gdbarch, + struct agent_expr *ax, int regnum) +{ + i386_gdbarch_tdep *tdep = (i386_gdbarch_tdep *) gdbarch_tdep (gdbarch); + + if (i386_byte_regnum_p (gdbarch, regnum)) + { + int gpnum = regnum - tdep->al_regnum; + + if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS) + ax_reg_mask (ax, gpnum - AMD64_NUM_LOWER_BYTE_REGS); + else + ax_reg_mask (ax, gpnum); + return 0; + } + else if (i386_dword_regnum_p (gdbarch, regnum)) + { + int gpnum = regnum - tdep->eax_regnum; + + ax_reg_mask (ax, gpnum); + return 0; + } + else + return i386_ax_pseudo_register_collect (gdbarch, ax, regnum); +} + /* Register classes as defined in the psABI. */ @@ -510,17 +542,112 @@ amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2) static void amd64_classify (struct type *type, enum amd64_reg_class theclass[2]); -/* Return non-zero if TYPE is a non-POD structure or union type. */ +/* Return true if TYPE is a structure or union with unaligned fields. */ -static int -amd64_non_pod_p (struct type *type) +static bool +amd64_has_unaligned_fields (struct type *type) { - /* ??? A class with a base class certainly isn't POD, but does this - catch all non-POD structure types? */ - if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0) - return 1; + if (type->code () == TYPE_CODE_STRUCT + || type->code () == TYPE_CODE_UNION) + { + for (int i = 0; i < type->num_fields (); i++) + { + struct type *subtype = check_typedef (type->field (i).type ()); + + /* Ignore static fields, empty fields (for example nested + empty structures), and bitfields (these are handled by + the caller). */ + if (field_is_static (&type->field (i)) + || (TYPE_FIELD_BITSIZE (type, i) == 0 + && TYPE_LENGTH (subtype) == 0) + || TYPE_FIELD_PACKED (type, i)) + continue; - return 0; + int bitpos = type->field (i).loc_bitpos (); + + if (bitpos % 8 != 0) + return true; + + int align = type_align (subtype); + if (align == 0) + error (_("could not determine alignment of type")); + + int bytepos = bitpos / 8; + if (bytepos % align != 0) + return true; + + if (amd64_has_unaligned_fields (subtype)) + return true; + } + } + + return false; +} + +/* Classify field I of TYPE starting at BITOFFSET according to the rules for + structures and union types, and store the result in THECLASS. */ + +static void +amd64_classify_aggregate_field (struct type *type, int i, + enum amd64_reg_class theclass[2], + unsigned int bitoffset) +{ + struct type *subtype = check_typedef (type->field (i).type ()); + enum amd64_reg_class subclass[2]; + int bitsize = TYPE_FIELD_BITSIZE (type, i); + + if (bitsize == 0) + bitsize = TYPE_LENGTH (subtype) * 8; + + /* Ignore static fields, or empty fields, for example nested + empty structures.*/ + if (field_is_static (&type->field (i)) || bitsize == 0) + return; + + int bitpos = bitoffset + type->field (i).loc_bitpos (); + int pos = bitpos / 64; + int endpos = (bitpos + bitsize - 1) / 64; + + if (subtype->code () == TYPE_CODE_STRUCT + || subtype->code () == TYPE_CODE_UNION) + { + /* Each field of an object is classified recursively. */ + int j; + for (j = 0; j < subtype->num_fields (); j++) + amd64_classify_aggregate_field (subtype, j, theclass, bitpos); + return; + } + + gdb_assert (pos == 0 || pos == 1); + + amd64_classify (subtype, subclass); + theclass[pos] = amd64_merge_classes (theclass[pos], subclass[0]); + if (bitsize <= 64 && pos == 0 && endpos == 1) + /* This is a bit of an odd case: We have a field that would + normally fit in one of the two eightbytes, except that + it is placed in a way that this field straddles them. + This has been seen with a structure containing an array. + + The ABI is a bit unclear in this case, but we assume that + this field's class (stored in subclass[0]) must also be merged + into class[1]. In other words, our field has a piece stored + in the second eight-byte, and thus its class applies to + the second eight-byte as well. + + In the case where the field length exceeds 8 bytes, + it should not be necessary to merge the field class + into class[1]. As LEN > 8, subclass[1] is necessarily + different from AMD64_NO_CLASS. If subclass[1] is equal + to subclass[0], then the normal class[1]/subclass[1] + merging will take care of everything. For subclass[1] + to be different from subclass[0], I can only see the case + where we have a SSE/SSEUP or X87/X87UP pair, which both + use up all 16 bytes of the aggregate, and are already + handled just fine (because each portion sits on its own + 8-byte). */ + theclass[1] = amd64_merge_classes (theclass[1], subclass[0]); + if (pos == 0) + theclass[1] = amd64_merge_classes (theclass[1], subclass[1]); } /* Classify TYPE according to the rules for aggregate (structures and @@ -529,10 +656,19 @@ amd64_non_pod_p (struct type *type) static void amd64_classify_aggregate (struct type *type, enum amd64_reg_class theclass[2]) { - /* 1. If the size of an object is larger than two eightbytes, or in - C++, is a non-POD structure or union type, or contains - unaligned fields, it has class memory. */ - if (TYPE_LENGTH (type) > 16 || amd64_non_pod_p (type)) + /* 1. If the size of an object is larger than two times eight bytes, or + it is a non-trivial C++ object, or it has unaligned fields, then it + has class memory. + + It is important that the trivially_copyable check is before the + unaligned fields check, as C++ classes with virtual base classes + will have fields (for the virtual base classes) with non-constant + loc_bitpos attributes, which will cause an assert to trigger within + the unaligned field check. As classes with virtual bases are not + trivially copyable, checking that first avoids this problem. */ + if (TYPE_LENGTH (type) > 16 + || !language_pass_by_reference (type).trivially_copyable + || amd64_has_unaligned_fields (type)) { theclass[0] = theclass[1] = AMD64_MEMORY; return; @@ -542,11 +678,11 @@ amd64_classify_aggregate (struct type *type, enum amd64_reg_class theclass[2]) theclass[0] = theclass[1] = AMD64_NO_CLASS; /* 3. Each field of an object is classified recursively so that - always two fields are considered. The resulting class is - calculated according to the classes of the fields in the - eightbyte: */ + always two fields are considered. The resulting class is + calculated according to the classes of the fields in the + eightbyte: */ - if (TYPE_CODE (type) == TYPE_CODE_ARRAY) + if (type->code () == TYPE_CODE_ARRAY) { struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type)); @@ -560,56 +696,11 @@ amd64_classify_aggregate (struct type *type, enum amd64_reg_class theclass[2]) int i; /* Structure or union. */ - gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT - || TYPE_CODE (type) == TYPE_CODE_UNION); + gdb_assert (type->code () == TYPE_CODE_STRUCT + || type->code () == TYPE_CODE_UNION); - for (i = 0; i < TYPE_NFIELDS (type); i++) - { - struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i)); - int pos = TYPE_FIELD_BITPOS (type, i) / 64; - enum amd64_reg_class subclass[2]; - int bitsize = TYPE_FIELD_BITSIZE (type, i); - int endpos; - - if (bitsize == 0) - bitsize = TYPE_LENGTH (subtype) * 8; - endpos = (TYPE_FIELD_BITPOS (type, i) + bitsize - 1) / 64; - - /* Ignore static fields. */ - if (field_is_static (&TYPE_FIELD (type, i))) - continue; - - gdb_assert (pos == 0 || pos == 1); - - amd64_classify (subtype, subclass); - theclass[pos] = amd64_merge_classes (theclass[pos], subclass[0]); - if (bitsize <= 64 && pos == 0 && endpos == 1) - /* This is a bit of an odd case: We have a field that would - normally fit in one of the two eightbytes, except that - it is placed in a way that this field straddles them. - This has been seen with a structure containing an array. - - The ABI is a bit unclear in this case, but we assume that - this field's class (stored in subclass[0]) must also be merged - into class[1]. In other words, our field has a piece stored - in the second eight-byte, and thus its class applies to - the second eight-byte as well. - - In the case where the field length exceeds 8 bytes, - it should not be necessary to merge the field class - into class[1]. As LEN > 8, subclass[1] is necessarily - different from AMD64_NO_CLASS. If subclass[1] is equal - to subclass[0], then the normal class[1]/subclass[1] - merging will take care of everything. For subclass[1] - to be different from subclass[0], I can only see the case - where we have a SSE/SSEUP or X87/X87UP pair, which both - use up all 16 bytes of the aggregate, and are already - handled just fine (because each portion sits on its own - 8-byte). */ - theclass[1] = amd64_merge_classes (theclass[1], subclass[0]); - if (pos == 0) - theclass[1] = amd64_merge_classes (theclass[1], subclass[1]); - } + for (i = 0; i < type->num_fields (); i++) + amd64_classify_aggregate_field (type, i, theclass, 0); } /* 4. Then a post merger cleanup is done: */ @@ -632,7 +723,7 @@ amd64_classify_aggregate (struct type *type, enum amd64_reg_class theclass[2]) static void amd64_classify (struct type *type, enum amd64_reg_class theclass[2]) { - enum type_code code = TYPE_CODE (type); + enum type_code code = type->code (); int len = TYPE_LENGTH (type); theclass[0] = theclass[1] = AMD64_NO_CLASS; @@ -644,14 +735,14 @@ amd64_classify (struct type *type, enum amd64_reg_class theclass[2]) if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE || code == TYPE_CODE_CHAR - || code == TYPE_CODE_PTR || code == TYPE_CODE_REF) + || code == TYPE_CODE_PTR || TYPE_IS_REFERENCE (type)) && (len == 1 || len == 2 || len == 4 || len == 8)) theclass[0] = AMD64_INTEGER; - /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64 - are in class SSE. */ + /* Arguments of types _Float16, float, double, _Decimal32, _Decimal64 and + __m64 are in class SSE. */ else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT) - && (len == 4 || len == 8)) + && (len == 2 || len == 4 || len == 8)) /* FIXME: __m64 . */ theclass[0] = AMD64_SSE; @@ -669,8 +760,8 @@ amd64_classify (struct type *type, enum amd64_reg_class theclass[2]) /* Class X87 and X87UP. */ theclass[0] = AMD64_X87, theclass[1] = AMD64_X87UP; - /* Arguments of complex T where T is one of the types float or - double get treated as if they are implemented as: + /* Arguments of complex T - where T is one of the types _Float16, float or + double - get treated as if they are implemented as: struct complexT { T real; @@ -678,7 +769,7 @@ amd64_classify (struct type *type, enum amd64_reg_class theclass[2]) }; */ - else if (code == TYPE_CODE_COMPLEX && len == 8) + else if (code == TYPE_CODE_COMPLEX && (len == 8 || len == 4)) theclass[0] = AMD64_SSE; else if (code == TYPE_CODE_COMPLEX && len == 16) theclass[0] = theclass[1] = AMD64_SSE; @@ -722,8 +813,8 @@ amd64_return_value (struct gdbarch *gdbarch, struct value *function, if (theclass[0] == AMD64_MEMORY) { /* As indicated by the comment above, the ABI guarantees that we - can always find the return value just after the function has - returned. */ + can always find the return value just after the function has + returned. */ if (readbuf) { @@ -737,20 +828,20 @@ amd64_return_value (struct gdbarch *gdbarch, struct value *function, } /* 8. If the class is COMPLEX_X87, the real part of the value is - returned in %st0 and the imaginary part in %st1. */ + returned in %st0 and the imaginary part in %st1. */ if (theclass[0] == AMD64_COMPLEX_X87) { if (readbuf) { - regcache_raw_read (regcache, AMD64_ST0_REGNUM, readbuf); - regcache_raw_read (regcache, AMD64_ST1_REGNUM, readbuf + 16); + regcache->raw_read (AMD64_ST0_REGNUM, readbuf); + regcache->raw_read (AMD64_ST1_REGNUM, readbuf + 16); } if (writebuf) { i387_return_value (gdbarch, regcache); - regcache_raw_write (regcache, AMD64_ST0_REGNUM, writebuf); - regcache_raw_write (regcache, AMD64_ST1_REGNUM, writebuf + 16); + regcache->raw_write (AMD64_ST0_REGNUM, writebuf); + regcache->raw_write (AMD64_ST1_REGNUM, writebuf + 16); /* Fix up the tag word such that both %st(0) and %st(1) are marked as valid. */ @@ -778,7 +869,7 @@ amd64_return_value (struct gdbarch *gdbarch, struct value *function, case AMD64_SSE: /* 4. If the class is SSE, the next available SSE register - of the sequence %xmm0, %xmm1 is used. */ + of the sequence %xmm0, %xmm1 is used. */ regnum = sse_regnum[sse_reg++]; break; @@ -792,7 +883,7 @@ amd64_return_value (struct gdbarch *gdbarch, struct value *function, case AMD64_X87: /* 6. If the class is X87, the value is returned on the X87 - stack in %st0 as 80-bit x87 number. */ + stack in %st0 as 80-bit x87 number. */ regnum = AMD64_ST0_REGNUM; if (writebuf) i387_return_value (gdbarch, regcache); @@ -800,7 +891,7 @@ amd64_return_value (struct gdbarch *gdbarch, struct value *function, case AMD64_X87UP: /* 7. If the class is X87UP, the value is returned together - with the previous X87 value in %st0. */ + with the previous X87 value in %st0. */ gdb_assert (i > 0 && theclass[0] == AMD64_X87); regnum = AMD64_ST0_REGNUM; offset = 8; @@ -817,11 +908,11 @@ amd64_return_value (struct gdbarch *gdbarch, struct value *function, gdb_assert (regnum != -1); if (readbuf) - regcache_raw_read_part (regcache, regnum, offset, min (len, 8), - readbuf + i * 8); + regcache->raw_read_part (regnum, offset, std::min (len, 8), + readbuf + i * 8); if (writebuf) - regcache_raw_write_part (regcache, regnum, offset, min (len, 8), - writebuf + i * 8); + regcache->raw_write_part (regnum, offset, std::min (len, 8), + writebuf + i * 8); } return RETURN_VALUE_REGISTER_CONVENTION; @@ -829,8 +920,8 @@ amd64_return_value (struct gdbarch *gdbarch, struct value *function, static CORE_ADDR -amd64_push_arguments (struct regcache *regcache, int nargs, - struct value **args, CORE_ADDR sp, int struct_return) +amd64_push_arguments (struct regcache *regcache, int nargs, struct value **args, + CORE_ADDR sp, function_call_return_method return_method) { static int integer_regnum[] = { @@ -849,7 +940,7 @@ amd64_push_arguments (struct regcache *regcache, int nargs, AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, }; - struct value **stack_args = alloca (nargs * sizeof (struct value *)); + struct value **stack_args = XALLOCAVEC (struct value *, nargs); int num_stack_args = 0; int num_elements = 0; int element = 0; @@ -858,7 +949,7 @@ amd64_push_arguments (struct regcache *regcache, int nargs, int i; /* Reserve a register for the "hidden" argument. */ - if (struct_return) +if (return_method == return_method_struct) integer_reg++; for (i = 0; i < nargs; i++) @@ -874,7 +965,7 @@ amd64_push_arguments (struct regcache *regcache, int nargs, amd64_classify (type, theclass); /* Calculate the number of integer and SSE registers needed for - this argument. */ + this argument. */ for (j = 0; j < 2; j++) { if (theclass[j] == AMD64_INTEGER) @@ -884,7 +975,7 @@ amd64_push_arguments (struct regcache *regcache, int nargs, } /* Check whether enough registers are available, and if the - argument should be passed in registers at all. */ + argument should be passed in registers at all. */ if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum) || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum) || (needed_integer_regs == 0 && needed_sse_regs == 0)) @@ -896,7 +987,7 @@ amd64_push_arguments (struct regcache *regcache, int nargs, else { /* The argument will be passed in registers. */ - const gdb_byte *valbuf = value_contents (args[i]); + const gdb_byte *valbuf = value_contents (args[i]).data (); gdb_byte buf[8]; gdb_assert (len <= 16); @@ -922,14 +1013,17 @@ amd64_push_arguments (struct regcache *regcache, int nargs, offset = 8; break; + case AMD64_NO_CLASS: + continue; + default: gdb_assert (!"Unexpected register class."); } gdb_assert (regnum != -1); memset (buf, 0, sizeof buf); - memcpy (buf, valbuf + j * 8, min (len, 8)); - regcache_raw_write_part (regcache, regnum, offset, 8, buf); + memcpy (buf, valbuf + j * 8, std::min (len, 8)); + regcache->raw_write_part (regnum, offset, 8, buf); } } } @@ -945,7 +1039,7 @@ amd64_push_arguments (struct regcache *regcache, int nargs, for (i = 0; i < num_stack_args; i++) { struct type *type = value_type (stack_args[i]); - const gdb_byte *valbuf = value_contents (stack_args[i]); + const gdb_byte *valbuf = value_contents (stack_args[i]).data (); int len = TYPE_LENGTH (type); write_memory (sp + element * 8, valbuf, len); @@ -964,19 +1058,27 @@ static CORE_ADDR amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, - int struct_return, CORE_ADDR struct_addr) + function_call_return_method return_method, + CORE_ADDR struct_addr) { enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); gdb_byte buf[8]; + /* BND registers can be in arbitrary values at the moment of the + inferior call. This can cause boundary violations that are not + due to a real bug or even desired by the user. The best to be done + is set the BND registers to allow access to the whole memory, INIT + state, before pushing the inferior call. */ + i387_reset_bnd_regs (gdbarch, regcache); + /* Pass arguments. */ - sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return); + sp = amd64_push_arguments (regcache, nargs, args, sp, return_method); /* Pass "hidden" argument". */ - if (struct_return) + if (return_method == return_method_struct) { store_unsigned_integer (buf, 8, byte_order, struct_addr); - regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf); + regcache->cooked_write (AMD64_RDI_REGNUM, buf); } /* Store return address. */ @@ -986,10 +1088,10 @@ amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, /* Finally, update the stack pointer... */ store_unsigned_integer (buf, 8, byte_order, sp); - regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf); + regcache->cooked_write (AMD64_RSP_REGNUM, buf); /* ...and fake a frame pointer. */ - regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf); + regcache->cooked_write (AMD64_RBP_REGNUM, buf); return sp + 16; } @@ -1003,8 +1105,9 @@ struct amd64_insn { /* The number of opcode bytes. */ int opcode_len; - /* The offset of the rex prefix or -1 if not present. */ - int rex_offset; + /* The offset of the REX/VEX instruction encoding prefix or -1 if + not present. */ + int enc_prefix_offset; /* The offset to the first opcode byte. */ int opcode_offset; /* The offset to the modrm byte or -1 if not present. */ @@ -1014,22 +1117,23 @@ struct amd64_insn gdb_byte *raw_insn; }; -struct displaced_step_closure +struct amd64_displaced_step_copy_insn_closure + : public displaced_step_copy_insn_closure { + amd64_displaced_step_copy_insn_closure (int insn_buf_len) + : insn_buf (insn_buf_len, 0) + {} + /* For rip-relative insns, saved copy of the reg we use instead of %rip. */ - int tmp_used; + int tmp_used = 0; int tmp_regno; ULONGEST tmp_save; /* Details of the instruction. */ struct amd64_insn insn_details; - /* Amount of space allocated to insn_buf. */ - int max_len; - - /* The possibly modified insn. - This is a variable-length field. */ - gdb_byte insn_buf[1]; + /* The possibly modified insn. */ + gdb::byte_vector insn_buf; }; /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with @@ -1090,6 +1194,22 @@ rex_prefix_p (gdb_byte pfx) return REX_PREFIX_P (pfx); } +/* True if PFX is the start of the 2-byte VEX prefix. */ + +static bool +vex2_prefix_p (gdb_byte pfx) +{ + return pfx == 0xc5; +} + +/* True if PFX is the start of the 3-byte VEX prefix. */ + +static bool +vex3_prefix_p (gdb_byte pfx) +{ + return pfx == 0xc4; +} + /* Skip the legacy instruction prefixes in INSN. We assume INSN is properly sentineled so we don't have to worry about falling off the end of the buffer. */ @@ -1208,19 +1328,30 @@ amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details) details->raw_insn = insn; details->opcode_len = -1; - details->rex_offset = -1; + details->enc_prefix_offset = -1; details->opcode_offset = -1; details->modrm_offset = -1; /* Skip legacy instruction prefixes. */ insn = amd64_skip_prefixes (insn); - /* Skip REX instruction prefix. */ + /* Skip REX/VEX instruction encoding prefixes. */ if (rex_prefix_p (*insn)) { - details->rex_offset = insn - start; + details->enc_prefix_offset = insn - start; ++insn; } + else if (vex2_prefix_p (*insn)) + { + /* Don't record the offset in this case because this prefix has + no REX.B equivalent. */ + insn += 2; + } + else if (vex3_prefix_p (*insn)) + { + details->enc_prefix_offset = insn - start; + insn += 3; + } details->opcode_offset = insn - start; @@ -1270,15 +1401,14 @@ amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details) We set base = pc + insn_length so we can leave disp unchanged. */ static void -fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc, +fixup_riprel (struct gdbarch *gdbarch, + amd64_displaced_step_copy_insn_closure *dsc, CORE_ADDR from, CORE_ADDR to, struct regcache *regs) { - enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); const struct amd64_insn *insn_details = &dsc->insn_details; int modrm_offset = insn_details->modrm_offset; gdb_byte *insn = insn_details->raw_insn + modrm_offset; CORE_ADDR rip_base; - int32_t disp; int insn_length; int arch_tmp_regno, tmp_regno; ULONGEST orig_value; @@ -1287,9 +1417,8 @@ fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc, ++insn; /* Compute the rip-relative address. */ - disp = extract_signed_integer (insn, sizeof (int32_t), byte_order); - insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf, - dsc->max_len, from); + insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf.data (), + dsc->insn_buf.size (), from); rip_base = from + insn_length; /* We need a register to hold the address. @@ -1298,10 +1427,22 @@ fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc, arch_tmp_regno = amd64_get_unused_input_int_reg (insn_details); tmp_regno = amd64_arch_reg_to_regnum (arch_tmp_regno); - /* REX.B should be unset as we were using rip-relative addressing, - but ensure it's unset anyway, tmp_regno is not r8-r15. */ - if (insn_details->rex_offset != -1) - dsc->insn_buf[insn_details->rex_offset] &= ~REX_B; + /* Position of the not-B bit in the 3-byte VEX prefix (in byte 1). */ + static constexpr gdb_byte VEX3_NOT_B = 0x20; + + /* REX.B should be unset (VEX.!B set) as we were using rip-relative + addressing, but ensure it's unset (set for VEX) anyway, tmp_regno + is not r8-r15. */ + if (insn_details->enc_prefix_offset != -1) + { + gdb_byte *pfx = &dsc->insn_buf[insn_details->enc_prefix_offset]; + if (rex_prefix_p (pfx[0])) + pfx[0] &= ~REX_B; + else if (vex3_prefix_p (pfx[0])) + pfx[1] |= VEX3_NOT_B; + else + gdb_assert_not_reached ("unhandled prefix"); + } regcache_cooked_read_unsigned (regs, tmp_regno, &orig_value); dsc->tmp_regno = tmp_regno; @@ -1314,16 +1455,15 @@ fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc, regcache_cooked_write_unsigned (regs, tmp_regno, rip_base); - if (debug_displaced) - fprintf_unfiltered (gdb_stdlog, "displaced: %%rip-relative addressing used.\n" - "displaced: using temp reg %d, old value %s, new value %s\n", - dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save), - paddress (gdbarch, rip_base)); + displaced_debug_printf ("%%rip-relative addressing used."); + displaced_debug_printf ("using temp reg %d, old value %s, new value %s", + dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save), + paddress (gdbarch, rip_base)); } static void fixup_displaced_copy (struct gdbarch *gdbarch, - struct displaced_step_closure *dsc, + amd64_displaced_step_copy_insn_closure *dsc, CORE_ADDR from, CORE_ADDR to, struct regcache *regs) { const struct amd64_insn *details = &dsc->insn_details; @@ -1341,7 +1481,7 @@ fixup_displaced_copy (struct gdbarch *gdbarch, } } -struct displaced_step_closure * +displaced_step_copy_insn_closure_up amd64_displaced_step_copy_insn (struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to, struct regcache *regs) @@ -1350,14 +1490,11 @@ amd64_displaced_step_copy_insn (struct gdbarch *gdbarch, /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to continually watch for running off the end of the buffer. */ int fixup_sentinel_space = len; - struct displaced_step_closure *dsc = - xmalloc (sizeof (*dsc) + len + fixup_sentinel_space); + std::unique_ptr dsc + (new amd64_displaced_step_copy_insn_closure (len + fixup_sentinel_space)); gdb_byte *buf = &dsc->insn_buf[0]; struct amd64_insn *details = &dsc->insn_details; - dsc->tmp_used = 0; - dsc->max_len = len + fixup_sentinel_space; - read_memory (from, buf, len); /* Set up the sentinel space so we don't have to worry about running @@ -1379,18 +1516,16 @@ amd64_displaced_step_copy_insn (struct gdbarch *gdbarch, /* Modify the insn to cope with the address where it will be executed from. In particular, handle any rip-relative addressing. */ - fixup_displaced_copy (gdbarch, dsc, from, to, regs); + fixup_displaced_copy (gdbarch, dsc.get (), from, to, regs); write_memory (to, buf, len); - if (debug_displaced) - { - fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", - paddress (gdbarch, from), paddress (gdbarch, to)); - displaced_step_dump_bytes (gdb_stdlog, buf, len); - } + displaced_debug_printf ("copy %s->%s: %s", + paddress (gdbarch, from), paddress (gdbarch, to), + displaced_step_dump_bytes (buf, len).c_str ()); - return dsc; + /* This is a work around for a problem with g++ 4.8. */ + return displaced_step_copy_insn_closure_up (dsc.release ()); } static int @@ -1513,7 +1648,7 @@ amd64_classify_insn_at (struct gdbarch *gdbarch, CORE_ADDR addr, int len, classification; len = gdbarch_max_insn_length (gdbarch); - buf = alloca (len); + buf = (gdb_byte *) alloca (len); read_code (addr, buf, len); amd64_get_insn_details (buf, &details); @@ -1552,30 +1687,28 @@ amd64_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr) void amd64_displaced_step_fixup (struct gdbarch *gdbarch, - struct displaced_step_closure *dsc, + struct displaced_step_copy_insn_closure *dsc_, CORE_ADDR from, CORE_ADDR to, struct regcache *regs) { + amd64_displaced_step_copy_insn_closure *dsc + = (amd64_displaced_step_copy_insn_closure *) dsc_; enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); /* The offset we applied to the instruction's address. */ ULONGEST insn_offset = to - from; - gdb_byte *insn = dsc->insn_buf; + gdb_byte *insn = dsc->insn_buf.data (); const struct amd64_insn *insn_details = &dsc->insn_details; - if (debug_displaced) - fprintf_unfiltered (gdb_stdlog, - "displaced: fixup (%s, %s), " - "insn = 0x%02x 0x%02x ...\n", - paddress (gdbarch, from), paddress (gdbarch, to), - insn[0], insn[1]); + displaced_debug_printf ("fixup (%s, %s), insn = 0x%02x 0x%02x ...", + paddress (gdbarch, from), paddress (gdbarch, to), + insn[0], insn[1]); /* If we used a tmp reg, restore it. */ if (dsc->tmp_used) { - if (debug_displaced) - fprintf_unfiltered (gdb_stdlog, "displaced: restoring reg %d to %s\n", - dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save)); + displaced_debug_printf ("restoring reg %d to %s", + dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save)); regcache_cooked_write_unsigned (regs, dsc->tmp_regno, dsc->tmp_save); } @@ -1620,12 +1753,7 @@ amd64_displaced_step_fixup (struct gdbarch *gdbarch, Presumably this is a kernel bug. Fixup ensures its a nop, we add one to the length for it. */ && orig_rip != to + insn_len + 1) - { - if (debug_displaced) - fprintf_unfiltered (gdb_stdlog, - "displaced: syscall changed %%rip; " - "not relocating\n"); - } + displaced_debug_printf ("syscall changed %%rip; not relocating"); else { ULONGEST rip = orig_rip - insn_offset; @@ -1636,12 +1764,9 @@ amd64_displaced_step_fixup (struct gdbarch *gdbarch, regcache_cooked_write_unsigned (regs, AMD64_RIP_REGNUM, rip); - if (debug_displaced) - fprintf_unfiltered (gdb_stdlog, - "displaced: " - "relocated %%rip from %s to %s\n", - paddress (gdbarch, orig_rip), - paddress (gdbarch, rip)); + displaced_debug_printf ("relocated %%rip from %s to %s", + paddress (gdbarch, orig_rip), + paddress (gdbarch, rip)); } } @@ -1661,15 +1786,12 @@ amd64_displaced_step_fixup (struct gdbarch *gdbarch, regcache_cooked_read_unsigned (regs, AMD64_RSP_REGNUM, &rsp); retaddr = read_memory_unsigned_integer (rsp, retaddr_len, byte_order); - retaddr = (retaddr - insn_offset) & 0xffffffffUL; + retaddr = (retaddr - insn_offset) & 0xffffffffffffffffULL; write_memory_unsigned_integer (rsp, retaddr_len, byte_order, retaddr); - if (debug_displaced) - fprintf_unfiltered (gdb_stdlog, - "displaced: relocated return addr at %s " - "to %s\n", - paddress (gdbarch, rsp), - paddress (gdbarch, retaddr)); + displaced_debug_printf ("relocated return addr at %s to %s", + paddress (gdbarch, rsp), + paddress (gdbarch, retaddr)); } } @@ -1710,7 +1832,7 @@ amd64_relocate_instruction (struct gdbarch *gdbarch, int len = gdbarch_max_insn_length (gdbarch); /* Extra space for sentinels. */ int fixup_sentinel_space = len; - gdb_byte *buf = xmalloc (len + fixup_sentinel_space); + gdb_byte *buf = (gdb_byte *) xmalloc (len + fixup_sentinel_space); struct amd64_insn insn_details; int offset = 0; LONGEST rel32, newrel; @@ -1737,15 +1859,47 @@ amd64_relocate_instruction (struct gdbarch *gdbarch, the user program would return to. */ if (insn[0] == 0xe8) { - gdb_byte push_buf[16]; - unsigned int ret_addr; + gdb_byte push_buf[32]; + CORE_ADDR ret_addr; + int i = 0; /* Where "ret" in the original code will return to. */ ret_addr = oldloc + insn_length; - push_buf[0] = 0x68; /* pushq $... */ - store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr); + + /* If pushing an address higher than or equal to 0x80000000, + avoid 'pushq', as that sign extends its 32-bit operand, which + would be incorrect. */ + if (ret_addr <= 0x7fffffff) + { + push_buf[0] = 0x68; /* pushq $... */ + store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr); + i = 5; + } + else + { + push_buf[i++] = 0x48; /* sub $0x8,%rsp */ + push_buf[i++] = 0x83; + push_buf[i++] = 0xec; + push_buf[i++] = 0x08; + + push_buf[i++] = 0xc7; /* movl $imm,(%rsp) */ + push_buf[i++] = 0x04; + push_buf[i++] = 0x24; + store_unsigned_integer (&push_buf[i], 4, byte_order, + ret_addr & 0xffffffff); + i += 4; + + push_buf[i++] = 0xc7; /* movl $imm,4(%rsp) */ + push_buf[i++] = 0x44; + push_buf[i++] = 0x24; + push_buf[i++] = 0x04; + store_unsigned_integer (&push_buf[i], 4, byte_order, + ret_addr >> 32); + i += 4; + } + gdb_assert (i <= sizeof (push_buf)); /* Push the push. */ - append_insns (to, 5, push_buf); + append_insns (to, i, push_buf); /* Convert the relative call to a relative jump. */ insn[0] = 0xe9; @@ -1755,12 +1909,9 @@ amd64_relocate_instruction (struct gdbarch *gdbarch, newrel = (oldloc - *to) + rel32; store_signed_integer (insn + 1, 4, byte_order, newrel); - if (debug_displaced) - fprintf_unfiltered (gdb_stdlog, - "Adjusted insn rel32=%s at %s to" - " rel32=%s at %s\n", - hex_string (rel32), paddress (gdbarch, oldloc), - hex_string (newrel), paddress (gdbarch, *to)); + displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s", + hex_string (rel32), paddress (gdbarch, oldloc), + hex_string (newrel), paddress (gdbarch, *to)); /* Write the adjusted jump into its displaced location. */ append_insns (to, 5, insn); @@ -1784,12 +1935,9 @@ amd64_relocate_instruction (struct gdbarch *gdbarch, rel32 = extract_signed_integer (insn + offset, 4, byte_order); newrel = (oldloc - *to) + rel32; store_signed_integer (insn + offset, 4, byte_order, newrel); - if (debug_displaced) - fprintf_unfiltered (gdb_stdlog, - "Adjusted insn rel32=%s at %s to" - " rel32=%s at %s\n", - hex_string (rel32), paddress (gdbarch, oldloc), - hex_string (newrel), paddress (gdbarch, *to)); + displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s", + hex_string (rel32), paddress (gdbarch, oldloc), + hex_string (newrel), paddress (gdbarch, *to)); } /* Write the adjusted instruction into its displaced location. */ @@ -1884,8 +2032,8 @@ amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes: - 0x48 0x83 0xe4 0xf0 andq $-16, %rsp - 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp + 0x48 0x83 0xe4 0xf0 andq $-16, %rsp + 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp */ gdb_byte buf[18]; @@ -2008,7 +2156,7 @@ amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, if (current_pc > pc + offset_and) cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg); - return min (pc + offset + 2, current_pc); + return std::min (pc + offset + 2, current_pc); } /* Similar to amd64_analyze_stack_align for x32. */ @@ -2048,13 +2196,13 @@ amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes: - 0x48 0x83 0xe4 0xf0 andq $-16, %rsp - 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp + 0x48 0x83 0xe4 0xf0 andq $-16, %rsp + 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: - 0x83 0xe4 0xf0 andl $-16, %esp - 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp + 0x83 0xe4 0xf0 andl $-16, %esp + 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp */ gdb_byte buf[19]; @@ -2190,7 +2338,7 @@ amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, if (current_pc > pc + offset_and) cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg); - return min (pc + offset + 2, current_pc); + return std::min (pc + offset + 2, current_pc); } /* Do a limited analysis of the prologue at PC and update CACHE @@ -2207,6 +2355,9 @@ amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, pushq %rbp 0x55 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec) + The `endbr64` instruction can be found before these sequences, and will be + skipped if found. + Any function that doesn't start with one of these sequences will be assumed to have no prologue and thus no valid frame pointer in %rbp. */ @@ -2217,6 +2368,8 @@ amd64_analyze_prologue (struct gdbarch *gdbarch, struct amd64_frame_cache *cache) { enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); + /* The `endbr64` instruction. */ + static const gdb_byte endbr64[4] = { 0xf3, 0x0f, 0x1e, 0xfa }; /* There are two variations of movq %rsp, %rbp. */ static const gdb_byte mov_rsp_rbp_1[3] = { 0x48, 0x89, 0xe5 }; static const gdb_byte mov_rsp_rbp_2[3] = { 0x48, 0x8b, 0xec }; @@ -2237,16 +2390,30 @@ amd64_analyze_prologue (struct gdbarch *gdbarch, op = read_code_unsigned_integer (pc, 1, byte_order); + /* Check for the `endbr64` instruction, skip it if found. */ + if (op == endbr64[0]) + { + read_code (pc + 1, buf, 3); + + if (memcmp (buf, &endbr64[1], 3) == 0) + pc += 4; + + op = read_code_unsigned_integer (pc, 1, byte_order); + } + + if (current_pc <= pc) + return current_pc; + if (op == 0x55) /* pushq %rbp */ { /* Take into account that we've executed the `pushq %rbp' that - starts this instruction sequence. */ + starts this instruction sequence. */ cache->saved_regs[AMD64_RBP_REGNUM] = 0; cache->sp_offset += 8; /* If that's all, return now. */ if (current_pc <= pc + 1) - return current_pc; + return current_pc; read_code (pc + 1, buf, 3); @@ -2259,7 +2426,7 @@ amd64_analyze_prologue (struct gdbarch *gdbarch, return pc + 4; } - /* For X32, also check for `movq %esp, %ebp'. */ + /* For X32, also check for `movl %esp, %ebp'. */ if (gdbarch_ptr_bit (gdbarch) == 32) { if (memcmp (buf, mov_esp_ebp_1, 2) == 0 @@ -2307,8 +2474,8 @@ amd64_skip_xmm_prologue (CORE_ADDR pc, CORE_ADDR start_pc) start_pc_sal = find_pc_sect_line (start_pc, NULL, 0); if (start_pc_sal.symtab == NULL - || producer_is_gcc_ge_4 (COMPUNIT_PRODUCER - (SYMTAB_COMPUNIT (start_pc_sal.symtab))) < 6 + || producer_is_gcc_ge_4 (start_pc_sal.symtab->compunit () + ->producer ()) < 6 || start_pc_sal.pc != start_pc || pc >= start_pc_sal.end) return pc; @@ -2332,7 +2499,7 @@ amd64_skip_xmm_prologue (CORE_ADDR pc, CORE_ADDR start_pc) { /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */ if (buf[offset] != 0x0f || buf[offset + 1] != 0x29 - || (buf[offset + 2] & 0x3f) != (xmmreg << 3 | 0x5)) + || (buf[offset + 2] & 0x3f) != (xmmreg << 3 | 0x5)) return pc; /* 0b01?????? */ @@ -2373,13 +2540,15 @@ amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) = skip_prologue_using_sal (gdbarch, func_addr); struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr); - /* Clang always emits a line note before the prologue and another - one after. We trust clang to emit usable line notes. */ + /* LLVM backend (Clang/Flang) always emits a line note before the + prologue and another one after. We trust clang and newer Intel + compilers to emit usable line notes. */ if (post_prologue_pc && (cust != NULL - && COMPUNIT_PRODUCER (cust) != NULL - && startswith (COMPUNIT_PRODUCER (cust), "clang "))) - return max (start_pc, post_prologue_pc); + && cust->producer () != nullptr + && (producer_is_llvm (cust->producer ()) + || producer_is_icc_ge_19 (cust->producer ())))) + return std::max (start_pc, post_prologue_pc); } amd64_init_frame_cache (&cache); @@ -2466,21 +2635,23 @@ amd64_frame_cache_1 (struct frame_info *this_frame, static struct amd64_frame_cache * amd64_frame_cache (struct frame_info *this_frame, void **this_cache) { - volatile struct gdb_exception ex; struct amd64_frame_cache *cache; if (*this_cache) - return *this_cache; + return (struct amd64_frame_cache *) *this_cache; cache = amd64_alloc_frame_cache (); *this_cache = cache; - TRY_CATCH (ex, RETURN_MASK_ERROR) + try { amd64_frame_cache_1 (this_frame, cache); } - if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) - throw_exception (ex); + catch (const gdb_exception_error &ex) + { + if (ex.error != NOT_AVAILABLE_ERROR) + throw; + } return cache; } @@ -2542,6 +2713,7 @@ amd64_frame_prev_register (struct frame_info *this_frame, void **this_cache, static const struct frame_unwind amd64_frame_unwind = { + "amd64 prologue", NORMAL_FRAME, amd64_frame_unwind_stop_reason, amd64_frame_this_id, @@ -2577,20 +2749,19 @@ static struct amd64_frame_cache * amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) { struct gdbarch *gdbarch = get_frame_arch (this_frame); - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + i386_gdbarch_tdep *tdep = (i386_gdbarch_tdep *) gdbarch_tdep (gdbarch); enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); - volatile struct gdb_exception ex; struct amd64_frame_cache *cache; CORE_ADDR addr; gdb_byte buf[8]; int i; if (*this_cache) - return *this_cache; + return (struct amd64_frame_cache *) *this_cache; cache = amd64_alloc_frame_cache (); - TRY_CATCH (ex, RETURN_MASK_ERROR) + try { get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); cache->base = extract_unsigned_integer (buf, 8, byte_order) - 8; @@ -2604,8 +2775,11 @@ amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) cache->base_p = 1; } - if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) - throw_exception (ex); + catch (const gdb_exception_error &ex) + { + if (ex.error != NOT_AVAILABLE_ERROR) + throw; + } *this_cache = cache; return cache; @@ -2657,7 +2831,8 @@ amd64_sigtramp_frame_sniffer (const struct frame_unwind *self, struct frame_info *this_frame, void **this_cache) { - struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); + gdbarch *arch = get_frame_arch (this_frame); + i386_gdbarch_tdep *tdep = (i386_gdbarch_tdep *) gdbarch_tdep (arch); /* We shouldn't even bother if we don't have a sigcontext_addr handler. */ @@ -2684,6 +2859,7 @@ amd64_sigtramp_frame_sniffer (const struct frame_unwind *self, static const struct frame_unwind amd64_sigtramp_frame_unwind = { + "amd64 sigtramp", SIGTRAMP_FRAME, amd64_sigtramp_frame_unwind_stop_reason, amd64_sigtramp_frame_this_id, @@ -2712,18 +2888,20 @@ static const struct frame_base amd64_frame_base = /* Normal frames, but in a function epilogue. */ -/* The epilogue is defined here as the 'ret' instruction, which will +/* Implement the stack_frame_destroyed_p gdbarch method. + + The epilogue is defined here as the 'ret' instruction, which will follow any instruction such as 'leave' or 'pop %ebp' that destroys the function's stack frame. */ static int -amd64_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) +amd64_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) { gdb_byte insn; struct compunit_symtab *cust; cust = find_pc_compunit_symtab (pc); - if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust)) + if (cust != NULL && cust->epilogue_unwind_valid ()) return 0; if (target_read_memory (pc, &insn, 1)) @@ -2741,8 +2919,8 @@ amd64_epilogue_frame_sniffer (const struct frame_unwind *self, void **this_prologue_cache) { if (frame_relative_level (this_frame) == 0) - return amd64_in_function_epilogue_p (get_frame_arch (this_frame), - get_frame_pc (this_frame)); + return amd64_stack_frame_destroyed_p (get_frame_arch (this_frame), + get_frame_pc (this_frame)); else return 0; } @@ -2752,17 +2930,16 @@ amd64_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) { struct gdbarch *gdbarch = get_frame_arch (this_frame); enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); - volatile struct gdb_exception ex; struct amd64_frame_cache *cache; gdb_byte buf[8]; if (*this_cache) - return *this_cache; + return (struct amd64_frame_cache *) *this_cache; cache = amd64_alloc_frame_cache (); *this_cache = cache; - TRY_CATCH (ex, RETURN_MASK_ERROR) + try { /* Cache base will be %esp plus cache->sp_offset (-8). */ get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); @@ -2780,8 +2957,11 @@ amd64_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) cache->base_p = 1; } - if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) - throw_exception (ex); + catch (const gdb_exception_error &ex) + { + if (ex.error != NOT_AVAILABLE_ERROR) + throw; + } return cache; } @@ -2815,6 +2995,7 @@ amd64_epilogue_frame_this_id (struct frame_info *this_frame, static const struct frame_unwind amd64_epilogue_frame_unwind = { + "amd64 epilogue", NORMAL_FRAME, amd64_epilogue_frame_unwind_stop_reason, amd64_epilogue_frame_this_id, @@ -2850,8 +3031,8 @@ static void amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache, int regnum, const void *fpregs, size_t len) { - struct gdbarch *gdbarch = get_regcache_arch (regcache); - const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + struct gdbarch *gdbarch = regcache->arch (); + const i386_gdbarch_tdep *tdep = (i386_gdbarch_tdep *) gdbarch_tdep (gdbarch); gdb_assert (len >= tdep->sizeof_fpregset); amd64_supply_fxsave (regcache, regnum, fpregs); @@ -2867,8 +3048,8 @@ amd64_collect_fpregset (const struct regset *regset, const struct regcache *regcache, int regnum, void *fpregs, size_t len) { - struct gdbarch *gdbarch = get_regcache_arch (regcache); - const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + struct gdbarch *gdbarch = regcache->arch (); + const i386_gdbarch_tdep *tdep = (i386_gdbarch_tdep *) gdbarch_tdep (gdbarch); gdb_assert (len >= tdep->sizeof_fpregset); amd64_collect_fxsave (regcache, regnum, fpregs); @@ -2892,7 +3073,8 @@ amd64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) gdb_byte buf[8]; CORE_ADDR jb_addr; struct gdbarch *gdbarch = get_frame_arch (frame); - int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; + i386_gdbarch_tdep *tdep = (i386_gdbarch_tdep *) gdbarch_tdep (gdbarch); + int jb_pc_offset = tdep->jb_pc_offset; int len = TYPE_LENGTH (builtin_type (gdbarch)->builtin_func_ptr); /* If JB_PC_OFFSET is -1, we have no way to find out where the @@ -2921,10 +3103,21 @@ static const int amd64_record_regmap[] = AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM }; +/* Implement the "in_indirect_branch_thunk" gdbarch function. */ + +static bool +amd64_in_indirect_branch_thunk (struct gdbarch *gdbarch, CORE_ADDR pc) +{ + return x86_in_indirect_branch_thunk (pc, amd64_register_names, + AMD64_RAX_REGNUM, + AMD64_RIP_REGNUM); +} + void -amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) +amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch, + const target_desc *default_tdesc) { - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + i386_gdbarch_tdep *tdep = (i386_gdbarch_tdep *) gdbarch_tdep (gdbarch); const struct target_desc *tdesc = info.target_desc; static const char *const stap_integer_prefixes[] = { "$", NULL }; static const char *const stap_register_prefixes[] = { "%", NULL }; @@ -2939,7 +3132,7 @@ amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) tdep->fpregset = &amd64_fpregset; if (! tdesc_has_registers (tdesc)) - tdesc = tdesc_amd64; + tdesc = default_tdesc; tdep->tdesc = tdesc; tdep->num_core_regs = AMD64_NUM_GREGS + I387_NUM_REGS; @@ -2976,6 +3169,18 @@ amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) tdep->bnd0r_regnum = AMD64_BND0R_REGNUM; } + if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.segments") != NULL) + { + tdep->fsbase_regnum = AMD64_FSBASE_REGNUM; + } + + if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.pkeys") != NULL) + { + tdep->pkeys_register_names = amd64_pkeys_names; + tdep->pkru_regnum = AMD64_PKRU_REGNUM; + tdep->num_pkeys_regs = 1; + } + tdep->num_byte_regs = 20; tdep->num_word_regs = 16; tdep->num_dword_regs = 16; @@ -2986,6 +3191,8 @@ amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) amd64_pseudo_register_read_value); set_gdbarch_pseudo_register_write (gdbarch, amd64_pseudo_register_write); + set_gdbarch_ax_pseudo_register_collect (gdbarch, + amd64_ax_pseudo_register_collect); set_tdesc_pseudo_register_name (gdbarch, amd64_pseudo_register_name); @@ -3070,13 +3277,26 @@ amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) set_gdbarch_insn_is_call (gdbarch, amd64_insn_is_call); set_gdbarch_insn_is_ret (gdbarch, amd64_insn_is_ret); set_gdbarch_insn_is_jump (gdbarch, amd64_insn_is_jump); + + set_gdbarch_in_indirect_branch_thunk (gdbarch, + amd64_in_indirect_branch_thunk); + + register_amd64_ravenscar_ops (gdbarch); +} + +/* Initialize ARCH for x86-64, no osabi. */ + +static void +amd64_none_init_abi (gdbarch_info info, gdbarch *arch) +{ + amd64_init_abi (info, arch, amd64_target_description (X86_XSTATE_SSE_MASK, + true)); } - static struct type * amd64_x32_pseudo_register_type (struct gdbarch *gdbarch, int regnum) { - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + i386_gdbarch_tdep *tdep = (i386_gdbarch_tdep *) gdbarch_tdep (gdbarch); switch (regnum - tdep->eax_regnum) { @@ -3091,16 +3311,12 @@ amd64_x32_pseudo_register_type (struct gdbarch *gdbarch, int regnum) } void -amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) +amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch, + const target_desc *default_tdesc) { - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - const struct target_desc *tdesc = info.target_desc; + i386_gdbarch_tdep *tdep = (i386_gdbarch_tdep *) gdbarch_tdep (gdbarch); - amd64_init_abi (info, gdbarch); - - if (! tdesc_has_registers (tdesc)) - tdesc = tdesc_x32; - tdep->tdesc = tdesc; + amd64_init_abi (info, gdbarch, default_tdesc); tdep->num_dword_regs = 17; set_tdesc_pseudo_register_type (gdbarch, amd64_x32_pseudo_register_type); @@ -3109,20 +3325,45 @@ amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) set_gdbarch_ptr_bit (gdbarch, 32); } -/* Provide a prototype to silence -Wmissing-prototypes. */ -void _initialize_amd64_tdep (void); +/* Initialize ARCH for x64-32, no osabi. */ -void -_initialize_amd64_tdep (void) +static void +amd64_x32_none_init_abi (gdbarch_info info, gdbarch *arch) { - initialize_tdesc_amd64 (); - initialize_tdesc_amd64_avx (); - initialize_tdesc_amd64_mpx (); - initialize_tdesc_amd64_avx512 (); + amd64_x32_init_abi (info, arch, + amd64_target_description (X86_XSTATE_SSE_MASK, true)); +} + +/* Return the target description for a specified XSAVE feature mask. */ + +const struct target_desc * +amd64_target_description (uint64_t xcr0, bool segments) +{ + static target_desc *amd64_tdescs \ + [2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/][2/*segments*/] = {}; + target_desc **tdesc; + + tdesc = &amd64_tdescs[(xcr0 & X86_XSTATE_AVX) ? 1 : 0] + [(xcr0 & X86_XSTATE_MPX) ? 1 : 0] + [(xcr0 & X86_XSTATE_AVX512) ? 1 : 0] + [(xcr0 & X86_XSTATE_PKRU) ? 1 : 0] + [segments ? 1 : 0]; + + if (*tdesc == NULL) + *tdesc = amd64_create_target_description (xcr0, false, false, + segments); - initialize_tdesc_x32 (); - initialize_tdesc_x32_avx (); - initialize_tdesc_x32_avx512 (); + return *tdesc; +} + +void _initialize_amd64_tdep (); +void +_initialize_amd64_tdep () +{ + gdbarch_register_osabi (bfd_arch_i386, bfd_mach_x86_64, GDB_OSABI_NONE, + amd64_none_init_abi); + gdbarch_register_osabi (bfd_arch_i386, bfd_mach_x64_32, GDB_OSABI_NONE, + amd64_x32_none_init_abi); } @@ -3142,20 +3383,20 @@ void amd64_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave) { - struct gdbarch *gdbarch = get_regcache_arch (regcache); - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + struct gdbarch *gdbarch = regcache->arch (); + i386_gdbarch_tdep *tdep = (i386_gdbarch_tdep *) gdbarch_tdep (gdbarch); i387_supply_fxsave (regcache, regnum, fxsave); if (fxsave && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) { - const gdb_byte *regs = fxsave; + const gdb_byte *regs = (const gdb_byte *) fxsave; if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) - regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), regs + 12); + regcache->raw_supply (I387_FISEG_REGNUM (tdep), regs + 12); if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) - regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), regs + 20); + regcache->raw_supply (I387_FOSEG_REGNUM (tdep), regs + 20); } } @@ -3165,22 +3406,29 @@ void amd64_supply_xsave (struct regcache *regcache, int regnum, const void *xsave) { - struct gdbarch *gdbarch = get_regcache_arch (regcache); - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + struct gdbarch *gdbarch = regcache->arch (); + i386_gdbarch_tdep *tdep = (i386_gdbarch_tdep *) gdbarch_tdep (gdbarch); i387_supply_xsave (regcache, regnum, xsave); if (xsave && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) { - const gdb_byte *regs = xsave; + const gdb_byte *regs = (const gdb_byte *) xsave; + ULONGEST clear_bv; - if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) - regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), - regs + 12); - if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) - regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), - regs + 20); + clear_bv = i387_xsave_get_clear_bv (gdbarch, xsave); + + /* If the FISEG and FOSEG registers have not been initialised yet + (their CLEAR_BV bit is set) then their default values of zero will + have already been setup by I387_SUPPLY_XSAVE. */ + if (!(clear_bv & X86_XSTATE_X87)) + { + if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) + regcache->raw_supply (I387_FISEG_REGNUM (tdep), regs + 12); + if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) + regcache->raw_supply (I387_FOSEG_REGNUM (tdep), regs + 20); + } } } @@ -3193,18 +3441,18 @@ void amd64_collect_fxsave (const struct regcache *regcache, int regnum, void *fxsave) { - struct gdbarch *gdbarch = get_regcache_arch (regcache); - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - gdb_byte *regs = fxsave; + struct gdbarch *gdbarch = regcache->arch (); + i386_gdbarch_tdep *tdep = (i386_gdbarch_tdep *) gdbarch_tdep (gdbarch); + gdb_byte *regs = (gdb_byte *) fxsave; i387_collect_fxsave (regcache, regnum, fxsave); if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) { if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) - regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), regs + 12); + regcache->raw_collect (I387_FISEG_REGNUM (tdep), regs + 12); if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) - regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), regs + 20); + regcache->raw_collect (I387_FOSEG_REGNUM (tdep), regs + 20); } } @@ -3214,19 +3462,19 @@ void amd64_collect_xsave (const struct regcache *regcache, int regnum, void *xsave, int gcore) { - struct gdbarch *gdbarch = get_regcache_arch (regcache); - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - gdb_byte *regs = xsave; + struct gdbarch *gdbarch = regcache->arch (); + i386_gdbarch_tdep *tdep = (i386_gdbarch_tdep *) gdbarch_tdep (gdbarch); + gdb_byte *regs = (gdb_byte *) xsave; i387_collect_xsave (regcache, regnum, xsave, gcore); if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) { if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) - regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), + regcache->raw_collect (I387_FISEG_REGNUM (tdep), regs + 12); if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) - regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), + regcache->raw_collect (I387_FOSEG_REGNUM (tdep), regs + 20); } }