X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=gdb%2Farm-tdep.h;h=629c3b8ac685f411fe7eba45eb37ded3ea9d2a82;hb=a51951c25813b8d6c763f51d78d3756d9ca85ee1;hp=faa543e1c4f1ce13b4f9c9060ddfdbb13a5e71fe;hpb=618f726fcb851883a0094aa7fa17003889b7189f;p=binutils-gdb.git diff --git a/gdb/arm-tdep.h b/gdb/arm-tdep.h index faa543e1c4f..629c3b8ac68 100644 --- a/gdb/arm-tdep.h +++ b/gdb/arm-tdep.h @@ -1,5 +1,5 @@ /* Common target dependent code for GDB on ARM systems. - Copyright (C) 2002-2016 Free Software Foundation, Inc. + Copyright (C) 2002-2020 Free Software Foundation, Inc. This file is part of GDB. @@ -20,23 +20,21 @@ #define ARM_TDEP_H /* Forward declarations. */ -struct gdbarch; struct regset; struct address_space; struct get_next_pcs; struct arm_get_next_pcs; struct gdb_get_next_pcs; -#include "arch/arm.h" +/* Set to true if the 32-bit mode is in use. */ + +extern bool arm_apcs_32; -/* Say how long FP registers are. Used for documentation purposes and - code readability in this header. IEEE extended doubles are 80 - bits. DWORD aligned they use 96 bits. */ -#define FP_REGISTER_SIZE 12 +#include "gdbarch.h" +#include "arch/arm.h" +#include "infrun.h" -/* Say how long VFP double precision registers are. Used for documentation - purposes and code readability. These are fixed at 64 bits. */ -#define VFP_REGISTER_SIZE 8 +#include /* Number of machine registers. The only define actually required is gdbarch_num_regs. The other definitions are used for documentation @@ -97,19 +95,19 @@ struct gdbarch_tdep enum arm_float_model fp_model; /* Floating point calling conventions. */ - int have_fpa_registers; /* Does the target report the FPA registers? */ - int have_wmmx_registers; /* Does the target report the WMMX registers? */ + bool have_fpa_registers; /* Does the target report the FPA registers? */ + bool have_wmmx_registers; /* Does the target report the WMMX registers? */ /* The number of VFP registers reported by the target. It is zero if VFP registers are not supported. */ int vfp_register_count; - int have_vfp_pseudos; /* Are we synthesizing the single precision + bool have_vfp_pseudos; /* Are we synthesizing the single precision VFP registers? */ - int have_neon_pseudos; /* Are we synthesizing the quad precision + bool have_neon_pseudos; /* Are we synthesizing the quad precision NEON registers? Requires have_vfp_pseudos. */ - int have_neon; /* Do we have a NEON unit? */ + bool have_neon; /* Do we have a NEON unit? */ - int is_m; /* Does the target follow the "M" profile. */ + bool is_m; /* Does the target follow the "M" profile. */ CORE_ADDR lowest_pc; /* Lowest address at which instructions will appear. */ @@ -138,10 +136,6 @@ struct gdbarch_tdep struct type *neon_double_type; struct type *neon_quad_type; - /* Return the expected next PC if the program is stopped at a syscall - instruction. */ - CORE_ADDR (*syscall_next_pc) (struct regcache *regcache); - /* syscall record. */ int (*arm_syscall_record) (struct regcache *regcache, unsigned long svc_number); }; @@ -153,9 +147,9 @@ struct gdbarch_tdep /* The maximum number of modified instructions generated for one single-stepped instruction, including the breakpoint (usually at the end of the instruction sequence) and any scratch words, etc. */ -#define DISPLACED_MODIFIED_INSNS 8 +#define ARM_DISPLACED_MODIFIED_INSNS 8 -struct displaced_step_closure +struct arm_displaced_step_closure : public displaced_step_closure { ULONGEST tmp[DISPLACED_TEMPS]; int rd; @@ -202,7 +196,7 @@ struct displaced_step_closure /* If non-NULL, override generic SVC handling (e.g. for a particular OS). */ int (*copy_svc_os) (struct gdbarch *gdbarch, struct regcache *regs, - struct displaced_step_closure *dsc); + arm_displaced_step_closure *dsc); } svc; } u; @@ -216,12 +210,12 @@ struct displaced_step_closure - ARM instruction occupies one slot, - Thumb 16 bit instruction occupies one slot, - Thumb 32-bit instruction occupies *two* slots, one part for each. */ - unsigned long modinsn[DISPLACED_MODIFIED_INSNS]; + unsigned long modinsn[ARM_DISPLACED_MODIFIED_INSNS]; int numinsns; CORE_ADDR insn_addr; CORE_ADDR scratch_base; void (*cleanup) (struct gdbarch *, struct regcache *, - struct displaced_step_closure *); + arm_displaced_step_closure *); }; /* Values for the WRITE_PC argument to displaced_write_reg. If the register @@ -240,16 +234,16 @@ enum pc_write_style extern void arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to, struct regcache *regs, - struct displaced_step_closure *dsc); + arm_displaced_step_closure *dsc); extern void arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from, - CORE_ADDR to, struct displaced_step_closure *dsc); + CORE_ADDR to, arm_displaced_step_closure *dsc); extern ULONGEST - displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc, + displaced_read_reg (struct regcache *regs, arm_displaced_step_closure *dsc, int regno); extern void displaced_write_reg (struct regcache *regs, - struct displaced_step_closure *dsc, int regno, + arm_displaced_step_closure *dsc, int regno, ULONGEST val, enum pc_write_style write_pc); CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR); @@ -261,20 +255,12 @@ ULONGEST arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, CORE_ADDR arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self, CORE_ADDR val); -CORE_ADDR arm_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self, - CORE_ADDR pc); - int arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self); -void arm_insert_single_step_breakpoint (struct gdbarch *, - struct address_space *, CORE_ADDR); -int arm_software_single_step (struct frame_info *); +std::vector arm_software_single_step (struct regcache *); int arm_is_thumb (struct regcache *regcache); int arm_frame_is_thumb (struct frame_info *frame); -extern struct displaced_step_closure * - arm_displaced_step_copy_insn (struct gdbarch *, CORE_ADDR, CORE_ADDR, - struct regcache *); extern void arm_displaced_step_fixup (struct gdbarch *, struct displaced_step_closure *, CORE_ADDR, CORE_ADDR, struct regcache *); @@ -288,7 +274,7 @@ extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR); extern int arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache, CORE_ADDR addr); -/* Functions exported from armbsd-tdep.h. */ +/* Functions exported from arm-bsd-tdep.h. */ /* Return the appropriate register set for the core section identified by SECT_NAME and SECT_SIZE. */ @@ -299,11 +285,11 @@ extern void void *cb_data, const struct regcache *regcache); -/* Target descriptions. */ -extern struct target_desc *tdesc_arm_with_m; -extern struct target_desc *tdesc_arm_with_iwmmxt; -extern struct target_desc *tdesc_arm_with_vfpv2; -extern struct target_desc *tdesc_arm_with_vfpv3; -extern struct target_desc *tdesc_arm_with_neon; +/* Get the correct Arm target description with given FP hardware type. */ +const target_desc *arm_read_description (arm_fp_type fp_type); + +/* Get the correct Arm M-Profile target description with given hardware + type. */ +const target_desc *arm_read_mprofile_description (arm_m_profile_type m_type); #endif /* arm-tdep.h */