X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=gdb%2Farm-tdep.h;h=a8d21c44ba414b0da7d19dc081d028e0a81209e8;hb=48680a5f9d8ec2fcfa349ff2006a21b3b788b959;hp=705aa77a0ed65f4f6f008152e8fdf2b12f8759a4;hpb=ae66a8f19ef6bf2dc7369cf26073f34ddf7c175b;p=binutils-gdb.git diff --git a/gdb/arm-tdep.h b/gdb/arm-tdep.h index 705aa77a0ed..a8d21c44ba4 100644 --- a/gdb/arm-tdep.h +++ b/gdb/arm-tdep.h @@ -1,5 +1,5 @@ /* Common target dependent code for GDB on ARM systems. - Copyright (C) 2002-2021 Free Software Foundation, Inc. + Copyright (C) 2002-2023 Free Software Foundation, Inc. This file is part of GDB. @@ -87,69 +87,88 @@ enum struct_return }; /* Target-dependent structure in gdbarch. */ -struct gdbarch_tdep +struct arm_gdbarch_tdep : gdbarch_tdep_base { /* The ABI for this architecture. It should never be set to ARM_ABI_AUTO. */ - enum arm_abi_kind arm_abi; + enum arm_abi_kind arm_abi {}; - enum arm_float_model fp_model; /* Floating point calling conventions. */ + enum arm_float_model fp_model {}; /* Floating point calling conventions. */ - bool have_fpa_registers; /* Does the target report the FPA registers? */ - bool have_wmmx_registers; /* Does the target report the WMMX registers? */ + bool have_fpa_registers = false; /* Does the target report the FPA registers? */ + bool have_wmmx_registers = false; /* Does the target report the WMMX registers? */ /* The number of VFP registers reported by the target. It is zero if VFP registers are not supported. */ - int vfp_register_count; - bool have_s_pseudos; /* Are we synthesizing the single precision + int vfp_register_count = 0; + bool have_s_pseudos = false; /* Are we synthesizing the single precision VFP registers? */ - int s_pseudo_base; /* Register number for the first S pseudo + int s_pseudo_base = 0; /* Register number for the first S pseudo register. */ - int s_pseudo_count; /* Number of S pseudo registers. */ - bool have_q_pseudos; /* Are we synthesizing the quad precision + int s_pseudo_count = 0; /* Number of S pseudo registers. */ + bool have_q_pseudos = false; /* Are we synthesizing the quad precision Q (NEON or MVE) registers? Requires have_s_pseudos. */ - int q_pseudo_base; /* Register number for the first quad + int q_pseudo_base = 0; /* Register number for the first quad precision pseudo register. */ - int q_pseudo_count; /* Number of quad precision pseudo + int q_pseudo_count = 0; /* Number of quad precision pseudo registers. */ - bool have_neon; /* Do we have a NEON unit? */ + bool have_neon = false; /* Do we have a NEON unit? */ - bool have_mve; /* Do we have a MVE extension? */ - int mve_vpr_regnum; /* MVE VPR register number. */ - int mve_pseudo_base; /* Number of the first MVE pseudo register. */ - int mve_pseudo_count; /* Total number of MVE pseudo registers. */ + bool have_mve = false; /* Do we have a MVE extension? */ + int mve_vpr_regnum = 0; /* MVE VPR register number. */ + int mve_pseudo_base = 0; /* Number of the first MVE pseudo register. */ + int mve_pseudo_count = 0; /* Total number of MVE pseudo registers. */ - bool is_m; /* Does the target follow the "M" profile. */ - CORE_ADDR lowest_pc; /* Lowest address at which instructions + bool have_pacbti = false; /* True if we have the ARMv8.1-m PACBTI + extensions. */ + int pacbti_pseudo_base = 0; /* Number of the first PACBTI pseudo + register. */ + int pacbti_pseudo_count = 0; /* Total number of PACBTI pseudo registers. */ + + int m_profile_msp_regnum = ARM_SP_REGNUM; /* M-profile MSP register number. */ + int m_profile_psp_regnum = ARM_SP_REGNUM; /* M-profile PSP register number. */ + + /* Secure and Non-secure stack pointers with security extension. */ + int m_profile_msp_ns_regnum = ARM_SP_REGNUM; /* M-profile MSP_NS register number. */ + int m_profile_psp_ns_regnum = ARM_SP_REGNUM; /* M-profile PSP_NS register number. */ + int m_profile_msp_s_regnum = ARM_SP_REGNUM; /* M-profile MSP_S register number. */ + int m_profile_psp_s_regnum = ARM_SP_REGNUM; /* M-profile PSP_S register number. */ + + int tls_regnum = 0; /* Number of the tpidruro register. */ + + bool is_m = false; /* Does the target follow the "M" profile. */ + bool have_sec_ext = false; /* Do we have security extensions? */ + CORE_ADDR lowest_pc = 0; /* Lowest address at which instructions will appear. */ - const gdb_byte *arm_breakpoint; /* Breakpoint pattern for an ARM insn. */ - int arm_breakpoint_size; /* And its size. */ - const gdb_byte *thumb_breakpoint; /* Breakpoint pattern for a Thumb insn. */ - int thumb_breakpoint_size; /* And its size. */ + const gdb_byte *arm_breakpoint = nullptr; /* Breakpoint pattern for an ARM insn. */ + int arm_breakpoint_size = 0; /* And its size. */ + const gdb_byte *thumb_breakpoint = nullptr; /* Breakpoint pattern for a Thumb insn. */ + int thumb_breakpoint_size = 0; /* And its size. */ /* If the Thumb breakpoint is an undefined instruction (which is affected by IT blocks) rather than a BKPT instruction (which is not), then we need a 32-bit Thumb breakpoint to preserve the instruction count in IT blocks. */ - const gdb_byte *thumb2_breakpoint; - int thumb2_breakpoint_size; + const gdb_byte *thumb2_breakpoint = nullptr; + int thumb2_breakpoint_size = 0; - int jb_pc; /* Offset to PC value in jump buffer. + int jb_pc = 0; /* Offset to PC value in jump buffer. If this is negative, longjmp support will be disabled. */ - size_t jb_elt_size; /* And the size of each entry in the buf. */ + size_t jb_elt_size = 0; /* And the size of each entry in the buf. */ /* Convention for returning structures. */ - enum struct_return struct_return; + enum struct_return struct_return {}; /* ISA-specific data types. */ - struct type *arm_ext_type; - struct type *neon_double_type; - struct type *neon_quad_type; + struct type *arm_ext_type = nullptr; + struct type *neon_double_type = nullptr; + struct type *neon_quad_type = nullptr; /* syscall record. */ - int (*arm_syscall_record) (struct regcache *regcache, unsigned long svc_number); + int (*arm_syscall_record) (struct regcache *regcache, + unsigned long svc_number) = nullptr; }; /* Structures used for displaced stepping. */ @@ -260,7 +279,7 @@ extern void arm_displaced_step_copy_insn_closure *dsc, int regno, ULONGEST val, enum pc_write_style write_pc); -CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR); +CORE_ADDR arm_skip_stub (frame_info_ptr, CORE_ADDR); ULONGEST arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, int len, @@ -273,7 +292,7 @@ int arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self); std::vector arm_software_single_step (struct regcache *); int arm_is_thumb (struct regcache *regcache); -int arm_frame_is_thumb (struct frame_info *frame); +int arm_frame_is_thumb (frame_info_ptr frame); extern void arm_displaced_step_fixup (struct gdbarch *, displaced_step_copy_insn_closure *, @@ -300,7 +319,7 @@ extern void const struct regcache *regcache); /* Get the correct Arm target description with given FP hardware type. */ -const target_desc *arm_read_description (arm_fp_type fp_type); +const target_desc *arm_read_description (arm_fp_type fp_type, bool tls); /* Get the correct Arm M-Profile target description with given hardware type. */