X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=gdb%2Farm-tdep.h;h=a8d21c44ba414b0da7d19dc081d028e0a81209e8;hb=48680a5f9d8ec2fcfa349ff2006a21b3b788b959;hp=807849a5ffcac0627a5c945fbd59197e3260dbcd;hpb=f0452268d6c7296106aba81f532b04dc08187352;p=binutils-gdb.git diff --git a/gdb/arm-tdep.h b/gdb/arm-tdep.h index 807849a5ffc..a8d21c44ba4 100644 --- a/gdb/arm-tdep.h +++ b/gdb/arm-tdep.h @@ -1,5 +1,5 @@ /* Common target dependent code for GDB on ARM systems. - Copyright (C) 2002-2019 Free Software Foundation, Inc. + Copyright (C) 2002-2023 Free Software Foundation, Inc. This file is part of GDB. @@ -20,13 +20,17 @@ #define ARM_TDEP_H /* Forward declarations. */ -struct gdbarch; struct regset; struct address_space; struct get_next_pcs; struct arm_get_next_pcs; struct gdb_get_next_pcs; +/* Set to true if the 32-bit mode is in use. */ + +extern bool arm_apcs_32; + +#include "gdbarch.h" #include "arch/arm.h" #include "infrun.h" @@ -83,57 +87,88 @@ enum struct_return }; /* Target-dependent structure in gdbarch. */ -struct gdbarch_tdep +struct arm_gdbarch_tdep : gdbarch_tdep_base { /* The ABI for this architecture. It should never be set to ARM_ABI_AUTO. */ - enum arm_abi_kind arm_abi; + enum arm_abi_kind arm_abi {}; - enum arm_float_model fp_model; /* Floating point calling conventions. */ + enum arm_float_model fp_model {}; /* Floating point calling conventions. */ - int have_fpa_registers; /* Does the target report the FPA registers? */ - int have_wmmx_registers; /* Does the target report the WMMX registers? */ + bool have_fpa_registers = false; /* Does the target report the FPA registers? */ + bool have_wmmx_registers = false; /* Does the target report the WMMX registers? */ /* The number of VFP registers reported by the target. It is zero if VFP registers are not supported. */ - int vfp_register_count; - int have_vfp_pseudos; /* Are we synthesizing the single precision + int vfp_register_count = 0; + bool have_s_pseudos = false; /* Are we synthesizing the single precision VFP registers? */ - int have_neon_pseudos; /* Are we synthesizing the quad precision - NEON registers? Requires - have_vfp_pseudos. */ - int have_neon; /* Do we have a NEON unit? */ - - int is_m; /* Does the target follow the "M" profile. */ - CORE_ADDR lowest_pc; /* Lowest address at which instructions + int s_pseudo_base = 0; /* Register number for the first S pseudo + register. */ + int s_pseudo_count = 0; /* Number of S pseudo registers. */ + bool have_q_pseudos = false; /* Are we synthesizing the quad precision + Q (NEON or MVE) registers? Requires + have_s_pseudos. */ + int q_pseudo_base = 0; /* Register number for the first quad + precision pseudo register. */ + int q_pseudo_count = 0; /* Number of quad precision pseudo + registers. */ + bool have_neon = false; /* Do we have a NEON unit? */ + + bool have_mve = false; /* Do we have a MVE extension? */ + int mve_vpr_regnum = 0; /* MVE VPR register number. */ + int mve_pseudo_base = 0; /* Number of the first MVE pseudo register. */ + int mve_pseudo_count = 0; /* Total number of MVE pseudo registers. */ + + bool have_pacbti = false; /* True if we have the ARMv8.1-m PACBTI + extensions. */ + int pacbti_pseudo_base = 0; /* Number of the first PACBTI pseudo + register. */ + int pacbti_pseudo_count = 0; /* Total number of PACBTI pseudo registers. */ + + int m_profile_msp_regnum = ARM_SP_REGNUM; /* M-profile MSP register number. */ + int m_profile_psp_regnum = ARM_SP_REGNUM; /* M-profile PSP register number. */ + + /* Secure and Non-secure stack pointers with security extension. */ + int m_profile_msp_ns_regnum = ARM_SP_REGNUM; /* M-profile MSP_NS register number. */ + int m_profile_psp_ns_regnum = ARM_SP_REGNUM; /* M-profile PSP_NS register number. */ + int m_profile_msp_s_regnum = ARM_SP_REGNUM; /* M-profile MSP_S register number. */ + int m_profile_psp_s_regnum = ARM_SP_REGNUM; /* M-profile PSP_S register number. */ + + int tls_regnum = 0; /* Number of the tpidruro register. */ + + bool is_m = false; /* Does the target follow the "M" profile. */ + bool have_sec_ext = false; /* Do we have security extensions? */ + CORE_ADDR lowest_pc = 0; /* Lowest address at which instructions will appear. */ - const gdb_byte *arm_breakpoint; /* Breakpoint pattern for an ARM insn. */ - int arm_breakpoint_size; /* And its size. */ - const gdb_byte *thumb_breakpoint; /* Breakpoint pattern for a Thumb insn. */ - int thumb_breakpoint_size; /* And its size. */ + const gdb_byte *arm_breakpoint = nullptr; /* Breakpoint pattern for an ARM insn. */ + int arm_breakpoint_size = 0; /* And its size. */ + const gdb_byte *thumb_breakpoint = nullptr; /* Breakpoint pattern for a Thumb insn. */ + int thumb_breakpoint_size = 0; /* And its size. */ /* If the Thumb breakpoint is an undefined instruction (which is affected by IT blocks) rather than a BKPT instruction (which is not), then we need a 32-bit Thumb breakpoint to preserve the instruction count in IT blocks. */ - const gdb_byte *thumb2_breakpoint; - int thumb2_breakpoint_size; + const gdb_byte *thumb2_breakpoint = nullptr; + int thumb2_breakpoint_size = 0; - int jb_pc; /* Offset to PC value in jump buffer. + int jb_pc = 0; /* Offset to PC value in jump buffer. If this is negative, longjmp support will be disabled. */ - size_t jb_elt_size; /* And the size of each entry in the buf. */ + size_t jb_elt_size = 0; /* And the size of each entry in the buf. */ /* Convention for returning structures. */ - enum struct_return struct_return; + enum struct_return struct_return {}; /* ISA-specific data types. */ - struct type *arm_ext_type; - struct type *neon_double_type; - struct type *neon_quad_type; + struct type *arm_ext_type = nullptr; + struct type *neon_double_type = nullptr; + struct type *neon_quad_type = nullptr; /* syscall record. */ - int (*arm_syscall_record) (struct regcache *regcache, unsigned long svc_number); + int (*arm_syscall_record) (struct regcache *regcache, + unsigned long svc_number) = nullptr; }; /* Structures used for displaced stepping. */ @@ -145,7 +180,8 @@ struct gdbarch_tdep sequence) and any scratch words, etc. */ #define ARM_DISPLACED_MODIFIED_INSNS 8 -struct arm_displaced_step_closure : public displaced_step_closure +struct arm_displaced_step_copy_insn_closure + : public displaced_step_copy_insn_closure { ULONGEST tmp[DISPLACED_TEMPS]; int rd; @@ -190,9 +226,9 @@ struct arm_displaced_step_closure : public displaced_step_closure struct { /* If non-NULL, override generic SVC handling (e.g. for a particular - OS). */ + OS). */ int (*copy_svc_os) (struct gdbarch *gdbarch, struct regcache *regs, - arm_displaced_step_closure *dsc); + arm_displaced_step_copy_insn_closure *dsc); } svc; } u; @@ -211,7 +247,7 @@ struct arm_displaced_step_closure : public displaced_step_closure CORE_ADDR insn_addr; CORE_ADDR scratch_base; void (*cleanup) (struct gdbarch *, struct regcache *, - arm_displaced_step_closure *); + arm_displaced_step_copy_insn_closure *); }; /* Values for the WRITE_PC argument to displaced_write_reg. If the register @@ -230,19 +266,20 @@ enum pc_write_style extern void arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to, struct regcache *regs, - arm_displaced_step_closure *dsc); + arm_displaced_step_copy_insn_closure *dsc); extern void arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from, - CORE_ADDR to, arm_displaced_step_closure *dsc); + CORE_ADDR to, + arm_displaced_step_copy_insn_closure *dsc); extern ULONGEST - displaced_read_reg (struct regcache *regs, arm_displaced_step_closure *dsc, + displaced_read_reg (regcache *regs, arm_displaced_step_copy_insn_closure *dsc, int regno); extern void displaced_write_reg (struct regcache *regs, - arm_displaced_step_closure *dsc, int regno, + arm_displaced_step_copy_insn_closure *dsc, int regno, ULONGEST val, enum pc_write_style write_pc); -CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR); +CORE_ADDR arm_skip_stub (frame_info_ptr, CORE_ADDR); ULONGEST arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr, int len, @@ -255,10 +292,10 @@ int arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self); std::vector arm_software_single_step (struct regcache *); int arm_is_thumb (struct regcache *regcache); -int arm_frame_is_thumb (struct frame_info *frame); +int arm_frame_is_thumb (frame_info_ptr frame); extern void arm_displaced_step_fixup (struct gdbarch *, - struct displaced_step_closure *, + displaced_step_copy_insn_closure *, CORE_ADDR, CORE_ADDR, struct regcache *); /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */ @@ -269,7 +306,7 @@ extern int arm_psr_thumb_bit (struct gdbarch *); extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR); extern int arm_process_record (struct gdbarch *gdbarch, - struct regcache *regcache, CORE_ADDR addr); + struct regcache *regcache, CORE_ADDR addr); /* Functions exported from arm-bsd-tdep.h. */ /* Return the appropriate register set for the core section identified @@ -281,11 +318,11 @@ extern void void *cb_data, const struct regcache *regcache); -/* Target descriptions. */ -extern struct target_desc *tdesc_arm_with_m; -extern struct target_desc *tdesc_arm_with_iwmmxt; -extern struct target_desc *tdesc_arm_with_vfpv2; -extern struct target_desc *tdesc_arm_with_vfpv3; -extern struct target_desc *tdesc_arm_with_neon; +/* Get the correct Arm target description with given FP hardware type. */ +const target_desc *arm_read_description (arm_fp_type fp_type, bool tls); + +/* Get the correct Arm M-Profile target description with given hardware + type. */ +const target_desc *arm_read_mprofile_description (arm_m_profile_type m_type); #endif /* arm-tdep.h */