X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=gdb%2Fmips-tdep.h;h=4d2664d42731a8ca984380f759bf18e86efd3503;hb=1d2eeb660f0885807320792ee18c033b34522225;hp=85c40d94898c2020d16c9ceefe5a3ef0333da4f0;hpb=e38d4e1aae6fb86cfae320ae6ae9b2b48cd1ddb7;p=binutils-gdb.git diff --git a/gdb/mips-tdep.h b/gdb/mips-tdep.h index 85c40d94898..4d2664d4273 100644 --- a/gdb/mips-tdep.h +++ b/gdb/mips-tdep.h @@ -1,6 +1,6 @@ /* Target-dependent header for the MIPS architecture, for GDB, the GNU Debugger. - Copyright (C) 2002, 2003, 2007, 2008 Free Software Foundation, Inc. + Copyright (C) 2002-2022 Free Software Foundation, Inc. This file is part of GDB. @@ -20,9 +20,12 @@ #ifndef MIPS_TDEP_H #define MIPS_TDEP_H +#include "objfiles.h" +#include "gdbarch.h" + struct gdbarch; -/* All the possible MIPS ABIs. */ +/* All the possible MIPS ABIs. */ enum mips_abi { MIPS_ABI_UNKNOWN = 0, @@ -38,6 +41,27 @@ enum mips_abi /* Return the MIPS ABI associated with GDBARCH. */ enum mips_abi mips_abi (struct gdbarch *gdbarch); +/* Base and compressed MIPS ISA variations. */ +enum mips_isa + { + ISA_MIPS = -1, /* mips_compression_string depends on it. */ + ISA_MIPS16, + ISA_MICROMIPS + }; + +/* Corresponding MSYMBOL_TARGET_FLAG aliases. */ +#define MSYMBOL_TARGET_FLAG_MIPS16(sym) \ + (sym)->target_flag_1 () + +#define SET_MSYMBOL_TARGET_FLAG_MIPS16(sym) \ + (sym)->set_target_flag_1 (true) + +#define MSYMBOL_TARGET_FLAG_MICROMIPS(sym) \ + (sym)->target_flag_2 () + +#define SET_MSYMBOL_TARGET_FLAG_MICROMIPS(sym) \ + (sym)->set_target_flag_2 (true) + /* Return the MIPS ISA's register size. Just a short cut to the BFD architecture's word size. */ extern int mips_isa_regsize (struct gdbarch *gdbarch); @@ -53,6 +77,8 @@ struct mips_regnum int cause; /* Describes last exception. */ int hi; /* Multiply/divide temp. */ int lo; /* ... */ + int dspacc; /* SmartMIPS/DSP accumulators. */ + int dspctl; /* DSP control. */ }; extern const struct mips_regnum *mips_regnum (struct gdbarch *gdbarch); @@ -66,39 +92,40 @@ enum mips_fpu_type MIPS_FPU_NONE /* No floating point. */ }; -/* MIPS specific per-architecture information */ -struct gdbarch_tdep +/* MIPS specific per-architecture information. */ +struct mips_gdbarch_tdep : gdbarch_tdep { /* from the elf header */ - int elf_flags; + int elf_flags = 0; /* mips options */ - enum mips_abi mips_abi; - enum mips_abi found_abi; - enum mips_fpu_type mips_fpu_type; - int mips_last_arg_regnum; - int mips_last_fp_arg_regnum; - int default_mask_address_p; + enum mips_abi mips_abi {}; + enum mips_abi found_abi {}; + enum mips_isa mips_isa {}; + enum mips_fpu_type mips_fpu_type {}; + int mips_last_arg_regnum = 0; + int mips_last_fp_arg_regnum = 0; + int default_mask_address_p = 0; /* Is the target using 64-bit raw integer registers but only storing a left-aligned 32-bit value in each? */ - int mips64_transfers_32bit_regs_p; + int mips64_transfers_32bit_regs_p = 0; /* Indexes for various registers. IRIX and embedded have different values. This contains the "public" fields. Don't add any that do not need to be public. */ - const struct mips_regnum *regnum; + const struct mips_regnum *regnum = nullptr; /* Register names table for the current register set. */ - const char **mips_processor_reg_names; + const char * const *mips_processor_reg_names = nullptr; /* The size of register data available from the target, if known. This doesn't quite obsolete the manual mips64_transfers_32bit_regs_p, since that is documented to force left alignment even for big endian (very strange). */ - int register_size_valid_p; - int register_size; + int register_size_valid_p = 0; + int register_size = 0; /* Return the expected next PC if FRAME is stopped at a syscall instruction. */ - CORE_ADDR (*syscall_next_pc) (struct frame_info *frame); + CORE_ADDR (*syscall_next_pc) (struct frame_info *frame) = nullptr; }; /* Register numbers of various important registers. */ @@ -108,8 +135,10 @@ enum MIPS_ZERO_REGNUM = 0, /* Read-only register, always 0. */ MIPS_AT_REGNUM = 1, MIPS_V0_REGNUM = 2, /* Function integer return value. */ - MIPS_A0_REGNUM = 4, /* Loc of first arg during a subr call */ + MIPS_A0_REGNUM = 4, /* Loc of first arg during a subr call. */ + MIPS_S2_REGNUM = 18, /* Contains return address in MIPS16 thunks. */ MIPS_T9_REGNUM = 25, /* Contains address of callee in PIC. */ + MIPS_GP_REGNUM = 28, MIPS_SP_REGNUM = 29, MIPS_RA_REGNUM = 31, MIPS_PS_REGNUM = 32, /* Contains processor status. */ @@ -119,15 +148,12 @@ enum MIPS_EMBED_CAUSE_REGNUM = 36, MIPS_EMBED_PC_REGNUM = 37, MIPS_EMBED_FP0_REGNUM = 38, - MIPS_UNUSED_REGNUM = 73, /* Never used, FIXME */ + MIPS_UNUSED_REGNUM = 73, /* Never used, FIXME. */ MIPS_FIRST_EMBED_REGNUM = 74, /* First CP0 register for embedded use. */ MIPS_PRID_REGNUM = 89, /* Processor ID. */ MIPS_LAST_EMBED_REGNUM = 89 /* Last one. */ }; -/* Defined in mips-tdep.c and used in remote-mips.c */ -extern void deprecated_mips_set_processor_regs_hack (void); - /* Instruction sizes and other useful constants. */ enum { @@ -138,18 +164,41 @@ enum }; /* Single step based on where the current instruction will take us. */ -extern int mips_software_single_step (struct frame_info *frame); +extern std::vector mips_software_single_step + (struct regcache *regcache); + +/* Strip the ISA (compression) bit off from ADDR. */ +extern CORE_ADDR mips_unmake_compact_addr (CORE_ADDR addr); + +/* Tell if the program counter value in MEMADDR is in a standard + MIPS function. */ +extern int mips_pc_is_mips (CORE_ADDR memaddr); /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ -extern int mips_pc_is_mips16 (bfd_vma memaddr); +extern int mips_pc_is_mips16 (struct gdbarch *gdbarch, CORE_ADDR memaddr); + +/* Tell if the program counter value in MEMADDR is in a microMIPS + function. */ +extern int mips_pc_is_micromips (struct gdbarch *gdbarch, CORE_ADDR memaddr); -/* Return the currently configured (or set) saved register size. */ +/* Return the currently configured (or set) saved register size. */ extern unsigned int mips_abi_regsize (struct gdbarch *gdbarch); +/* Make PC the address of the next instruction to execute. */ +extern void mips_write_pc (struct regcache *regcache, CORE_ADDR pc); + /* Target descriptions which only indicate the size of general registers. */ extern struct target_desc *mips_tdesc_gp32; extern struct target_desc *mips_tdesc_gp64; +/* Return non-zero if PC is in a MIPS SVR4 lazy binding stub section. */ + +static inline int +in_mips_stubs_section (CORE_ADDR pc) +{ + return pc_in_section (pc, ".MIPS.stubs"); +} + #endif /* MIPS_TDEP_H */