X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=gdb%2Fppc-tdep.h;h=68f3a74eecb377e50f18688ef132157f5dd98ab3;hb=0e1862bb401f47716446aef143b2bf7a4563f541;hp=f523b34a3de33f29bee346f9896998320e9ea7e8;hpb=4a7622d18f7a0e67c53090c685f99ac2c38d0201;p=binutils-gdb.git diff --git a/gdb/ppc-tdep.h b/gdb/ppc-tdep.h index f523b34a3de..68f3a74eecb 100644 --- a/gdb/ppc-tdep.h +++ b/gdb/ppc-tdep.h @@ -1,7 +1,6 @@ /* Target-dependent code for GDB, the GNU debugger. - Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008 - Free Software Foundation, Inc. + Copyright (C) 2000-2015 Free Software Foundation, Inc. This file is part of GDB. @@ -27,15 +26,15 @@ struct value; struct regcache; struct type; -/* From ppc-sysv-tdep.c ... */ +/* From ppc-sysv-tdep.c ... */ enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch, - struct type *func_type, + struct value *function, struct type *valtype, struct regcache *regcache, gdb_byte *readbuf, const gdb_byte *writebuf); enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch, - struct type *func_type, + struct value *function, struct type *valtype, struct regcache *regcache, gdb_byte *readbuf, @@ -54,18 +53,16 @@ CORE_ADDR ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch, struct value **args, CORE_ADDR sp, int struct_return, CORE_ADDR struct_addr); -CORE_ADDR ppc64_sysv_abi_adjust_breakpoint_address (struct gdbarch *gdbarch, - CORE_ADDR bpaddr); - enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch, - struct type *func_type, + struct value *function, struct type *valtype, struct regcache *regcache, gdb_byte *readbuf, const gdb_byte *writebuf); -/* From rs6000-tdep.c... */ +/* From rs6000-tdep.c... */ int altivec_register_p (struct gdbarch *gdbarch, int regno); +int vsx_register_p (struct gdbarch *gdbarch, int regno); int spe_register_p (struct gdbarch *gdbarch, int regno); /* Return non-zero if the architecture described by GDBARCH has @@ -76,6 +73,9 @@ int ppc_floating_point_unit_p (struct gdbarch *gdbarch); Altivec registers (vr0 --- vr31, vrsave and vscr). */ int ppc_altivec_support_p (struct gdbarch *gdbarch); +/* Return non-zero if the architecture described by GDBARCH has + VSX registers (vsr0 --- vsr63). */ +int vsx_support_p (struct gdbarch *gdbarch); int ppc_deal_with_atomic_sequence (struct frame_info *frame); @@ -136,8 +136,16 @@ extern void ppc_supply_vrregset (const struct regset *regset, struct regcache *regcache, int regnum, const void *vrregs, size_t len); +/* Supply register REGNUM in the VSX register set REGSET + from the buffer specified by VSXREGS and LEN to register cache + REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ + +extern void ppc_supply_vsxregset (const struct regset *regset, + struct regcache *regcache, + int regnum, const void *vsxregs, size_t len); + /* Collect register REGNUM in the general-purpose register set - REGSET. from register cache REGCACHE into the buffer specified by + REGSET, from register cache REGCACHE into the buffer specified by GREGS and LEN. If REGNUM is -1, do this for all registers in REGSET. */ @@ -146,7 +154,7 @@ extern void ppc_collect_gregset (const struct regset *regset, int regnum, void *gregs, size_t len); /* Collect register REGNUM in the floating-point register set - REGSET. from register cache REGCACHE into the buffer specified by + REGSET, from register cache REGCACHE into the buffer specified by FPREGS and LEN. If REGNUM is -1, do this for all registers in REGSET. */ @@ -163,7 +171,25 @@ extern void ppc_collect_vrregset (const struct regset *regset, const struct regcache *regcache, int regnum, void *vrregs, size_t len); -/* Private data that this module attaches to struct gdbarch. */ +/* Collect register REGNUM in the VSX register set + REGSET from register cache REGCACHE into the buffer specified by + VSXREGS and LEN. If REGNUM is -1, do this for all registers in + REGSET. */ + +extern void ppc_collect_vsxregset (const struct regset *regset, + const struct regcache *regcache, + int regnum, void *vsxregs, size_t len); + +/* Private data that this module attaches to struct gdbarch. */ + +/* ELF ABI version used by the inferior. */ +enum powerpc_elf_abi +{ + POWERPC_ELF_AUTO, + POWERPC_ELF_V1, + POWERPC_ELF_V2, + POWERPC_ELF_LAST +}; /* Vector ABI used by the inferior. */ enum powerpc_vector_abi @@ -180,6 +206,8 @@ struct gdbarch_tdep int wordsize; /* Size in bytes of fixed-point word. */ int soft_float; /* Avoid FP registers for arguments? */ + enum powerpc_elf_abi elf_abi; /* ELF ABI version. */ + /* How to pass vector arguments. Never set to AUTO or LAST. */ enum powerpc_vector_abi vector_abi; @@ -196,21 +224,26 @@ struct gdbarch_tdep is not present in this variant. */ /* Floating-point registers. */ - int ppc_fp0_regnum; /* floating-point register 0 */ - int ppc_fpscr_regnum; /* fp status and condition register */ + int ppc_fp0_regnum; /* Floating-point register 0. */ + int ppc_fpscr_regnum; /* fp status and condition register. */ /* Multiplier-Quotient Register (older POWER architectures only). */ int ppc_mq_regnum; + /* POWER7 VSX registers. */ + int ppc_vsr0_regnum; /* First VSX register. */ + int ppc_vsr0_upper_regnum; /* First right most dword vsx register. */ + int ppc_efpr0_regnum; /* First Extended FP register. */ + /* Altivec registers. */ - int ppc_vr0_regnum; /* First AltiVec register */ - int ppc_vrsave_regnum; /* Last AltiVec register */ + int ppc_vr0_regnum; /* First AltiVec register. */ + int ppc_vrsave_regnum; /* Last AltiVec register. */ /* SPE registers. */ - int ppc_ev0_upper_regnum; /* First GPR upper half register */ - int ppc_ev0_regnum; /* First ev register */ - int ppc_acc_regnum; /* SPE 'acc' register */ - int ppc_spefscr_regnum; /* SPE 'spefscr' register */ + int ppc_ev0_upper_regnum; /* First GPR upper half register. */ + int ppc_ev0_regnum; /* First ev register. */ + int ppc_acc_regnum; /* SPE 'acc' register. */ + int ppc_spefscr_regnum; /* SPE 'spefscr' register. */ /* Decimal 128 registers. */ int ppc_dl0_regnum; /* First Decimal128 argument register pair. */ @@ -225,16 +258,22 @@ struct gdbarch_tdep /* ISA-specific types. */ struct type *ppc_builtin_type_vec64; + struct type *ppc_builtin_type_vec128; + + int (*ppc_syscall_record) (struct regcache *regcache); }; /* Constants for register set sizes. */ enum { - ppc_num_gprs = 32, /* 32 general-purpose registers */ - ppc_num_fprs = 32, /* 32 floating-point registers */ - ppc_num_srs = 16, /* 16 segment registers */ - ppc_num_vrs = 32 /* 32 Altivec vector registers */ + ppc_num_gprs = 32, /* 32 general-purpose registers. */ + ppc_num_fprs = 32, /* 32 floating-point registers. */ + ppc_num_srs = 16, /* 16 segment registers. */ + ppc_num_vrs = 32, /* 32 Altivec vector registers. */ + ppc_num_vshrs = 32, /* 32 doublewords (dword 1 of vs0~vs31). */ + ppc_num_vsrs = 64, /* 64 VSX vector registers. */ + ppc_num_efprs = 32 /* 32 Extended FP registers. */ }; @@ -260,9 +299,29 @@ enum { PPC_VR0_REGNUM = 106, PPC_VSCR_REGNUM = 138, PPC_VRSAVE_REGNUM = 139, + PPC_VSR0_UPPER_REGNUM = 140, + PPC_VSR31_UPPER_REGNUM = 171, PPC_NUM_REGS }; +/* An instruction to match. */ + +struct ppc_insn_pattern +{ + unsigned int mask; /* mask the insn with this... */ + unsigned int data; /* ...and see if it matches this. */ + int optional; /* If non-zero, this insn may be absent. */ +}; + +extern int ppc_insns_match_pattern (struct frame_info *frame, CORE_ADDR pc, + struct ppc_insn_pattern *pattern, + unsigned int *insns); +extern CORE_ADDR ppc_insn_d_field (unsigned int insn); + +extern CORE_ADDR ppc_insn_ds_field (unsigned int insn); + +extern int ppc_process_record (struct gdbarch *gdbarch, + struct regcache *regcache, CORE_ADDR addr); /* Instruction size. */ #define PPC_INSN_SIZE 4